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Alliance Series 2.1i Quick Start Guide
Introduction Implementation Tools Tutorial Using Software Alliance FPGA Express Interface Notes Mentor Graphics Interface Notes Xilinx Synopsys Interface Notes Viewlogic Interface Notes Using LogiBLOX with Interfaces Instantiated Components Alliance Constraints Configuring Xprinter Glossary
Alliance Series 2.1i Quick Start Guide July 1999
Printed U.S.A.
Alliance Series 2.1i Quick Start Guide
Xilinx logo shown above registered trademark Xilinx, Inc. FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Timing Wizard, TRACE, XACT, XILINX, XC2064, XC3090, XC4005, XC5210, XC-DS501 registered trademarks Xilinx, Inc.
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Xilinx Development System
errors contained herein advise user this text correction such made. Xilinx, Inc. will assume liability accuracy correctness engineering software support assistance provided user. Xilinx products intended life support appliances, devices, systems. Xilinx product such applications without written consent appropriate Xilinx officer prohibited. Copyright 1991-1998 Xilinx, Inc. Rights Reserved.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
About This Manual
This manual provides overview Alliance Series 2.1i Software, including basic tutorial. There also instructions configure your third-party interface tools work with Alliance software flow. This manual targeted user already installed their software online documentation, their user environment variables. Other publications consult related information include Design Manager/Flow Engine Guide Alliance Release Notes Installation Guide.
Additional Resources
additional information, http://support.xilinx.com. following table lists some resources access from this page. also directly access some these resources using provided URLs. Resource Tutorial Description/URL Tutorials covering Xilinx design flows, from design entry verification debugging Current listing solution records Xilinx software tools Search this database using search function Descriptions device-specific design techniques approaches
Answers Database Application Notes
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide
Resource Data Book
Description/URL Pages from Programmable Logic Data Book, which describe devicespecific information Xilinx device characteristics, including readback, boundary scan, configuration, length count, debugging Quarterly journals Xilinx programmable logic users Latest news, design tips, patch information Xilinx design environment
Xcell Journals Tech Tips
Manual Contents
This manual covers following topics. Chapter "Introduction" introduces various features Xilinx software. Chapter "Implementation Tools Tutorial" provides tutorial Xilinx design flow. Chapter "Using Software" looks in-depth capability flexibility Alliance software tools. Appendix "Alliance FPGA Express Interface Notes," covers install start using FPGA Express Alliance 2.1i Software. Appendix "Mentor Graphics Interface Notes," covers Mentor Graphics interface associated libraries. Appendix "Xilinx Synopsys Interface Notes," covers Xilinx Synopsys Interface (XSI) associated libraries. Appendix "Viewlogic Interface Notes," covers Viewlogic interface project libraries. Appendix "Using LogiBLOX with Interfaces," covers LogiBLOX interface associated libraries Appendix "Instantiated Components," includes listing components most frequently instantiated synthesis designs.
Xilinx Development System
Appendix "Alliance Constraints," describes most common constraints apply your design control timing layout Xilinx FPGA CPLD. Appendix "Configuring Xprinter,"provides configuration details Workstation users they print from Xilinx applications. Appendix "Glossary," contains definitions explanations terms used Quick Start Guide.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
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Conventions
This manual uses following typographical online document conventions. example illustrates each typographical convention.
Typographical
following conventions used documents. Courier font indicates messages, prompts, program files that system displays.
speed grade: -100
Courier bold indicates literal commands that enter syntactical statement. However, braces Courier bold literal square brackets Courier bold literal only case specifications, such [7:0]. rpt_del_net= Courier bold also indicates commands that select from menu. File Open
Italic font denotes following items. Variables syntax statement which must supply values edif2ngd design_name References other manuals Development System Reference Guide more information.
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide Emphasis text wire drawn that overlaps symbol, nets connected. Square brackets indicate optional entry parameter. However, specifications, such [7:0], they required. edif2ngd [option_name] design_name Braces enclose list items from which must choose more. lowpwr ={on|off} vertical separates items list choices. lowpwr ={on|off} vertical ellipsis indicates repetitive material that been omitted.
Name QOUT' Name CLKIN'
horizontal ellipsis indicates that item repeated more times. allow block block_name loc1 loc2 locn;
Online Document
following conventions used online documents. Red-underlined text indicates interbook link, which crossreference another book. Click red-underlined text open specified cross-reference. Blue-underlined text indicates intrabook link, which crossreference within book. Click blue-underlined text open specified cross-reference.
Xilinx Development System
Contents
Additional Resources Manual Contents Typographical. Online Document
Chapter
Introduction
Supported Devices. Supported Netlists. Xilinx Development System Tools Features Software Manuals Online Help. Features Software Manuals. Software Manuals Web. Online Help Software Manuals Installing Software Manuals Printing Software Manuals Printing Files. Printing from Online Document Viewer. Third Party Interface Support. Software Installation Licensing. Support Services. Technical Support 1-10 Customer Service 1-10
Chapter
Implementation Tools Tutorial
Installing Tutorial Files Step Creating Implementation Project Design Manager Status Bar. Design Manager Toolbox. Step Specifying Options. Step Translating Design. 2-11 Step Using Constraints Editor 2-13
Alliance Series 2.1i Quick Start Guide July 1999
Aliance Series 2.1i Quick Start Guide Stop Design Processing Flow. 2-14 Starting Flow Engine Translating/Mapping your Design 2-16 Step Mapping Design. 2-17 Step Using Timing Analysis Evaluate Block Delays After Mapping 2-19 Estimating Timing Goals With 50/50 Rule 2-19 Report Paths Timing Constraints Option 2-19 Step Placing Routing Design 2-20 Step Evaluating Post-Layout Timing 2-23 Step Creating Timing Simulation Data 2-23 Step Creating Configuration Data 2-24 Step Using PROM File Formatter 2-26
Chapter
Using Software
Using Xilinx Tools. Xilinx Design Flow. Using Design Manager Creating Project Implementing Your Design Using Flow Engine Translating Your Design Mapping Your Design Placing Routing Your Design. Configuring Your Design. Analyzing Reports with Design Manager Translation Report Report Place Route Report Report. Selecting Options Using Design Constraints. Adding Constraints with Constraints Editor. 3-10 Guiding Design with Floorplanner Files 3-11 Static Timing Analysis 3-12 Static Timing Analysis After 3-12 Static Timing Analysis After Place Route. 3-13 Summary Timing Reports 3-13 Detailed Timing Analysis. 3-14 Creating Simulation Files 3-14 Creating Timing Simulation Data 3-15 Creating Functional Simulation Data 3-16 Downloading Design 3-17
Xilinx Development System
Contents Creating PROM. 3-17 In-Circuit Debugging 3-17 Advanced Implementation Flows 3-17 Re-Entrant Route 3-18 Multi-Pass Place Route. 3-19 Guiding Implementation 3-20 Specifying Guide Design. 3-20 Exact Guide Mode 3-21 Leveraged Guide Mode 3-21
Appendix Alliance FPGA Express Interface Notes
Additional Documentation Alliance FPGA Express/Xilinx Design Flow Installing FPGA Express Entering Design. Simulating Design Timing Constraints Porting Code from FPGA Compiler FPGA Express Using LogiBLOX with FPGA Express
Appendix Mentor Graphics Interface Notes
Additional Documentation Setting Xilinx/Mentor Interface. Mentor/Xilinx Software Design Flow Translating Design Xilinx EDIF Timing Simulation. Generating Timing-Annotated EDIF Netlist. Generating Timing Model. Running PLD_QuickSim Mentor Interface Environment Variables. Library Locations Sample Location Map. Locking. Timing Constraints
Appendix Xilinx Synopsys Interface Notes
Documentation Setting Synopsys Interface. Setting Simulation Libraries. Compiling Libraries. Compiling Simulation Libraries Examples Synopsys Setup Files. XC4000 Devices
Alliance Series 2.1i Quick Start Guide
Aliance Series 2.1i Quick Start Guide Example .synopsys_dc.setup File Example .synopsys_vss.setup File. Example Script File XC4000E/EX/XL/XV Designs Virtex Devices Example .synopsys_dc.setup File Example Script File Virtex Devices. Entity Coding Examples C-12 VHDL C-12 Verilog Code: Module Example C-14 Comments About Code. C-15
Appendix Viewlogic Interface Notes
Documentation Setting Viewlogic Interface Workstations Setting Viewlogic Interface Setting Project Libraries Workstation Xilinx Commands ViewDraw. Assigning Location. Timing Constraints
Appendix Using LogiBLOX with Interfaces
Documentation Setting LogiBLOX Workstation Mentor Interface Environment Variables. Synopsys Interface Environment Variables Viewlogic Interface Environment Variables. Setting LogiBLOX Viewlogic Environment Variables PCs. Starting LogiBLOX Using LogiBLOX Schematic Design Creating LogiBLOX Module Design Simulation Copying Modules Using LogiBLOX Synthesis Design Instantiating LogiBLOX Module Analyzing LogiBLOX Module Mentor QuickHDL Synopsys Viewlogic Vantage Modelsim
Xilinx Development System
Contents VHDL Designs Verilog Designs. LogiBLOX Modules
Appendix Instantiated Components
STARTUP Component. STARTBUF Component. BSCAN Component READBACK Component. ROM. Global Buffers Fast Output Primitives. Components. Clock Delay Components. F-11
Appendix Alliance Constraints
Entering Design Constraints Adding Constraints with Constraints Editor. Using Global Translating Merging Logical Designs Constraining LogiBLOX RAM/ROM with Synopsys Estimating Number Primitives Used Naming Primitives Referencing LogiBLOX Module Referencing LogiBLOX Module Primitives. FPGA/Design Compiler Express Verilog Examples. Test.v Example Inside.v Example Memory.v Example (FPGA/Design compiler only) Runscript Example (FPGA/Design compiler only) Test.ucf Example (FPGA/Design compiler only) Test.ucf Example (FPGA Express only) FPGA/Design Compiler Express VHDL Examples Test.vhd Example Inside.vhd Example G-10 Runscript Example (FPGA/Design compiler only) G-10 Test.ucf Example (FPGA/Design compiler only) G-11 Test.ucf Example (FPGA Express only) G-11
Appendix Configuring Xprinter
Required Wind/U Files Configuring .WindU
Alliance Series 2.1i Quick Start Guide
Aliance Series 2.1i Quick Start Guide Printer Information Files Unix Print Command. Configuring Wind/U Printing Defining Port Define Port Modify Existing Port. Matching Printer Type Defined Port. Remove Installed Printer Specifying Default Printer Specify Default Printer. Setting Printer Options. Sending Output File H-10 Solving Printing Problems H-11
Appendix Glossary
aliases attribute AutoRoute block. component constraint. Constraints Editor. DC2NCF. guided mapping. Implementation Tools. file. LCA2NCD LogiBLOX. locking Logic Block Editor macro file. file. File. file. file. file File NGDAnno. file. NGD2EDIF
Xilinx Development System
Contents NGD2VER. NGD2VHDL. NGDBuild file. file (Place Route). path delay. file physical Design Rule Check (DRC) physical macro pinwires route route-through. states. TRCE file wire. file
Alliance Series 2.1i Quick Start Guide
Aliance Series 2.1i Quick Start Guide
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Xilinx Development System
Chapter
Introduction
This chapter contains basic information about Alliance 2.1i Software components, along with listing Xilinx Devices that supported software. complete information about features this software release, refer "What's New" file included your Alliance Implementation Tools CD-ROM. This chapter contains following sections. "Supported Devices" "Supported Netlists" "Xilinx Development System Tools Features" "Software Manuals Online Help" "EDA Third Party Interface Support" "Software Installation Licensing" "Support Services"
Note: Complete software installation information located Alliance 2.1i Release Notes Installation Guide.
Supported Devices
Alliance 2.1i Software supports following device families. XC3000A/L XC3100A/L XC4000E/L/EX/XL/XV/XLA XC5200
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide XC9500/X Spartan/XL/II Virtex/E
Refer Programmable Logic Data Book more information these devices. online version Data Book http:// updated information regarding speed grades package support, search Xilinx Answers Database latest Application Notes. search Xilinx Technical Documentation http://
Supported Netlists
must Xilinx Unified Libraries create your designs. Refer Xilinx Libraries Guide list components. following table lists netlist formats supported Xilinx software. Netlist Format EDIF Variations SEDIF, EDN, EDF, EDIF SXNF, XFF, XTF,
Xilinx Development System Tools Features
This section lists tools main features Xilinx software. tutorial this manual provides brief overview these software tools.
Xilinx Development System
Introduction detailed information using following Xilinx tools, refer appropriate online software manual. Table Feature Design Manager Xilinx Software Tools Description level software module Xilinx Development System. Design Manager provides access tools need read file from design entry tool implement Xilinx device. Displays executes steps needed implement Xilinx design, including translating design netlists; mapping logic CLBs; placing routing designs; creating configuration file downloading device; creating static timing reports; creating timing simulation netlists VHDL (Vital), Verilog, EDIF, XNF. Graphical tool used create high-level modules, such counters, shift registers, multiplexers. CORE Generator system been integrated into Alliance 2.1i Software interface. CORE Generator tool generates delivers parameterizable cores optimized Xilinx devices. Graphical tool used control placement your design into target FPGA using "drag drop" paradigm with mouse pointer. Graphical tool used after running NGDBuild timing constraints locations. Graphical tool used display configure your designs before after placing routing. Used download your design device, verify downloaded configuration, display internal states programmed device. Creates files serial byte-wide configuration PROMs. Three formats available: MCS, EXO, TEK. format also supported microprocessor-based configuration.
Flow Engine
LogiBLOX CORE Generator
Floorplanner
Constraints Editor FPGA Editor Hardware Debugger
PROM File Formatter
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
Table Feature Timing Specification Performance Multi-Pass
Xilinx Software Features Description
Xilinx software supports timing-driven placement routing. place route (PAR) software allows multiple place route iterations single machine, UNIXnetwork, multiple machines running parallel. This feature provides optimum performance efficiency, utilizing time achieve faster design results. Re-entrant routing skips placement routes your design. Routing begins with existing placement routing left place. select previously mapped, routed, fitted implementation revision guide implementation.
Re-Entrant Routing
Guide Incremental Design Changes
Software Manuals Online Help
Xilinx provides software user manuals online help tools associated software interfaces. access online help from Help Help Topics pull-down menu option each software tool. following sections provide more information about accessing using Software Manuals Online.
Features Software Manuals
Xilinx Software Manuals provided your Documentation CD-ROM. install software manuals locally, read them from CD-ROM, read them Xilinx site. Easy print options also available. web-compatible documentation includes powerful search functions viewed using your Java compatible internet browser. Note: best performance, Xilinx recommends version higher either Netscape Navigator Microsoft Internet Explorer browsers.
Xilinx Development System
Introduction
Software Manuals
2.1i Series Software Manuals accessible from Xilinx Support site following location. Bookmark this link easy future use, your Favorites list.
Online Help Software Manuals
Online help instructions reading, browsing, searching online manuals available through browser interface. Click Help button upper left-hand corner documentation viewer browser window access help topics. Note: web-compatible documentation will appear same whether access manuals locally (from CD-ROM) through site.
Installing Software Manuals
Complete directions installing online Software Manuals Alliance Implementation tools software located Alliance 2.1i Release Notes Installation Guide. order documentation viewer, must have Javaenabled browser installed your system network. During Alliance Implementation Tools installation, specify path your current browser install Netscape Navigator 4.0.5. have options installing Software Manuals. Install Manuals locally network location Access Manuals through
Xilinx recommends that install online manuals locally fastest access. install manuals, will able access them using Help Online Documentation pull-down menu command Design Manager other Xilinx tools. wish save space your local drive, choose access manuals through instead installing them. information about printing software manuals, "Printing Software Manuals" section.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide When read Software Manuals first time, "Java Security" window appear. This window requesting additional permissions Docsan, Java application used view software manuals. Select Grant button allow Docsan access your hard disk. Warning: must grant this permission view software manuals. your security, Docsan Java applet digitially signed Sidana Systems, Inc. using certificate from Verisign.
Printing Software Manuals
print entire Xilinx software manuals with graphics text inline. format files each software manuals provided 2.1i Software Documentation CD-ROM.
Printing Files
access print using files, following steps. Verify that have Adobe Acrobat Reader (version above) installed your network local area. install Acrobat from Alliance 2.1i Implementation tools software CD-ROM selecting Core Generator option. Start Acrobat Reader Unix users following command start this tool. Path_to_directory directory where your Acrobat program files located. users Select Start Programs Acrobat Reader Insert Xilinx 2.1i Software Documentation CD-ROM into your drive. Access your CD-ROM directory. Unix users
Xilinx Development System
Introduction Enter where path_to_CD-ROM_directory your mounted CD-ROM drive. Enter command view contents CD-ROM directory. users Select Start Programs Windows Explorer select your CD-ROM drive display contents CDROM. Open Print directory folder from CD-ROM contents. This directory contains files. Select book open Acrobat. following table lists book titles their corresponding file names. Table List Alliance 2.1i Software Manuals Manual Title Xilinx/Concept-HDL Interface Guide Constraints Editor Guide CPLD Schematic Design Guide CPLD Synthesis Design Guide Design Manager/Flow Engine Guide Development System Reference Guide FPGA Editor Guide Floorplanner Guide Hardware Debugger Guide Hardware User Guide JTAG Programmer Guide Libraries Guide LogiBLOX Guide Mentor Graphics Interface Guide PROM File Formatter Guide Alliance Series 2.1i Quick Start Guide Synthesis Simulation Design Guide File Name docchdl.pdf cst_edit.pdf sdg_alli syn_cpld dmfe.pdf dev_ref.pdf fpedit.pdf fplan.pdf hdebug.pdf huguide.pdf jtag.pdf libguide.pdf lblox.pdf mentor.pdf prom_fmt.pdf docaqsg.pdf gensim.pdf
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide Table List Alliance 2.1i Software Manuals Manual Title Synopsys Synthesis Simulation Design Guide Xilinx/Synopsys Interface Guide Timing Analyzer Guide Viewlogic Interface Guide File Name xsisyn.pdf xsi_int.pdf timing.pdf vlifg.pdf
Print book using File Print command from Adobe Acrobat reader window.
Printing from Online Document Viewer
print individual pages Software Manuals directly from your internet browser window. example, Netscape users would File Print Frame menu option from their browser window. (Make sure that have clicked right-hand book view frame order select printing.) Xilinx recommends that online books quick information access searching, files best print quality. Graphics web-based manuals inline will print automatically. They also sized optimal online viewing printed page. have access your Documentation CD-ROM, also access Software Manuals format Web. each manual your local area. Note: This process slower than accessing files directly from your CD-ROM.
Third Party Interface Support
Alliance 2.1i software supports various third party interfaces. most current information latest vendor version support Alliance partner program, refer http://www.xilinx.com/ programs/alliance/alligen.htm. Software manuals interface users provided your software documentation CD-ROM. also access manuals web, from support.xilinx.com.
Xilinx Development System
Introduction Several Appendixes this manual provide information your vendor tools interface with Alliance 2.1i software.
Software Installation Licensing
Complete software installation instructions located Alliance 2.1i Release Notes Installation Guide. When install software, will asked provide your CDKEY. This instructs installation program load software package that purchased. Your CD-KEY, which typically starts with letters "AB" "AS," located sticker back CD-ROM holder. will also asked provide your software serial number during software installation. This number helps technical customer support team assist more efficiently. This also ensures that will eligible receive free software updates they become available. Xilinx users, this "SN" number located sticker back your CD-ROM holder. current Xilinx customer, your serial number will appear mailing label your shipping package. need license Alliance 2.1i software. However, must registered user Xilinx Customer Service database order receive full benefits your customer technical support. have registered your sofware, this online http://www.support.xilinx.com. installation, Xilinx software users should select "Online Registration" option Register Web. Alternatively, could fill Xilinx registration card mail your Customer Service location. only need register your software once. This will ensure that receive future updates (during your warranty period) future product information.
Support Services
This section provides information contacting your technical support customer service representatives.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
Technical Support
experience problems with your software installation operation look solutions answers http:// support.xilinx.com. Xilinx technical support site also provides forms easily submitting your technical questions email. access these forms, "Services" area support.xilinx.com click "Open Case" link. need additional support, contact Xilinx Technical Support hotline phone fax. When faxing inquiries, provide your complete name, company name, phone number, along with software version using. Location North America United Kingdom France Germany Japan Korea Hong Kong Taiwan Corporate Switchboard Telephone 1-408-879-5199 1-800-255-7778 44-1932-820821 33-1-3463-0100 49-89-93088-130 local distributor local distributor local distributor local distributor 1-408-559-7778 Facsimile (Fax) 1-408-879-4442 44-1932-828522 33-1-3463-0959 49-89-93088-188 local distributor local distributor local distributor local distributor
Customer Service
This section provides information contacting your local Xilinx Customer Service representative. Contact your local distributor international countries listed. offices Canada open Monday through Friday from 8:00 5:00 Pacific time. European offices open Monday through Friday from 9:00 through 5:30 United Kingdom time. These offices Englishspeaking only.
1-10
Xilinx Development System
Introduction
Country United States Canada United Kingdom Belgium France Germany Italy Netherlands Other European Locations Japan
Telephone 1-800-624-4782 01932-333550 0800 73738 0800 918333 0130 816027 1677 90403 0800 0221079 (44) 1932-333550 3297 9153
Facsimile 408-559-0115 01932-828521
(44) 1932-828521 3297 9189
Alliance Series 2.1i Quick Start Guide
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Alliance Series 2.1i Quick Start Guide
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Xilinx Development System
Chapter
Implementation Tools Tutorial
This chapter contains user instructions tutorial that covers many functions Alliance 2.1i Implementation Tools. Using this tutorial good user learn Alliance design flow works with basic designs. Note: updated version this tutorial will available after July 7th, 1999 from Xilinx Support site well AppLINX site location techsup/tutorials/index.htm. Contact your local sales representative obtain copy AppLINX This chapter contains following sections. "Installing Tutorial Files" "Step Creating Implementation Project" "Step Specifying Options" "Step Translating Design" "Step Using Constraints Editor" "Step Mapping Design" "Step Using Timing Analysis Evaluate Block Delays After Mapping" "Step Placing Routing Design" "Step Evaluating Post-Layout Timing" "Step Creating Timing Simulation Data" "Step Creating Configuration Data" "Step Using PROM File Formatter"
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide
Installing Tutorial Files
This tutorial demonstrates Alliance Series Design Implementation Tools flow. front design already been compiled Interface tool described EDIF Netlist File (EDF). listing Interface tutorials, please reference Xilinx Support area referenced beginning this chapter. This tutorial passes input netlist from front tool back-end Alliance Series 2.1i Design Implementation Tools, then incorporates placement constraints through User Constraints File (UCF). Timing constraints will added later through Constraints Editor. tutorial design, titled "Watch," designed perform like track coach's stopwatch. There inputs system (RESET SRTSTP). configuration clock device used hertz (HZ) clock signal. Three seven-bit outputs generated this system output three seven-segment displays. Before proceeding Step tutorial, create working directory with tutorial files follows. Create empty working directory named Watch. Copy following files from $XILINX/userware/tutorial/ qstart/ directory into your newly created working directory.
following table lists relevant file names description. File Name watch.edn tenths.ngc watch.ucf Description Input netlist file (EDIF) LogiBLOX implementation file User constraints file
Note: order /userware/tutorial/qstart directory present your root Xilinx directory, must first install Userware Tutorial files from Alliance Series Design Implementation Tools CD-ROM.
Step Creating Implementation Project
Design Implementation Tools organized under single program called Design Manager. Design Manager helps
Xilinx Development System
Implementation Tools Tutorial manage design flow process keeping track design versions implementation revisions within each version. Design Manager also provides access entire suite Xilinx implementation tools needed complete design. While Design Manager manages your Xilinx design, Flow Engine actually implements Flow Engine closely integrated with Design Manager shares many same menus dialog boxes. begin, following steps create implementation project. workstation, enter following start Design Manager. xilinx select following start Design Manager. Start Programs Xilinx Design Manager When open Design Manager first time, must create project your design. project includes design versions, implementation revisions, reports, other Xilinx data created while work with design. Design Manager graphically displays information about these items project view. When create project, specify design open directory project. create many projects want, only work with time. Select File Project from Design Manager menu create implementation project tutorial design. Project dialog appears. fields this dialog described following table. Table Project Dialog Fields Description level netlist file containing design definition
Field Input Design
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide Table Project Dialog Fields Description Directory used store implementation data created design compiled Enter optional notation design this field
Field Work Directory Comment
specify your input design, click Browse button right Input Design field. Browse dialog appears shown following figure.
Figure Browse Dialog Select appropriate file type from drop-down list Files Type field. this tutorial design, EDIF selected. Select Watch design file. file name appears File Name field. Click Open. Browse dialog closes Project dialog updated include specified input netlist. default, Work Directory field directory containing input design. preferred, this another directory. Because
Xilinx Development System
Implementation Tools Tutorial files were previously copied Watch directory, this directory used implementation project resulting output files. Comment field, enter following. -tutorial Click close Project dialog box. Version dialog appears, shown following figure.
Figure Version Dialog When initially creating your project, Version dialog automatically appears allow enter information
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide necessary define design version. Furthermore, time that your input netlist changes change made within your front-end tool, prompted Design Manager generate design version. Once design version created, different implementation strategies your design. data associated with each these implementation strategies called implementation revision. Because implementation revision automatically created when create version, will both these fields already defined Version dialog. default, Version Name field shows ver1 default version, Revision Name field shows rev1 default revision. Comments note options strategies entered Version Revision Comment fields. Click Select display Part Selector dialog box. Part field will automatically contain part number specified target device your design entry tool. Since this field empty example, must define
Figure Part Selector Dialog drop-down lists fields Part Selector dialog enter Family, Device, Package, Speed Grade design. This design targets XC4003E-3-PC84. Click part number appears Part field Version dialog box.
Xilinx Development System
Implementation Tools Tutorial Copy Persistent Data heading allows specify copying constraint, guide, floorplan data revision that about created. choose copy data from previous revision custom file choose None want copy data. this tutorial, will keep drop-down boxes defined None. Note: default, Design Manager copies floorplan constraints file data from "last" revision. "last" revision bottommost revision Design Manager project view. When initially creating project, Design Manager copies constraints floorplan file data happens exist), from project directory revision directory. Click Version dialog box. Design Manager loads your design displays design version implementation revision icon project view, shown following figure.
Figure Watch Project Design Manager
Design Manager Status
bottom Design Manager window status bar. status lists current project, target device, currently selected version/revision pair. left-hand portion status provides help what currently selected your cursor, shown following figure.
Figure Design Manager Status
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Alliance Series 2.1i Quick Start Guide
Design Manager Toolbox
toolbox, located right side Design Manager window, becomes active when revision selected. Icons toolbox (shown following figure) represent Flow Engine, Timing Analyzer, Floorplanner, PROM File Formatter, Hardware Debugger, FPGA Editor, JTAG Programmer tools. Note: toolbar drag drop capability.
Figure Design Manager Toolbox
Step Specifying Options
implementation revision contains data files reports that created based specific implementation strategies. Implementation strategies defined specifying options. specify options that control Flow Engine implements design, creates timing simulation data, creates netlist files, generates reports, creates configuration data. options available depend target device family. tools create many implementation revisions want design version. example, want various implementation strategies netlist, several revisions created single design version. default, however, Design Manager recompiles within current revision. Within Design Manager, notice project view displays rev1 under initial version watch project. status revision noted (New, OK). refers state design updated throughout tutorial different compilation stages completed. status current state indicates errors design processing. following steps specify options this design. Select Design Options open Options dialog shown following figure.
Xilinx Development System
Implementation Tools Tutorial
Figure Options Dialog This dialog allows options used implementation, simulation, configuration flow. Changes made this dialog apply selected implementation revision. dialog above appears targeting FPGA. slightly different Options dialog would appear were targeting CPLD. Select Help button read through information regarding this entire dialog box. Select Edit Options next Implementation Program Option. XC4000 Implementation Options dialog displayed shown following figure. implementation options control software maps, places, routes, optimizes design.
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Alliance Series 2.1i Quick Start Guide
Figure XC4000 Implementation Options Dialog Select Timing Reports tab. Select Produce Logic Level Timing Report. option produce Post Layout Timing Report should already selected default. both reports, select Report Paths Timing Constraints. timing reports useful evaluating design performance. They will analyzed detail later this tutorial. Click save Implementation options return Options dialog. Select from drop down list next Configuration Program Options. This disables generation bitstream design. will revisit this option later once have completed evaluating performance design. Click exit Options dialog box.
previously mentioned, implementation revision created based specific implementation strategies. addition program options just set, implementation strategy defined constraints applied onto design. this design, were initially asked copy over User Constraints File (UCF) into your design directory. Since Design Manager default copies over your constraints information into revision created, should able open watch.ucf file found under your newly created rev1 directory. With text editor, view location constraints that specified this design. User Constraints File (UCF) provides mechanism constraining logical design without returning design entry tools. However, requires user understand exact syntax needed define constraints. other hand, Constraints Editor graphical tool Xilinx Development System that allows enter timing location constraints. will take
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Implementation Tools Tutorial advantage this tool only view constraints specified currently watch.ucf file, also some timing constraints own. continue with tutorial, select following from within Design Manager. Utilities Constraints Editor will prompted Translate step before launching this Utility. following step covers steps needed effectively translate your design.
Step Translating Design
Design Manager manages files created during implementation process while Flow Engine controls implementation process itself. programs Flow Engine settings supplied user options dialog box. Flow Engine gives complete control over design processed. Typically, should your options first, then through entire flow selecting "Implement" from Design Menu. this tutorial, attempting further define design setting constraints after having defined options. stated previously, order invoke Constraints Editor, must first Translate step. Select continue with flow. Flow Engine invoked first time. steps design flow graphically represented upper half Flow Engine window. status each stage also shown. Refer following figure.
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Alliance Series 2.1i Quick Start Guide
Figure Translating Design Notice "STOP" sign placed between Translate steps. This breakpoint been automatically this situation instruct Flow Engine stop after Translate step complete. During translation, program NGDBuild executed, performs following functions. Converts input design netlists writes results single merged netlist. merged netlist describes logic design well location timing constraints. Performs timing specification logical design rule checks Adds User Constraints File (UCF) merged netlist
Once complete, Flow Engine shuts down Constraints Editor invoked.
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Implementation Tools Tutorial
Step Using Constraints Editor
Constraints Editor utility that allow edit constraints previously defined (through file), well constraints your design. Input files Constraints Editor include following. (Native Generic Database) file. This file serves input mapper, which then outputs physical design database, (Native Circuit Description) file. Corresponding (User Constraint File).
default, when file opened, existing file with same base name file used. Alternatively, specify name file. Upon successful completion, Constraints Editor writes valid file. NGDBuild uses file, along with design source netlists produce newer file that incorporates changes made. then read program (the next step design flow). design, watch.ngd file watch.ucf file automatically read into Constraints Editor. Global appears foreground Constraints Editor window. This window automatically displays clock nets your design, allows define associated period, setup, and/or clock values. Select Period cell associated with clock oscout. Double-click your left mouse button. This invokes Clock Period dialog box. Within Clock Signal Definition, keep default (Specific Time) selected define explicit period clock rather designate period which relative another timing specification. Enter value Time text box. Verify that selected from Units pull-down list. Click Notice that period cell updated with global clock period constraint just defined (with default duty cycle) Note: purpose this tutorial, invoked secondary dialog double-clicking cell specify constraint values.
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Alliance Series 2.1i Quick Start Guide feature Constraints Editor 2.1i allows direct entry constraints into cells simply clicking once. Select Ports from Constraints Editor's main window. left hand side displays listing current ports defined user. Notice that certain cells Location column pre-populated with device pins locking down ports actual pins target device. This information obtained Constraints Editor watch.ucf file read Select File Save. change made within Constraints Editor saved into watch.ucf file your current revision directory. will prompted with reminder rerun Translate step. Click Select File Exit
Note: Make sure read following procedure before starting your design.
Stop Design Processing Flow
Before continue implementing design Flow Engine, review following procedure stopping processing design after step. Warning: Because steps tutorial design often finish quickly, should familiar with this procedure before start Flow Engine. Setting break point anywhere design process useful when want stop evaluate your performance before going forward. example, setting breakpoint after Translate step useful when want perform functional simulation design copy resulting design.ngd file your working directory. After copying design.ngd file, appropriate NGD2XXX program file create functional simulation data. more information NGD2XXX programs, appropriate chapter Development System Reference Guide. Note: This procedure utilized time Flow Engine stop after steps design flow.
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Implementation Tools Tutorial this tutorial, want stop processing design after step. this, must break point stop Flow Engine. stop after step from within Flow Engine, click stop sign toolbar icon while running. Stop After dialog displayed with default setting Configure shown following figure. list displays break points appropriate current state design. Because design completed processing this point, possible break points listed.
Figure 2-10
Stop After Dialog
Select list click stop sign added design flow between Place Route steps shown following figure.
Note: status bottom Flow Engine window will updated with specified user constraints file (watch.ucf).
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Figure 2-11
Mapping Design
Starting Flow Engine Translating/Mapping your Design
that implementation strategies have been defined (options constraints), let's continue with implementation design. Select Design Implement from Design Manager. Flow Engine automatically detects that changes were made your constraints file, which requires Translate step rerun. order changes just made Constraints Editor take affect, select YES. Perform procedure previously described "How Stop Design Processing Flow" section stop processing design.
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Step Mapping Design
this point, input netlist being translated (once again), merged into single design file. Furthermore, design will mapped into CLBs IOBs. After mapping, design will placed routed. final step design flow Configure step which configuration bitstream created downloading target device formatting into PROM programming file. performs following functions: Allocates resources basic logic elements design Processes location timing constraints, performs target device optimizations, runs design rule check resulting mapped netlist.
After step done, Flow Engine shuts down Implement Status dialog appears, shown following figure.
Figure 2-12
Implement Status Dialog
following steps show report browser. Select Reports invoke Report Browser window. Translation Report appears first report generated. Report Logic Level Timing Report files created result stage completing. reports that have been read denoted with gold star upper left corner file icon, shown following figure.
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Figure 2-13
Report Browser after Running
Double-click report review output. following table lists types reports describes their contents. following table lists types reports available you. Report Browser Reports Description Includes warning error messages from translation process. Includes information target device resources allocated, references trimmed logic, device utilization. detailed information report, refer Development System Reference Guide. Provides summary analysis your timing constraints based block delays estimates route delays. This report produced after prior (Place Route).
Table
Report Translation Report Report
Logic Level Timing Report
Select close Implement Status dialog. Keep Report Browser open now. will evaluating some these reports further detail next section.
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Implementation Tools Tutorial Notice that Design Manager project view displays status revision (Mapped, OK). "Mapped" refers state design updated throughout tutorial different compilation stages completed. "OK" refers status current state indicates errors design processing. design been mapped target architecture. next step involves checking design paths block delays.
Step Using Timing Analysis Evaluate Block Delays After Mapping
After design mapped, Logic Level Timing Report evaluate logical paths design. Because design placed routed yet, actual routing delay information available. timing report describes logical block delays estimated routing delays. delays that provided based optimal distance between blocks (also referred unplaced floors).
Estimating Timing Goals With 50/50 Rule
preliminary idea realistic your timing goals evaluating design after stage. rough guideline (known 50/50 rule) specifies that block delays single path make approximately total path delay after design routed. example, path with 10ns block delay should meet 20ns timing constraint after placed routed. your design extremely dense, using architecture with fewer routing resources (for example, 4025E device versus 4028XL), your delays more than total path delay.
Report Paths Timing Constraints Option
Because timing constraints were defined this tutorial design, Report Paths Timing Constraints option selected. This option forces Logic Level Timing Report provide period path analysis constraints specified. Taking look report, period timing constraint listed top, minimum period obtained tools after mapping. Because limited report path timing constraint, breakdown single path
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Alliance Series 2.1i Quick Start Guide that contains levels logic. Notice percentage block (logic) delay versus routing delay this calculation. unplaced floors listed estimates (indicated letter next delay) based optimal placement blocks. generate Logical Level Timing Report, still processes design based relationship between block delays, floors, timing specifications design. example, PERIOD constraint specified path, there block delays unplaced floor delays stops generates error message. this example, fails because determines that total delay greater than constraint placed design ns). Logic Level Timing Report determine timing violations that occur prior running PAR.
Step Placing Routing Design
After mapped design evaluated verify that block delays reasonable given design specifications, design placed routed. Flow Engine perform following place route algorithms. Timing Driven with timing constraints specified from within input netlist from constraints file Non-Timing Driven ignore timing constraints
this tutorial, timing driven placement timing driven routing automatically performed because timing constraints specified this design. Close Report Browser open reports. place route design, perform following procedure. Design Manager window, select Design Implement continue running implementation flow. Flow Engine will once again invoked. Status:OK message upper right corner indicates that errors generated this point. Refer following figure:
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Implementation Tools Tutorial
Figure 2-14
Placing Routing Design
Review reports generated make sure place route process finished expected. four reports created Report Browser Place Route Report, Report, Asynchronous Delay Report, Post-Layout Timing Report, shown following figure described following table.
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Figure 2-15 Table
Reports Available After Place Route Description Reports Available After Place Route Description Provides device utilization delay summary. this report verify that design successfully routed that timing constraints were met. Contains report location device pins. this report verify that pins locked down were placed correct location. Lists nets design delays loads net. Incorporates both logic routing delays generate evaluation design's timing constraints, clock frequencies, path delays.
Report Place Route Report
Report
Asynchronous Delay Report Post-Layout Timing Report
Note: Design Manager window, status current version/revision (Routed, OK).
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Step Evaluating Post-Layout Timing
After design placed routed, Post Layout Timing Report generated default verify that design meets your specified timing goals. This report evaluates logical block delays routing delays. delays reported actual routing delays after place route process (indicated letter next delay). Double-click Post Layout Timing Report open Following summary this report. minimum period value increased actual routing delays. After step, logic delay contributed about minimum period attained. post-layout report indicates that logical delay value decreased somewhat. total unplaced floors estimate changed well. Routing delay after equals about period; true report delays after place route step. post-layout result does necessarily follow 50/50 rule previously described because worst case path includes primarily component delays. After design mapped, block delays constituted about period. After place route, majority worst case path still made logic delay. Since total routing delay makes only small percentage total path delay, spread across three nets, expecting this reduced further unrealistic. general, reduce excessive block delays improve design performance decreasing number logic levels design.
Step Creating Timing Simulation Data
After your design placed routed timing statically verified, next step create timing simulation data. create timing simulation data, perform following steps Design Manager. Select Design Options open Options dialog box. Select simulator that corresponds your design entry tool from Simulation drop-down list Program Options section dialog box.
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Alliance Series 2.1i Quick Start Guide Click close Options dialog box. Select Design Implement from Design Manager Within Flow Engine, will notice stage appear directly after Place Route. This stage, called Timing(Sim), solely dedicated producing timing simulation data. tutorial, this stage appear originally because Program Option Simulation selected specific simulator initial pass. default, this option OFF. designs, have choice selecting options beginning design processing, coming back them later. During Timing(Sim) step, Flow Engine runs NGDAnno program create back-annotated file. file then used input NGD2XXX programs produce preferred simulation file format. default, files created named time_sim. make easy find output files your third-party simulation environment, files automatically copied your working directory.
Step Creating Configuration Data
next step creating configuration data. This step includes creating bitstream target device running configure step, follows: Select Design Options open Options dialog box. Select Default from drop-down list Configuration Program Options. Click Edit Options button corresponding Configuration, which just became enabled with selection Default. XC4000 Configuration Options dialog appears. configuration templates options that define initial configuration parameters, start-up sequence, readback capabilities, other advanced features. this tutorial, configuration file created that used programming, verifying, debugging XC4000E designs. Configuration tab, verify that PullUp selected next Done pin, that Perform During Configuration option selected.
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Implementation Tools Tutorial Select Readback tab, verify that CCLK selected readback clock. Click close XC4000 Configuration Options dialog box. Click close Options dialog box. Select Design Implement from Design Manager. Flow Engine comes running BitGen program newly added Configure stage. BitGen creates design_name.bit design_name.ll files this tutorial, watch.bit watch.ll files). design_name.bit file actual configuration data. design_name.ll file logical allocation file that used during hardware debugging determine location probable points design. These files automatically copied your working directory. Verify that they your working directory. more information device readback, please refer latest version Watch Design Hardware Verification Tutorial, located tutorials/index.htm. following figure shows Flow Engine window after configure step finished.
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Figure 2-16
Configuring Design
Flow Engine saves configuration options BitGen Report. Review report using Report Browser. Verify that specified options were used when creating configuration data.
Step Using PROM File Formatter
going program single device using Hardware Debugger, need design.bit file. going program several devices daisy chain configuration, program your devices using PROM, must PROM File Formatter (PFF) create PROM file. PROM File Formatter accepts number bitstreams creates more PROM files containing more daisy chain configurations.
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Implementation Tools Tutorial start PROM File Formatter, click PROM File Formatter icon toolbox Design Manager. starts with default PROM that matches currently selected (configured) revision. this point, additional bitstreams daisy chain; create additional daisy chains; remove current bitstream start over; immediately save current PROM file configuration. status bottom window displays PROM format, data format, current PROM size, percentage selected PROM used current PROM configuration. currently selected PROM XC1765D. 53,984 bits data required hold configuration bitstream XC4003E target device this tutorial. determined that XC1765D correct PROM because hold 65,536 configuration bits full). right half window directory structure used locating bitstreams. Only files with .BIT extension shown list. detailed information using PROM File Formatter create daisy chains complex PROM configurations, PROM File Formatter Guide. This tutorial describes save default PROM file. Select File PROM Properties open PROM Properties dialog box, shown following figure.
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Figure 2-17
PROM Properties Dialog with Single PROM
Select following options this dialog box. PROM File Format from drop-down list PROM Type Number PROMS used hold data have more data than space available PROM, must split data into several individual PROMs with Split PROM option. this case, only single PROM needed. Click accept PROM Properties.
Select File Save save PROM file. Specify your working directory area where PROM Description File will saved. PROM File Formatter saves both PROM file (watch.mcs) PROM Description File (watch.pdr). file reopened changes required. Verify that files exist your directory.
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Implementation Tools Tutorial Select File Exit close PROM File Formatter. This completes tutorial. more information Alliance design flow implementation methodologies (especially some tools programs that were covered part this tutorial), please reference online version Software Manuals http://support.xilinx.com
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Xilinx Development System
Chapter
Using Software
This chapter provides overview Xilinx Development System. standard flow from netlist PROM file described, including information options, reports, simulation netlists, constraints, floorplanning, guided implementations. Advanced flows, such re-entrant routing multi-pass place route, also described. This chapter includes following sections. "Using Xilinx Tools" "Xilinx Design Flow" "Selecting Options" "Using Design Constraints" "Guiding Design with Floorplanner Files" "Static Timing Analysis" "Creating Simulation Files" "Downloading Design" "Multi-Pass Place Route" "Guiding Implementation"
Note: latest information regarding Design Manager tools functions, "Legacy Information" Appendix Design Manager/Flow Engine Guide.
Using Xilinx Tools
start Xilinx tools double click Design Manager icon, enter following command line start Design Manager. xilinx
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Alliance Series 2.1i Quick Start Guide also start Design Manager entering following command line. dsgnmgr
Xilinx Design Flow
"Xilinx Design Flow" figure shows processing steps flow files Design Manager. "Detailed Design Flow" figure more detailed look various programs invoked during design implementation process.
Constraints Netlists
SXNF
EDIF
Design Manager
Flow Engine Translate
Functional SImulation Data
Report Browser
Logic-Level Timing Report
Timing Analyzer
Place Route
Post-Layout Timing Report EPIC Design Editor Configure
Timing Simulation Data
Flow only supported command line.
PROM File Formatter
Hardware Debugger
X7923
Simulator
Figure Xilinx Design Flow
Xilinx Development System
Using Software
SXNF
EDIF
design.ucf
NGDBuild
design.ncf
design.ngd
Trce
design.ncd design.pcf
NGDAnno, NGD2EDIF, NGD2VER, NGD2VHDL
design.xnf
design.edn design.ncd design.vhd design.sdf
BitGen
design.twr
design.bit
design.v design.sdf
X8037
Figure Detailed Design Flow
Using Design Manager
following section provides basic information about using Design Manager tool. Note: Refer Design Manager/Flow Engine Guide detailed information using Design Manager.
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Alliance Series 2.1i Quick Start Guide
Figure Design Manager Menu
Creating Project
following steps create project Design Manager. Select File Project from Design Manager menu click Project toolbar button. Project dialog appears. Specify design file open with following methods. Input Design field, type name design file open. Click Input Design Browse button right Input Design select level input netlist. Click
Note: Design Manager automatically creates subdirectory named xproj under input design directory uses work directory. Design Manager uses xproj subdirectory store data files project. want change this default work directory, type path Work Directory field Browse select directory. Project dialog box, click After your design loaded, Design Manager window appears, configured loaded design. information using Xilinx-supplied interface tools Synopsys, Viewlogic, Mentor Graphics, Cadence designs, appropriate appendix this manual, refer Interface User Guide your respective tool.
Xilinx Development System
Using Software
Implementing Your Design
Select Design Implement from Design Manager menu click Implement toolbar button. Implement dialog appears. Select part click Run. Design Manager automatically creates version revision. Additional versions created when netlist modified re-implemented. Additional revisions created when same netlist re-implemented with options constraints. Design Manager invokes Flow Engine process your design.
Using Flow Engine
Flow Engine allows process control implementation your design, well guide your implementation revisions. following figure shows various steps followed Flow Engine process your designs.
Figure Flow Engine Design Steps
Translating Your Design
Flow Engine's first step, Translate, merges input netlists running NGDBuild program.
Mapping Your Design
Mapping your design next step design flow. optimizes gates trims unused logic merged netlist.
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Alliance Series 2.1i Quick Start Guide also maps your design's logic resources performs physical design rule check.
Placing Routing Your Design
After mapping, Flow Engine places routes your design. (Place Route) program invoked optimally place route mapped CLBs IOBs your design. there timing constraints logic components, attempts minimize those delays moving corresponding logic blocks closer together. route stage, logic blocks assigned specific interconnect elements die. attempts minimize delays selecting faster interconnect.
Configuring Your Design
After placing routing your design, Flow Engine translates physical implementation into binary stream that used program FPGA.This binary stream saved configuration file (.bit) using BitGen program.
Analyzing Reports with Design Manager
Design Manager reports provide information logic trimming, logic optimization, timing constraint performance, assignment. access reports, select following from Design Manager menu. Utilities Report Browser open specific report, double click icon, shown following figure.
Xilinx Development System
Using Software
Figure Report Browser
Translation Report
Translation Report contains warning error messages from three translation processes: conversion EDIF style netlist Xilinx netlist; timing specification checks; logical design rule checks. report lists following. Hierarchical blocks that missing cannot translated Invalid incomplete timing constraints Output contention, loadless outputs, sourceless inputs
Report
Report (.mrp file) contains warning error messages detailing logic optimization logic mapping physical resources. report lists following information. Removed Logic Sourceless loadless signals cause removal entire chain logic. Each deleted element listed with progressive indentation easily identify origins removed logic sections; deletion statements indented. Added expanded logic speed optimization. Design Summary lists number percentage used CLBs, IOBs, flip-flops, latches. also lists architec-
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide ture-specific resources such global buffers boundary scan logic.
Place Route Report
Place Route Report (.par file) contains following information. Design Score Design Score measures relative goodness your design; lower score better. Because this score strongly dependent nature your design targeted part, meaningful score comparisons only made between iterations same design targeted same part. Number Signals Completely Routed should zero completely implemented design. not, able improve results using re-entrant route flow multipass place route flow. "Advanced Implementation Flows" section this chapter. timing summary report contains timing performance your design. information timing constraint performance synchronous delays, refer "Static Timing Analysis" section later this chapter.
Report
Report lists your design's pinout sorted signal name, then number.
Selecting Options
Options specify your design optimized, mapped, placed, routed, configured. Options grouped implementation templates configuration templates. Each template defines implementation configuration style. example, implementation style Quick Evaluation, while another Timing Constraint Driven. have multiple templates project. templates select implementation configuration style. access options templates, follow these steps.
Xilinx Development System
Using Software Select Design Implement from Design Manager menu click Implement toolbar button. Implement dialog appears. Select Options button Implement dialog box. Options dialog appears shown following figure.
Figure Options Dialog Select Edit Template button Implementation Configuration access associated template. Implementation Template Configuration Template dialog appears. options this depend target device family. information template options, Design Manager/Flow Engine Guide.
Using Design Constraints
Xilinx tools allow control implementation your design entering constraints. enter constraints during
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Alliance Series 2.1i Quick Start Guide design implementation phases design flow. During design phase, enter constraints follows. constraints your schematic design constraints your design your synthesis tool Enter constraints Xilinx Constraints Editor
apply location timing constraints your design. location constraints control mapping positioning logic elements target device. most common location constraints constraints. constraints used lock pins your design specific locations that placement consistent from revision revision. timing constraints specify fast path must meet your speed requirements. timing constraints placement routing your design. Constraints entered directly your input design known design constraints, eventually placed your design netlist. want constraints separated from your input design files, want modify your constraints without re-synthesizing your design, create User Constraints File (UCF) Constraints Editor. This file read NGDBuild during translation your design, combined with EDIF netlist into file. file exists with same name top-level netlist, automatically read. Otherwise, must specify file name User Constraints Options dialog box.
Adding Constraints with Constraints Editor
Constraints Editor graphical tool Xilinx Development System that allows enter timing constraints location constraints. enter constraints graphical interface without understanding file syntax. Constraints Editor passes these constraints implementation tools through file. Constraints Editor accepts following input files. valid file, which Xilinx logical design database file. This file serves input program, which generates physical design database (NCD).
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Using Software corresponding (User Constraint File), which contains logical constraints.
default, when file opened, existing file with same base name file used. Alternatively, specify name file. Constraints Editor writes valid file valid file.These files processed program, which generates (Physical Constraints File). Note: more information, Constraints Editor User Guide.
Guiding Design with Floorplanner Files
Floorplanner tool generates file that contains mapping placement information. this file guide mapping implementation revision. Note: file guide file, cannot guide mapping using Guide File(s) command Custom option. Also, Floorplanner only available XC4000 Spartan devices. guide your design with floorplan files, follow these steps. Design Manager project view, select implementation revision that been mapped modified using Floorplanner. more information Floorplanner, refer Floorplanner Reference/User Guide. Select Design Floorplan File(s) from Design Manager. Floorplan File(s) dialog appears. Select floorplan guide design from Floorplan Design dropdown list. Select existing implementation revision. Select None want guide design. Select Project Clipboard guide from implementation revision copied your project clipboard. data exists clipboard want copy data clipboard, Copy Floorplan Data Project Clipboard option Implement dialog box.
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Alliance Series 2.1i Quick Start Guide Select Custom guide from mapped file your file system, including designs generated from within Design Manager. This option invokes Custom dialog which specify your floorplan guide files. Specify file Floorplanning File field file Floorplanned Guide File field.
Flow Engine uses selected file guide implementation.
Static Timing Analysis
Timing analysis performed several stages implementation flow gauge delays. post-map timing report generated evaluate effects logic delays timing constraints, clock frequencies, path delays. post-place-and-route timing report, that incorporates both logic routing delays, generated final evaluation design's timing constraints, clock frequencies, path delays. Detailed timing constraint, clock, path analysis post-map post-place-and-route implementations accomplished using interactive Timing Analyzer tool.
Static Timing Analysis After
Post-map timing reports very useful evaluating timing performance. report uses real block delays estimates route delays. Although delays estimates, they provide valuable information. logic delays account significant portion percent) total allowable delay path, path able meet your timing requirements once real routing delays added. fact, logic-only-delays exceed total allowable delay path constraint, then place route process need since routing delays will only cause path's timing degrade. Routing delays typically account percent percent total path delays. identifying problem paths, mitigate potential problems before investing time place route. redesign logic paths fewer levels logic, paths specialized routing resources, move faster device, insert flip flops path, allocate more time path.
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Using Software logic-only-delays account much less (<15 percent) than total allowable delay path timing constraint, then very effort levels used place route tool. these cases, reducing effort levels allow decrease times while still meeting performance requirements.
Static Timing Analysis After Place Route
Post-PAR timing reports incorporate real block real route delays provide comprehensive timing summary. placed routed design your timing constraints, then proceed creating configuration data downloading device. identify problems timing reports, fixing problems increasing effort level, using re-entrant routing, using multi-pass place route. also redesign logic paths less levels logic, paths specialized routing resources, move faster device, insert flip flops path, allocate more time paths. identify paths that ignored, identified slower exceptions. Edit implementation template modify placer effort level. information re-entrant routing multi-pass place route, "Advanced Implementation Flows" section this chapter.
Summary Timing Reports
Implementing design Flow Engine automatically generate summary timing reports. summary reports show timing constraint performance clock performance. create summary timing reports, following steps. Open Options dialog post-MAP report, select Produce Logic Level Timing Report button post-PAR report, select Produce Post Layout Timing Report button
modify reports detail path delays paths failing timing constraints, following. Edit Implementation template
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Alliance Series 2.1i Quick Start Guide Select Timing Reports Select report format
After timing analysis finished, Logic Level Timing Post Layout Timing report appears report browser.
Detailed Timing Analysis
perform detailed timing analysis, select following from Design Manager. Tools Timing Analyzer specify specific paths analysis, discover paths covered timing constraints, analyze timing performance implementation based another speed grade. path analysis, following steps. Choose sources; from Timing Analyzer menu, select following. Path Filters Path Analysis Filters Select Sources Choose destinations; from Timing Analyzer menu, select following. Path Filters Path Analysis Filters Select Destinations create report, select following. Analyze Paths switch speed grades, select following. Select Options Speed Grade After speed grade selected, Timing Analyzer reports will based design running with speed grade delays. design does have re-implemented, because delays read from data file.
Creating Simulation Files
Once design implemented, timing simulation performed test timing requirements functionality your
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Xilinx Development System
Using Software design. Timing simulation save considerable time reducing time spent debugging test boards lab. Functional simulation help further save time uncovering design bugs before running Place Route. Xilinx tools allow create simulation data after each major processing step. This means that create functional simulation netlists after design been merged together NGDBuild Translate process, timing simulation netlists after design been placed routed PAR. Additionally, create simulation data after design been mapped, after design been placed routed. Simulation data created after design only been mapped contains timing data based block delays, most delays zero. Post-MAP simulation allows ensure that design's current implementation will give place route software sufficient margin route design within your timing requirements. Simulation data created after design been placed routed, contains accurate block delays estimates delays. Post-place simulation used incremental simulation step between post-MAP simulation complete post-route timing simulation.
Creating Timing Simulation Data
Follow these steps create timing simulation data. Select Design Implement from Design Manager menu click Implement toolbar button. Implement dialog appears. Select Options button Implement dialog box. Options dialog appears. Select Produce Timing Simulation Data option. same dialog box, click Edit Template button simulation. Select interface Simulation Template dialog box. General tab, select simulation netlist formats (EDIF, VHDL, Verilog®). selected EDIF, EDIF
Alliance Series 2.1i Quick Start Guide
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Alliance Series 2.1i Quick Start Guide tab, select Vendor. select VHDL Verilog, VHDL/Verilog select options want simulation. General tab, select Correlate Simulation Data Input Design option using simulation stimulus file test fixture that used functional simulation, contains signal names that were optimized your design during implementation.
With these options selected, Flow Engine automatically creates post-route simulation netlist selected format during timing stage. access simulation netlist Design Manager, perform following steps. Select your project revision. Select Design Export. Export dialog box, select Timing Simulation Data enter export directory file. Select listed netlist copied selected directory. netlist input your simulator perform timing simulation.
Note: more information, Development System Reference Guide.
Creating Functional Simulation Data
Functional simulation netlists should created using tools from your simulation vendor interface Alliance software tools. implementation processes need invoked create functional simulation netlists. However, your design contains modules with varying netlist formats that Xilinx interface software unable process, NGDBuild design create single design_name.ngd then create simulation netlist using translation tool: NGD2VHDL, NGD2VER, NGD2EDIF. following commands create functional simulation netlist. ngdbuild design_name ngd2edif design_name
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Xilinx Development System
Using Software
Downloading Design
implemented design downloaded directly from your workstation, using Hardware Debugger program XChecker cable, Parallel Cable III, MultiLINX cable. Hardware Debugger download file PROM file. more information downloading, Hardware Debugger User Guide Hardware User Guide.
Creating PROM
FPGA daisy chain FPGAs configured from serial parallel PROMs. PROM File Formatter create MCS, EXO, style files. files read PROM programmer that turns image into PROM. file also used configure FPGA daisy chain FPGAs through microprocessor. file stored data structure microprocessor boot-up code.
In-Circuit Debugging
Once design been downloaded FPGA, snapshots internal signal states captured read using Hardware Debugger program XChecker cable. display signal states waveforms Hardware Debugger. This capability allows test debug your design real-time environment interfaces with components your board. also control states your state machines, controlling when clock edges sent your system clock input. more information in-circuit debugging, Hardware Debugger, XChecker cable, Hardware Debugger Guide.
Advanced Implementation Flows
place route software, PAR, features that allow process complex designs that have tight timing requirements and/or difficult route. options varied many different ways. This section shows most common strategies.
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Alliance Series 2.1i Quick Start Guide
Re-Entrant Route
take implemented design input, starting point routing. your design placed routed, will placement just spend time routing design. your design partially routed, will existing placement routing only spend time routing unrouted signals. your design completely placed routed meeting timing specifications, start from where left continue rerouting design come with implementation that meets your timing specifications. running, continually updates file with current placement routing information. placed file re-entrant routing. perform re-entrant routing, follow these steps. Design Manager, select implemented revision, select Flow Engine button toolbox. Flow Engine, select following. Setup FPGA Re-entrant Setup Re-entrant Route dialog box, select Allow ReEntrant Routing button, which enables re-entrant route options. meeting timing specifications critical goal route, select Timespecs button during re-entrant route. meeting timing specifications critical, deselect button because timing driven route takes longer than non-timing driven route. Select number re-entrant routing passes. Auto selected, performs routing iterations until stops making significant progress until your design constraints have been fully met. Select number type cleanup passes. Cleanup passes after initial routing passes complete. effectiveness type cleanup passes depends design, device, constraints implementation. best methodology select more than three passes each most cases, single pass each sufficient), report determine which most effective. Then using more cleanup passes that style.
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Xilinx Development System
Using Software After have selected your options, click Place Route icon Flow Engine displays loop back arrow Re-Entrant route label.
specifying timing location constraints, want relax them give more flexibility. modify file, must step Flow Engine back Translation order incorporate changes. Since your design already implemented, step back beginning Place Route using Step Backward button bottom Flow Engine, then click button start again.
Multi-Pass Place Route
design completed routing meeting timing constraints, then perform more extensive search solution. produce multiple placed routed revisions, each revision with varying implementations. scores each implementation, choosing best revisions based score. choosing best implementation from large population, more likely find solution that meets your requirements. using Xilinx software networked UNIX workstations, significantly reduce time running place route passes parallel separate machines. execute Multi-Pass Place Route, perform following steps. Design Manager, sure select version revision, then from menu select following. Design FPGA Multi-Pass Place Route FPGA Multi-Pass Place Route dialog, select value Initial Placement Seed (Cost Table). Initial Placement Seed value that initializes Place Route algorithms. Each iteration receives incremented value starting strategy. initial runs, Seed since used your previous single- pass run. Select Place Route passes execute. Select number iterations save. Based design score, only files from best runs saved. using UNIX workstation, want Turns Engine multiple UNIX workstations, select nodelist file. nodelist file
Alliance Series 2.1i Quick Start Guide
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Alliance Series 2.1i Quick Start Guide user-created ASCII file that lists names workstations which want run. Each name should separate line. There should tabs spaces. Click start Multi-Pass Place Route Process.
Guiding Implementation
During design process your design modified implemented many times. most cases, parts your design change from implementation next. Guiding your design accelerates iterative implementations reusing unchanged sections from previous implementation current implementations. This advantageous because software spends time generating implementations only sections your design that have changed. guide process used during map, place, route, significantly reduce design times. guide process more effective when names instance names your design remain constant between iterations, except those specific parts your design that modified source level. This generally true schematic-based designs, synthesis-based designs. this reason, Xilinx does recommend using guide most synthesis-based designs.
Specifying Guide Design
select previous implementation guide current implementation, select following Design Manager. Design Guide File(s) Guide File(s) dialog appears. Guide Design field, select previously implemented revisions, Project Clipboard, Custom, None. Project Clipboard project clipboard used save guide data revisions that overwritten. save guide data project clipboard selecting Copy Guide Data Project Clipboard option Implement dialog box. Custom
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Xilinx Development System
Using Software Custom option guide from mapped, routed, fitted file your file system, including designs generated from within Design Manager. Custom dialog box, enter mapped file Mapping Guide File field. Enter placed routed file Guide File field. None Select None option want guide your design.
Exact Guide Mode
When guiding exact mode, unchanged logic modified way. This mode fastest, least flexible. this mode design iteration requires only minor changes. Exact mode default value. selected having Match Guide Design Exactly button pressed Options dialog.
Leveraged Guide Mode
When guiding leveraged mode, mapping, place, route unchanged logic modified tools need make layout changes accommodate logic. this mode significant changes have occurred your design. Leveraged mode automatically selected when Match Guide Design Exactly button selected Options dialog.
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Using Software
Alliance Series 2.1i Quick Start Guide
3-22
Appendix
Alliance FPGA Express Interface Notes
This appendix provides information installing using Alliance FPGA Express Xilinx Alliance Series release. Synopsys Xilinx CD-ROM documentation referenced help find additional information. Alliance FPGA Express FPGA Express software purchased from Synopsys. Foundation Express FPGA Express software bundled with current release Foundation purchased from Xilinx. references FPGA Express this appendix refer Alliance FPGA Express. more information Foundation Express, refer Foundation Series 2.1i Quick Start Guide. FPGA Express Verilog/VHDL compiler designed work with Windows 95/98 Windows v4.0. FPGA Express process either Verilog VHDL files. This tool writes files (EDIF Virtex designs) which fully compatible with Alliance Series Design Implementation tools. Only Xilinx implementation tools third party simulation tool needed addition FPGA Express fully create simulate design. This appendix includes following sections. "Additional Documentation" "Alliance FPGA Express/Xilinx Design Flow" "Installing FPGA Express" "Entering Design" "Simulating Design" "Timing Constraints" "Porting Code from FPGA Compiler FPGA Express" "Using LogiBLOX with FPGA Express"
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide
Additional Documentation
following documentation available FPGA Express Alliance Series Design Implementation tools current release software. installation Alliance Series Design Implementation Tools, refer Alliance Series 2.1i Release Notes Installation Guide. installation FPGA Express, HDL-entry flow, mixed entry flows, refer FPGA Express User's Guide, hard copy document included with your FPGA Express software from Synopsys. additional information FPGA Express Xilinx flow, refer Synopsys FPGA Express Design Guide, available This file Word Windows (95) version file.
Alliance FPGA Express/Xilinx Design Flow
FPGA Express top-level design tool design flow. FPGA Express writes file (EDIF Virtex) which fully compatible with Alliance Series Design Implementation tools. file written FPGA Express accepted NGDBuild Design Manager creation PROM file. following types simulation possible with FPGA Express. Behavioral Post-NGDBuild Post-Map Post-synthesis post-route timing simulation (post-PAR)
more specific information simulation with FPGA Express, refer FPGA Express Design Guide. Refer following figure graphic representation design flow.
Xilinx Development System
Alliance FPGA Express Interface Notes
.vhd
Unisim Library
Party Simulator
NGDAnno .ucf FPGA Express .ngd Behavioral Simulation
.xnf
NGDBuild
.ngd Design Manager .ngo
.ncd
.ncd
Testbench NGDAnno
.nga
.ngm
NGD2VER NGD2VHDL
.sdf
structural structural .vhdl
VITAL/Verilog Simulation Libraries
.bit and/or prom file
Timing Simulation
Functional Simulation
Party Simulators
X7761
Figure
Alliance FPGA Express/Xilinx Design Flow
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
Installing FPGA Express
Insert FPGA Express into your CD-ROM drive. Start Explorer double-click CD-ROM icon. Double-click setup.exe start install process. additional instructions install FPGA Express Windows Windows refer FPGA Express User's Guide included with FPGA Express software from Synopsys.
Entering Design
enter design, following steps. Start FPGA Express selecting following. Program Synopsys FPGA Express text editor enter your design Verilog VHDL. Define your project FPGA Express selecting. File New. Identify files synthesis selecting following. Synthesis Identify Sources Specify top-level file your project selecting top-level file top-level design drop-down list middle FPGA Express toolbar. Create implementation selecting following. Synthesis Create Implementation Optimize your design selecting following. Synthesis Optimize Chip Write file selecting following. Synthesis Export Netlist Verilog VHDL designs input files FPGA Express design flow, output file (EDIF Virtex designs), which processed directly Xilinx implementation tools. details defining projects FPGA Express, entering code, defining constraints FPGA Express, supported devices, design
Xilinx Development System
Alliance FPGA Express Interface Notes issues, refer FPGA Express User's Guide included with your FPGA Express software from Synopsys.
Simulating Design
FPGA Express synthesis tool only. Simulation designs with FPGA Express must done with third party simulation tool. more information simulation with FPGA Express, refer documentation your third party simulation tool. VHDL simulation, Xilinx VITAL libraries required. Xilinx VITAL libraries located $XILINX/vhdl directory, ($XILINX where Xilinx software installed). Verilog simulation, Xilinx Verilog libraries required. Xilinx Verilog libraries located $XILINX/verilog directory. more information simulation flow with FPGA Express, refer Development System Reference Guide. information using Design Manager simulation, refer Design Manager/Flow Engine Guide. Note: There three types simulation possible behavioral, postNGDBuild, back-annotated timing simulation.
Timing Constraints
FPGA Express automatically inserts timespecs into file writes out. Virtex designs, separate .ncf file containing timing constraints created along with .edf file. Optionally, user choose write timespecs file from FPGA Express. Instead, write constraints .ucf file. timespecs created FPGA Express file have FROM: syntax. Note: more information constraints FPGA Express, refer FPGA Express Expert Journal http://www.xilinx.com.
Porting Code from FPGA Compiler FPGA Express
Read this section porting design from FPGA/Design Compiler FPGA Express. compiling design originally compiled with FPGA/Design Compiler code hundred percent behavioral, then modification code needed. But, have instantiated components from libraries, some these components exist FPGA Express libraries.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide Some components that instantiated Xilinx design flow cannot instantiated FPGA Express tool, since there slight differences names. example, BUFGP_F component library does exist FPGA Express component library. FPGA Express, equivalent name BUFGP_F BUFGP. complete listing library cells that instantiated FPGA Express, refer contents following.
fpgaexpress/lib/xc3000 fpgaexpress/lib/xc4000e fpgaexpress/libxc5200
fpgaexpress directory where FPGA Express installed your system. these directories, there files with .dsn extension. string front .dsn name CELL that instantiated FPGA Express. general, instantiation necessary. XC4000EX/XL/ XLA/XV FPGA Express flow, must instantiate following components. muxes Fast capture latches BSCAN LogiBLOX
examples instantiation muxes, fast capture latches, RAM, BSCAN, refer "Xilinx Synopsys Interface Notes" appendix.
Using LogiBLOX with FPGA Express
information using LogiBLOX FPGA Express, refer FPGA Express "Tech Tips" http://support.xilinx.com.
Xilinx Development System
Appendix
Mentor Graphics Interface Notes
This appendix describes Mentor Graphics interface associated libraries, includes examples locking timing constraints. This chapter includes following sections. "Additional Documentation" "Setting Xilinx/Mentor Interface" "Mentor/Xilinx Software Design Flow" "Translating Design Xilinx EDIF" "Timing Simulation" "Mentor Interface Environment Variables" "Library Locations Sample Location Map" "Pin Locking" "Timing Constraints"
Additional Documentation
following documentation available Mentor Graphics interface. Mentor Graphics Interface Guide available online. This manual describes installation setup details Mentor Graphics Interface Mentor Graphics software documentation (for applications such Design Architect, QuickSim, QuickHDL, DVE) available online viewable with Mentor-supplied BOLD Browser.
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide
Setting Xilinx/Mentor Interface
following environment variables must modified added Xilinx/Mentor interface tools. MGC_HOME (add) (add) SIMPRIMS (add) MGC_GENLIB (add) MGC_LOCATION_MAP (add) path (modify) LD_LIBRARY_PATH (modify Solaris) SHLIB_PATH (modify HP-UX)
these variables follows.
setenv MGC_HOME <installation_path_to_mentor> setenv $XILINX/mentor/data setenv MGC_GENLIB $MGC_HOME/gen_lib setenv MGC_LOCATION_MAP <location_of_actual_map_file> path $path)
Solaris only.
setenv LD_LIBRARY_PATH $MGC_HOME/shared/
HP-UX only.
setenv SHLIB_PATH $MGC_HOME/shared/lib:$MGC_HOME/ lib:$SHLIB_PATH
Following example your environment variables.
setenv MGC_HOME /usr/mentor setenv $XILINX/mentor/data setenv SIMPRIMS $LCA/simprims setenv MGC_GENLIB $MGC_HOME/gen_lib
Xilinx Development System
Mentor Graphics Interface Notes
setenv MGC_LOCATION_MAP /usr/data/mgc_location_map path ($XILINX/mentor/bin/sol $path) setenv LD_LIBRARY_PATH $MGC_HOME/shared/
Note: previous settings assume that Xilinx environment variables point appropriate area, described Software Variable setup section Alliance 2.1i Installation Guide Release Notes.
Mentor/Xilinx Software Design Flow
following figure illustrates Mentor Graphics Xilinx software design flow. Shown design entry, functional simulation, implementation, timing simulation.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
Design Architect
Editor
EDDM
PLD_DVE
QVHCOM/QVLCOM
Design Viewpoint
Compiled Object
QuickHDL EDDM QuickSim QuickHDL
PLD_EDIF2TIM
PLD_MEN2EDIF
Synthesis Tool
EDIF
EDIF/XNF
Implementation Tools
NGA/NGD
NGD2EDIF
NGD2VHDL/NGD2VER
EDIF X8094
Figure
Mentor/Xilinx Software Flow
design flow starts with design entry with PLD_DA (the Mentor schematic design tool). design processed PLD_DVE generate Xilinx-style design viewpoint.
Xilinx Development System
Mentor Graphics Interface Notes design then passed PLD_QuickSim functional simulation. Once design logic been verified, Mentor schematic processed PLD_MEN2EDIF create EDIF file. EDIF file passed Xilinx tools implementation. Xilinx tools create file that processed PLD_EDIF2TIM create timing-annotated EDDM netlist. This netlist processed PLD_DVE generate Xilinx style design viewpoint. design passed PLD_QuickSim cross-probing mode timing simulation.
functional simulation, first generate simulation viewpoint, with PLD_DVE. example, generate viewpoint XC4000EX component my_design, following command. pld_dve my_design xc4000ex specific viewpoint name optionally given after technology type. given, default viewpoint created with name default. simulate this design, following command. pld_quicksim my_design This runs QuickSim functional simulation without cross-probing. also PLD_DVE PLD_QuickSim icons PLD_DMGR. more information functional simulation, Mentor Graphics Interface Guide.
Translating Design Xilinx EDIF
translate design into EDIF file Xilinx implementation tools, PLD_MEN2EDIF command. example, target my_design XC4000EX. pld_men2edif my_design xc4000ex also specify viewpoint name after technology type. viewpoint name given, default viewpoint used with name default. This default viewpoint name same that used PLD_DVE.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide also pld_men2edif icon PLD_DMGR. more information PLD_MEN2EDIF, Mentor Graphics Interface Guide.
Timing Simulation
After implementing your design generating annotated netlist (with NGDANNO), must NGD2EDIF generate timing-annotated EDIF netlist that Mentor use.
Generating Timing-Annotated EDIF Netlist
NGD2EDIF generate timing-annotated EDIF netlist. case my_design, example, enter following. ngd2edif mentor my_design.nga my_design.edn This creates file compatible with Mentor interface.
Generating Timing Model
After creating file, PLD_EDIF2TIM generate timing model with following command. pld_edif2tim my_design.edn This creates EDDM-type component under my_design_lib/ my_design, well simulation viewpoint that component.
Running PLD_QuickSim
After generating simulation viewpoint, PLD_QuickSim with cross-probing this component. wish annotate simulation values onto your original schematic, remove option without cross-probing.) pld_quicksim my_design_lib/my design -tim type -consm messages QuickSim will start read timing-annotated EDDM netlist. will also start Open viewpoint schematic sheet your original schematic annotate simulation values (from QuickSim) onto that front-end schematic.
Xilinx Development System
Mentor Graphics Interface Notes also PLD_EDIF2TIM PLD_QuickSim icons PLD_DMGR. more information timing simulation, including more detailed explanation cross-probing, Mentor Graphics Interface Guide.
Mentor Interface Environment Variables
following environment variables.
setenv $XILINX/mentor/data setenv SIMPRIMS $LCA/simprims path ($XILINX/mentor/bin/sol $path)
(This example Solaris workstations. Replace "sol" with "hp" HP-UX workstations.) These variables addition XILINX environment variable settings required Alliance Series Design Implementation Tools. refer Mentor-specific variables such MGC_HOME MGC_LOCATION_MAP, Mentor Graphics Interface Guide more information.
Library Locations Sample Location
Xilinx libraries reside under $LCA directory with XACT 5.x. Also underneath this directory "simprims" (simulation primitives) library that QuickSim must simulate back-end timing simulation models. This requires your location have following lines addition other soft names (including MGC_GENLIB) have included.
MGC_LOCATION_MAP_1 $LCA (blank line) $SIMPRIMS (blank line)
always, your $MGC_LOCATION_MAP file points location this file. more information location maps, Mentor Graphics Interface Guide.
Locking
symbols (IPAD, OPAD, etc.) have generic pin-location ("LOC") properties already attached them. (They appear "PXX"
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide symbol.) place pads specific locations device modifying these properties required. example property value symbol "P24".) Note that "bused" symbols (for example, IPAD8) take comma-separated list order) locations (P24, P23, P22, more information location constraints, Libraries Guide.
Timing Constraints
Timing constraints placed properties TIMESPEC symbol design. Timespec label (the label that begins with "TS") entered property name, while timing specification (for example, "FROM:FFS:TO:FFS=30NS") entered property value. more information timing constraints, Development System Reference Guide.
Xilinx Development System
Appendix
Xilinx Synopsys Interface Notes
This appendix provides information setting Xilinx Synopsys Interface (XSI) associated libraries. Example files included help FPGA Compiler with Xilinx software. This chapter contains following sections. "Documentation" "Setting Synopsys Interface" "Examples Synopsys Setup Files" "Entity Coding Examples"
Documentation
following documentation available Synopsys interface. Xilinx Synopsys Interface Guide available Alliance 2.1i Documentation CD-ROM. Alliance 2.1i Release Documentation describes installation setup current issues regarding Synopsys interface. converting XACT 5.x.x Synopsys design refer Xilinx Software Conversion Guide from XACTstep v5.X.X XACTstep vM1.X.X.
Setting Synopsys Interface
following environment variables must modified added Synopsys interface tools. SYNOPSYS (add) PATH (modify)
Alliance Series 2.1i Quick Start Guide July 1999
Alliance Series 2.1i Quick Start Guide LD_LIBRARY_PATH (modify) SHLIB_PATH (modify)
these variables follows. setenv SYNOPSYS installation_path_to_synopsys path ($XILINX/bin/platform_name $SYNOPSYS/platform_name/syn/bin $SYNOPSYS/platform_name/sim/bin $path) Solaris only. setenv LD_LIBRARY_PATH $SYNOPSYS/platform_name/sim/ lib:$LD_LIBRARY_PATH HP/UX only. setenv SHLIB_PATH $SYNOPSYS/platform_name/sim/ lib:$SHLIB_PATH following example. setenv SYNOPSYS /usr/synopsys path ($XILINX/bin/sol $SYNOPSYS/sol/syn/bin $SYNOPSYS/sol/sim/bin $path) setenv LD_LIBRARY_PATH $SYNOPSYS/sol/sim/ lib:$LD_LIBRARY_PATH
Setting Simulation Libraries
Note: using FPGA CompilerII v3.2 later, must re-compile Xilinx DesignWare (XDW) libraries. (Xilinx Synopsys Interface) simulation (Xilinx DesignWare) libraries compiled Synopsys v1998.08. using latest version with version Synopsys newer than v1998.08, must re-compile libraries with version
Xilinx Development System
Xilinx Synopsys Interface Notes Synopsys using. going simulate with VSS, must re-compile simulation libraries. Compiling libraries $XILINX area requires write permissions this area. copy $XILINX/synopsys directory local area, need rewrite permissions $XILINX area re-compile libraries. However, verify that .synopsys_dc.setup .synopsys_vss.setup files local copy.
Compiling Libraries
Follow these steps compile libraries. your Xilinx Synopsys software environments. directory. this directory, there subdirectories that represent Xilinx device families that have libraries. going device families listed, must corresponding subdirectory compile script that directory. example, Spartan device, enter following commands. spartan install_dw.dc script entering following. dc_shell install_dw.dc When script finished, back $XILINX/synopsys/ libraries/dw/src. Repeat these steps each device plan using.
Compiling Simulation Libraries
Note: following procedure compiling simulation libraries with VSS. using different simulator, refer your simulator's documentation instructions compiling simulation libraries. Setup your Synopsys software environments. directory. this directory, there subdirectories that represent five simulation libraries, described follows.
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide LogiBLOX functional simulation VHDL designs with instantiated LogiBLOX components SimPrims timing simulation library UNISIMS functional simulation library XC9000 XC9500 functional simulation library Functional simulation library post-synthesis (FPGA compiler) pre-NGDBuild simulation
Some these libraries need re-compiled depending device type simulation plan using. Xilinx recommends compiling logiblox, simprims, unisims libraries. following steps compile these libraries. logiblox directory enter following command. ./analyze.csh back directory. simprims directory enter following command. ./analyze.csh back directory. unisims directory enter following command. ./analyze.csh unisims directory also contains analyze_52k.csh script. plan simulating XC5200 devices, must this script well. must also edit .synopsys_dc.setup file unisims directory point location compiled XC5200 libraries. back directory. directory enter following command. ./analyze.csh back directory. xc9000/ftgs directory enter following command. dc_shell install_xc9000.dc
Xilinx Development System
Xilinx Synopsys Interface Notes
Examples Synopsys Setup Files
This section includes examples Synopsys setup files needed FPGA Compiler with Xilinx tools. These examples XC4000XL Virtex devices. Other FPGA CPLD templates Xilinx installation path, $XILINX/synopsys/ examples.
XC4000 Devices
Although following .synopsys_dc.setup file example XC4000XL device, similar setup file required XC4000E/ EX/XLA/XV devices.
Example .synopsys_dc.setup File
Template .synopsys_dc.setup file Xilinx targeting XC4000XL XilinxInstall get_unix_variable(XILINX); SynopsysInstall get_unix_variable(SYNOPSYS); search_path XilinxInstall /synopsys/libraries/syn SynopsysInstall /libraries/syn Define work library.You must create `work' define_design_lib WORK -path ./WORK Declare Xilinx DesignWare library define_design_lib xdw_4000xl -path XilinxInstall General configuration settings. compile_fix_multiple_port_nets true xnfout_constraints_per_endpoint xnfout_library_version "2.0.0"
bus_naming_style "%s<%d>" bus_dimension_separator_style "><" bus_inference_style "%s<%d>" synlibs 4028ex-3 .synopsys_dc.setup
Example .synopsys_vss.setup File
simulation preferences. TIMEBASE TIME_RES_FACTOR Define work library current project
Alliance Series 2.1i Quick Start Guide
Alliance Series 2.1i Quick Start Guide
WORK DEFAULT DEFAULT ./WORK SIMPRIM Back-annotation libraries SIMPRIM LogiBLOX simulation libraries LOGIBLOX example pointers Xilinx Unisim functional simulation library UNISIM:
Example Script File XC4000E/EX/XL/XV Designs
This section describes typical sequence commands used process designs with Synopsys interface. should commands dc_shell command line, either individually batch mode. While every design require commands used this section, following example represents good starting point most designs. This script file includes information location constraints, timing constraints, setting part-type, controlling characteristics, controlling Synopsys mapping packing functions.
Sample Script Synopsys Xilinx Using FPGA Compiler targeting XC4000EX device*/ name design's top-level <design_name> designer "XSI Team" company "Xilinx, Inc" part "4028expg299-3" Analyze Elaborate design file. analyze -format vhdl ".vhd" elaborate current design level. current_design synthesis design constraints. remove_constraint -all Some example constraints create_clock <clock_port_name> -period set_input_delay -clock <clock_port_name> <a_list_of_input_ports> set_output_delay -clock <clock_port_name> <a_list_of_output_ports> set_max_delay -from <source> <destination>
Xilinx Development System
Xilinx Synopsys Interface Notes
set_false_path -fr
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