This document pertains following devices packages: 9536XL PLCC44, CSP4
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XC9500XL FAMILY
This document pertains following devices packages: 9536XL PLCC44, CSP48, VQFP64 9572XL PLCC44, CSP48, VQFP64, TQFP100 95144XL TQFP100, TQFP144, CSP144 95288XL TQFP144, PQFP208, BGA256 device programming verification procedures similar those used with standard FLASH memories. Initially, after each erasure, cells device logical (00H) state. Xilinx software generates device programming files JEDEC format. JEDEC file also contains information specific each device, which will compared device being programmed. Each product contains portion with manufacturer's code identify Xilinx manufacturer product code identify device. Please refer Add.dat file specific code information.
Addressing device addressed byte-wide memory with several significant exceptions. There several illegal addresses some bytes which bits programmed. legal device addresses contained included Add.dat floppy disk. Operating Modes device operating modes: Program Erase. Program used selectively changing FLASH cells within device. Erase procedure used erase device. other operations make programming mode. This includes Stand Alone Verify, Blank Check, Load, reading Signature String, Manufacturer's Product Codes. Signature String programmer host computer must support mode reading displaying four signature string bytes alphanumeric characters. Programming these bytes automatic because Xilinx software inserts this string into design file. Note: sample design files (jedec format) included with this document, have signature string `fast'. Unlike previous CPLD devices, don't need complement data before displaying Display data read Device Security device supports read security feature which protects design from being copied. secured device still erased reprogrammed.
Features
Erase device electrically erasable. algorithm perform blank check device ensure bits erased before allowing programming.
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Special Instructions
Device/ File Checksum Calculation Contained each JEDEC file fuse checksum (C-Field), which should used represent file checksum. This checksum 16-bit (i.e. modulo 65,535) 8-bit word containing fuse states entire device. Unused bits final 8-bit word must zero. same method must used calculate device checksum should match. Compatibility Checks 3.2.1 Adapter Type adapter should contain electronically readable code identification. programming algorithm must check adapter compatibility with target device. JEDEC design file also contains information specific device count fuse size, both which must compared adapter use. count, fuse size, packages each device listed Add.dat file, supplied floppy disk.
Read Manufacturer's Code Verify that manufacturer's code device matches value listed Add.dat file contained supplied disk. manufacturer's code does match, display message "Manufacturer's Code Error" terminate programming sequence. appropriate address found Add.dat file. Read Product Code Verify that product code device matches value listed Add.dat file contained supplied disk. product code does match, display message "Product Code Error" terminate programming sequence. appropriate address found Add.dat file. Note: Different product codes require different program erase voltages. Read Version Code Verify that version code device matches value listed Add.dat file contained supplied disk. Version code does match with associated product code, display message "Version Code Error" terminate programming sequence. product codes have valid version code. appropriate codes Add.dat file.
Programming Sequence
device programming sequence, illustrated Figure begins verifying that device design file programming algorithm match installed programmer adapter. This check accomplished comparing programmer adapter first acceptable adapter programmer algorithm next fuse count count contained JEDEC file. mismatch occurs, display message "Incompatible Adapter File" current algorithm terminate programming sequence.
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Device Blank Check Verify that FLASH cells unprogrammed state (`0'). Blank Check performed with Vppvfy3. FLASH cells programmed (`1'), display message "Device Blank" allow option erase device. device blank prior programming. device fails, display message "Device Failed Erase" terminate programming sequence. Device Programming Margin Verify this point actual programming cycle begins. minimize duration programming cycle, FLASH cells `Word Line' (WL) first loaded before short programming pulse applied device. amount address varies from device device. Specific address information address WL's found Add.dat file each device. (Please note setup hold time programming pulse, TENSV TENH.) After programming device, power down device perform margin verify, illustrated Figure Power down after margin verify cycle. programming/ margin verify cycle repeated until FLASH cells pass. cells fails margin testing, number retries permitted. Each time, full address array reprogrammed. number retries (NMAX) calculated using following equation:
attempts, cell still fails pass margin test, display message "Device Failed Program" terminate programming sequence. Post Program Verify Once programmed margin verified successfully, power device down then perform stand alone verify post program verify (See figure This operation performed with Vppvfy2. device fails, display message "Device Failed Verify" terminate programming sequence. programmer operator should able turn this operation. Secure Device Following programming stand alone verify sequence, algorithm should prompt operator secure device, illustrated Figure user elects secure device, display message "Device Secured" terminate programming sequence. user chooses secure device, program security bits following instructions specified address.dat file display message "Device Secured" (see Figure terminate programming sequence. device fails secure, number retries permitted. number retries (NMAX) calculated using following equation:
NMAX
TPWPGM
NMAX
TPWPGM
Where tPWPGM actual, measured value programming pulse width used. after NMAX
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Where TPWPGM actual, measured value programming pulse width used programming. after NMAX attempts,
XC9500XL FAMILY
security address still fails pass margin verify, display message Device Failed Secure" terminate programming sequence. device Read Secured, signature string, manufacturer's code product code still read. other data scrambled. Table shows which operations performed after device Read Secured.
Other Device Operations
Device Content Loading Confirm that device secured before attempting load content device. security been programmed (`1'), display message "Device Secured" terminate read sequence. loading operation performed with Vppvf2. Stand Alone Verify
Table Read Secure*
Operation Program Erase Verify Load Blank Check Signature String Mfg/Product Code Valid
Confirm that device secured before attempting this operation. security been programmed (`1'), display message "Device Secured" terminate stand alone verify operation. operation performed with Vppvf2. Stand Alone Erase erase device, follow flow Figure timing according Figure Add.dat file Function Block (FB) erase address. Erase device with Vppers then perform erase verify with Vppbnk. bits failed erase, number retries permitted. number retries (NMAX-ERASE) calculated using following equation:
NMAX-ERASE
TERASE
Add.dat file addresses data. After erasing secured device, program device again.
Where TERASE actual, measured value erase pulse width used erasing. after NMAX-ERASE attempts addresses still fails pass erase verify, display message "Device Failed Erase".
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Code
Start
Messages Incompatible Adapter File Current Algorithm Manufacturer's Code Error Product Code Error Produce Version Error Device Secured Device Blank Device Failed Erase Device Failed Program Device Secured Device Failed Verify Device Failed Secure
Compare Algorithm Adapter Fuse Count Count
Stop
Compare
Read Code
Compare Stop
Read Product Code
Blank Check
Compare Stop Pass
Read Version Code
Erase
Stop
Compare Stop
Program
Stop Erase
Check Security Addresses
Pass
Pass
Stop
Stop
Figure Overall Programming Sequence
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Program
N=N+1
Load addresses current Word Line
Program Word Line with
Last Word Line? Power Down, then Power Margin Verify Power Down Nmax Stop Pass Stop Secure Device
Margin Verify Pass Stand Alone Verify
Program Verify Security Bits
Stop Pass Stop
Stop
Figure Programming Flow
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Erase
N=N+1
Apply Erase Address
Erase Power down, then power
ERASE
Erase Verify Address
MAX-ERASE
Verify Pass
Stop Stop
Figure Erase Flow
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Secure
N=N+1
Program First Security Address with PWPGM
Program Next Security Address with PWPGM
Last Address Margin Verify Security Address
Pass
Stop
Stop
Figure Secure Flow
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Common Programming Erase Characteristics 25°C
Symbol Description VPPTST VCCBNK
VCCNOM
Limits
Units
Input Leakage Supply Current Supply Current Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage During Test Mode Entry During Blank Verify Nominal Nominal Margin Verify During Blank Verify Stand Alone Verify, Secure Verify, Load
VPPNOM VPPVF1 VPPBNK VPPVF2
Note: Although limits given, Xilinx recommends that mean used whenever possible.
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Specific Programming Erase Characteristics 25°C
Symbol
VPPERS
Description
Erase
Product
XC9536XL XC9536XL XC9572XL XC9572XL XC95144XL XC95144XL XC95288XL XC95288XL
Code
Version
Units
VPPPROG
Program
XC9536XL XC9536XL XC9572XL XC9572XL XC95144XL XC95144XL XC95288XL XC95288XL
Note: Version code available product revision.
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Programming Specifications
Symbol Description
TPWTST TPWSTB TPWPGM TVDV TERASE TVOFF1 TVOFF2 TENSU TENH Delay from VCCNOM VPPNOM Delay from VPPNOM TSTEN Test Mode Enable Pulse Width Setup Time VFYEN PGMEN Setup Time Test Setup Time AD_STB Setup Time PGMEN VFYEN Hold Time Test Hold Time AD_STB Hold Time AD_STB Pulse Width Address Setup Time Address Hold Time Program Pulse Width VFYEN Data Valid Erase Pulse Width Before Signals Signals Before Setup address data before PGM/ERS strobe Setup address data after PGM/ERS strobe
Limits
Units
Recommended TPWPGM Recommended TERASE
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CCNOM
TSTEN
ADDRESS
2ndW
2ndW
ata0
ata1
ata2
atan
ata0
ata1
DATA
PGMEN
VFYEN
AD_STB
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PPNOM
PPNOM
PPNOM
CCNOM
TSTEN
NEXT ADDRESS
rify rify rify, rify
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PPNOM
PPNOM
CCNOM
TSTEN
NEXT ADDRESS
trin
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PPNOM
PPNOM
PPBNK
CCNOM
NEXT ADDRESS
VFYEN
TS2-T
AD_STB
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ENTERING TEST MODE SELECT ERASE MODE ERASE DEVICE SELECT BLANK MODE BLANK CHECK DEVICE
PPTST
PWTST
PPNOM
PPERS
PPNOM
PPBNK
CCNOM
TSTEN
ERASE ADDRESS FIRST ADDRESS NEXT ADDRESS
ADDRESS
TERASE
OUTPUT OUTPUT
DATA
TENSU
TENH
PGMEN
VFYEN
TS2-TS3
AD_STB
PWSTB
Figure9. Erase
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XC9536XL Programming Signal Definitions Type PC44 VFYEN ADSTB TSTEN D3/TD1 VQ64 Type PGMEN A1/TDO PC44 VQ64
NOTE: Pins marked with must connected soft GND.
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XC9572XL Programming Signal Definitions Type PC44 TSTEN PGMEN VFYEN A5/TDI A6/TCK VQ64 Type A13/TDO ADSTB PC44 VQ64
NOTE: Pins marked with must connected soft GND.
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XC9572XL Programming Signal Definitions (Cont.) Type TSTEN PGMEN VFYEN TQ100 TYPE TQ100 TYPE ADSTB TQ100
NOTE: Pins marked with must connected soft GND.
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XC95144XL Programming Signal Definitions Type TQ100 CS144 TQ144 VFYEN ADSTB** ADSTB** PGMEN TSTEN Type TQ100 CS144 TQ144
Note: Pins marked with must connected soft GND. signal ADSTB should applied pins device simultaneously.
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XC95144XL Programming Signal Definitions (Cont.) Type TQ100 CS144 TQ144 Type TQ100 CS144 TQ144
Note: Pins marked with must connected soft GND.
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XC95288XL Programming Signal Definitions
Type
VFYEN ADSTB PGMEN TSTEN
TQ144 PQ208 BG256
Type TQ144 PQ208 BG256
Note: Pins marked with must connected soft GND.
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XC95288XL Programming Signal Definitions (Cont.)
Type
TQ144 PQ208 BG256
Type TQ144 PQ208 BG256
Note: Pins marked with must connected soft GND.
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XC95288XL Programming Signal Definitions (Cont.)
Type
TQ144 PQ208 BG256
Type TQ144 PQ208 BG256
Note: Pins marked with must connected soft GND.
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XC95288XL Programming Signal Definitions (Cont.)
Type
TQ144 PQ208 BG256
Type TQ144 PQ208 BG256
Note: Pins marked with must connected soft GND.
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