LogiCOREFacts Core Specifics Device Family CLBs Used IOBs Used5 S

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LogiCOREFacts Core Specifics Device Family CLBs Used IOBs Used5 S

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Master Slave Interfaces Version 1.2.0
LogiCOREFacts
Core Specifics Device Family CLBs Used IOBs Used5 System Clock fmax Device Features Used XC4000E 53/51 33MHz Bi-directional data buses SelectRAM(optional user FIFO) Boundary scan (optional) I/O5 -/76 107/109 141/143 107/109 141/143 Provided with Core CLB2
Xilinx Inc. 2100 Logic Drive Jose, 95124 Phone: 408-559-7778 Fax: 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com
Features
Fully compliant bit, 33MHz Interface Master (Initiator/Target) Slave (Target-only) Pre-defined implementation predictable timing Xilinx XC4000E FPGAs HardWire (see LogiCORE Facts listing supported devices) Fully verified design Simulated using VirtualChipsPCI testbench Tested hardware (silicon proven) Configurable on-chip FIFO added maximum burst speed (see Xilinx Documents section) Programmable single-chip solution with customizable back-end functionality Design Once- automatic conversion HardWire cost reduction Supported Initiator functions (PCI Master only) Initiate Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL) commands Initiate Read, Write commands Initiate Configuration Read, Configuration Write commands Parking Supported Target functions (PCI Master Slave) Type Configuration Space Header Base Address Registers (memory with adjustable block size from bytes Mbytes, slow decode speed) Parity Generation (PAR), Parity Error Detection (PERR# SERR#) Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Real Line (MRL), Memory Write, Invalidate (MWI) commands Read, Write commands Configuration Read, Configuration Write commands
Supported Devices1/Resources Remaining XC4013E PQ160 XC4013E PQ208 XC4013E HQ240 XC4020E HQ240 Documentation
XC4020E HQ208
User's Guide Interface Protocol Checklist V1.0 V1.1 Comparison Ping Ref. Design Users Guide Design File Formats VIEWlogic schematics Netlist3 Constraint Files TimeSpecs, RPMs, Guide files, sample synthesis script Verification Tool VIEWlogic command files VHDL Testbench Verilog Testbench Schematic Symbols VIEWlogic, VHDL, Verilog Evaluation Model VHDL, Verilog Simulation Model3 Reference designs Example design application notes Ping Reference Design4 Additional Items Reference book: System Architectures Design Tool Requirements Xilinx Core Tools XACTstep 5.2.1/6.0.1 Entry/Verification CORE generator: Tools VHDL, Verilog, Schematic changing source files: Workview Office V7.1.2 V7.2 Notes: next page.
Master Slave Interfaces Version 1.2.0
LogiCOREFacts (cont.)
Support Xilinx provides technical support this LogiCORE product when used described User's Guide supporting Application Notes. Xilinx cannot guarantee timing, functionality, support product implemented devices listed above, customized beyond that referenced product documentation, changes done sections design marked MODIFY".
Notes: Speed grade determined configuration user back-end, Figure exact number CLBs depends user configuration core level resource sharing with adjacent logic. Available Xilinx Home Page, LogiCORE Lounge: heading "Ping Reference Design" Master/Slave Slave only
adapters data acquisition boards. Embedded applications within telecommunication industrial systems. Other applications that need
General Description
LogiCOREMaster Slave Interfaces preimplemented fully tested modules Xilinx XC4000E FPGAs (see LogiCORE Facts listing supported devices). pin-out relative placement internal Configurable Logic Blocks (CLBs) pre-defined. Critical paths controlled TimeSpec's ensure that timing always met. This significantly reduces engineering time required implement portion your design. Resources instead focused unique back-end logic FPGA system level design. result, LogiCORE products your development time several months. Xilinx XC4000E Series FPGAs enables designs fully PCI-compliant systems. devices meet required electrical timing parameters including output drive characteristics, input capacitance specifications (10pF), setup hold system clock, system clock output. Compliance Checklist XC4000E additional details (see Xilinx Documents section). Other features that enable efficient implementation complete system XC4000E includes: Select-RAMmemory: on-chip ultra-fast with synchronous write option dual-port option. Used Interfaces implement FIFO. Individual output enable each
Features (cont.)
32-bit data transfers, burst transfers with linear address ordering Target Abort, Target Retry, Target Disconnect Full Command/Status Register Supported Xilinx CORE Generator Web-based configuration Generation proven design files
Applications
Add-in boards such graphic cards, video adapters,
PERRSERRParity Generator/ Checker
Base Address Register
Base Address Register
Command/ Status Register
AD[3
INTERFACE
FRAMEIRDYREQGNTInitiator State Machine Interrupt Line Register Latency Timer Register Vendor Other User Data
TRDYDEVSELSTOPTarget State Machine
X7954
USER APPLICATION
Internal 3-state capability global low-skew clock signal distribution networks IEEE 1149.1-compatible boundary scan logic support Xilinx 1996 Data Book more details. module carefully optimized best possible performance utilization XC4000E FPGA architecture. Implemented smallest supported FPGA, XC4013, more than FPGA's resources remain integrating unique back-end interface other system functions into fully programmable one-chip solution. Xilinx DesignOnceservice allows automatic conversion cost HardWiredevice high-volume production.
implement memory- I/O-mapped address spaces. Each sets base address interface allows system software determine addressable range required interface. Using combination Configurable Logic Block (CLB) flip-flops read/write registers look-up tables read-only registers results optimized packing density layout. Table Configuration Space Header Device Status Class Code Vendor Command Latency Timer
Functional Description
LogiCORE Master Interface partitioned into five major blocks, plus user application, shown Figure Each block described below.
BIST
Header Type
Cache Line Size
Interrupt Line
Base Address Register (BAR0) Base Address Register (BAR1)
Interface Block
interface block handles physical connection including signaling, input output synchronization, output three-state controls, requestgrant handshaking mastering.
Base Address Register (BAR2) Base Address Register (BAR3) Base Address Register (BAR5) Base Address Register (BAR5) Cardbus Pointer
Subsystem Subsystem Vendor
Parity Generator/Checker
Generates/checks even parity across bus, lines, signal. Reports data parity errors PERR- address parity errors SERR-.
Target State Machine
This block manages control over interface Target functions. states implemented subset equations defined "Appendix Local Specification. controller high-performance state machine using state-per-bit (one-hot) encoding maximum performance. State-per-bit encoding narrower shallower next-state logic functions that closely match Xilinx FPGA architecture.
Expansion Base Address
Reserved Reserved Max_Lat Min_Gnt Interrupt
Note: Italicized address areas implemented LogiCORE Interface default configuration. These locations return zero during configuration read accesses.
Initiator State Machine (PCI Master only)
This block manages control over interface Initiator functions. states implemented subset equations defined "Appendix Local Specification. Initiator Control Logic also uses stateper-bit encoding maximum performance.
User Application with Optional Burst FIFOs
LogiCORE Interface provides simple, generalpurpose interface with 32-bit data path latched address de-multiplexing address/data bus. general-purpose user interface allows rest device used wide range applications. Typically, user application contains burst FIFOs increase system performance Application Note available, please Xilinx Documents section). onchip read/write FIFO, built from on-chip synchronous
Configuration Space
This block provides first bytes Type version 2.1, Configuration Space Header (CSH) (see Table support software-driven "Plug-and Play" initialization configuration. This includes Command, Status, Base Address Registers (BARs). These BARs illustrate
Master Slave Interfaces Version 1.2.0 dual-port (SelectRAMTM) available XC4000E devices, supports data transfers excess MHz.
Supported Commands
Table illustrates commands supported LogiCORE Interface. LogiCOREPCI Interface Protocol Checklist (2.1) more details supported unsupported commands (see Xilinx Documents section)
Core Configuration
LogiCORE Interface easily configured unique system requirements using Xilinx web-based CORE Generator changing Viewlogic schematics. Following customization supported LogiCORE product described accompanying documentation. Initiator target functionality (PCI Master only) Base Address Register configuration Registers, size mode) Configuration Space Header Initiator target state machine (e.g., termination conditions, transaction types request/transaction arbitration) Burst functionality User Application including FIFO (back-end design)
Burst Transfer
derives performance from ability support burst transfers. performance application depends largely size burst transfer. FIFO support burst transfer efficiently implemented using XC4000E on-chip feature, SelectRAMTM. Each XC4000E supports 16x1 blocks. This corresponds bits single-ported bits dual-ported RAM, with simultaneous read/write capability. Table provides summary different FIFO sizes performance XC4000E-2. reliably perform burst transfer generic system LogiCORE Interface automatically inserts wait state when supplying data bus. Consequently, LogiCORE Interface accept data 100% burst transfer rate supply data 50%. Table transfer rates various operations. resulting bandwidth shown Figure
Table Commands [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Master Ignore Ignore Ignore Ignore Slave Ignore Ignore Ignore Ignore Ignore Ignore Ignore
Ideal Read
Transfer Rate (Mbytes/sec)
Ideal Write
Initiator Read Target Write Initiator Write
Target Read
Double-Word Burst Size
X8084
Figure Bandwidth
Note: Initiator present these commands, however, they either require additional user-application logic support them have been thoroughly tested.
Pinout
LogiCOREPCI Master Slave Interfaces support PCI-SIG recommended pin-out add-in cards. Tables describe signals pin-out LogiCORE Master Slave Interfaces. LogiCORE Master Slave Interface User's Guide detailed signal description. Table XC4000E-2 Synchronous FIFO Modules Depth Width 16x16 32x8 64x8 16x32 CLBs Single Port Performance Equivalent Dual-port Performance
Table Signal Description (internal signals) Signal Signal Description Target Name Address/Data AD[31:0] Address/Data CBE[3:0] Command/Byte Enable Parity Signal Interface FRAME Frame TRDY Target Ready IRDY Initiator Ready STOP Stop DEVSEL Device Select IDSEL Initialization Device SeIn lect LOCK Lock Interrupts INTD Interrupt INTC Interrupt INTB Interrupt INTA Interrupt Cache (not supported) SDONE SDONE Error Signals PERR Parity Error SERR System Error Arbitration Request Grant Boundary Scan Test Data Input Test Mode Select Test Clock Test Data Output Miscellaneous Global Reset Clock Note: Initiator
Table LogiCORE Transfer Rates Operation Initiator Write (PCI LogiCORE) Initiator Read (PCI LogiCORE) Target Write LogiCORE) Target Read (PCI LogiCORE) Transfer Rate 3-2-2-2 4-1-1-2 5-1-1-1 6-2-2-2
Note: Initiator Read Target Write operations have effectively same bandwidth burst transfer.
Signals marked applicable supported. Signals marked Open Drain output.
Master Slave Interfaces Version 1.2.0 Table Signal Description (internal signal) Signal Signal Description Name Cycle Control FRAMEFrame IRDYInitiator Ready TRDYTarget Ready STOPStop Transaction DEVSELDevice Selected Control BASE_HIT Base Address ADDR_VLD Address Valid DATA_VLD Data Valid CNFG_VLD Configuration Valid S_WRDN Slave Write/Read Dir. PCI_CMD[1 Command 5:0] S_CBE[3:0] Slave Comm/Byte Enable Address/Data ADDR[31:0] Latched Address ADIO[31:0] Address/Data PERRData Parity Error User Control READY Ready TERM Terminate Transaction T_ABORT Target Abort SRC_EN Source Data Enable INTRInterrupt KEEPOUT Keep Initiator Only Functions REQUEST Request Transaction M_CBE[3:0] Master Comm/Byte Enable M_WRDN Master Write/Read Dir. COMPLETE Complete Transaction TIME_OUT Latency Timer Timeout State Bits (Initiator) M_DATA Data Transfer State DR_BUS Parked M_ADDR- Addr. State/Bus Parking I_IDLE Initiator Idle State State Bits (Target) IDLE Target Idle State B_BUSY Busy S_DATA Data Transfer State BACKOFF TERM Asserted FREE Free State LOCKED Locked State Target Initiator Signal Signal Description Name Status Output CSR[39:0] Extended Comm/Status
Note: Signals marked using internal tri-state.
Target
Initiator
Table LogiCORE Pinout Signal AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 CBE3 CBE2 CBE1 CBE0 FRAMETRDYIRDYPQ160 PQ/HQ208 HQ240
Signal STOPDEVSELIDSEL LOCKINTA PERRSERRREQ RSTCLK
PQ160
PQ/HQ208
HQ240
Table Timing Parameters [ns] LogiCORE PCI, Spec. XC4000E-2/1 9.43 TPSU TPSU 9.43
Parameter Cycle Time High Time Time Signals Valid4 REQ# GNT# Valid4 Tri-state Active Tri-state Signal Setup (IOB) Signal Setup (CLB) GNT# Setup Input Hold Time After (IOB) Input Hold Time After (CLB) RST# Tri-state
Ref.
TICKOF
TICKOF
Timing Specification
XC4000E family, together with LogiCORE products enables design fully compliant systems. choice FPGA speed grade your application determined configuration your back-end design illustrated Figure Factors affecting your back-end designs include loading signals coming directly from bus, gate count floor planning. Table shows timing parameters LogiCORE Interfaces that must full compliance.
Notes: Controlled TimeSpecs, included product Verified analysis bench-testing Advanced speed grade data configured Fast slew rate
Figure Choice Speed Grade
Customer Back-End
Simple Slave Demanding
Verification Methods
LogiCORE Interfaces have been extensively simulated using VirtualChips VHDL test bench from Phoenix Technologies, Ltd. (not included with LogiCOREPCI products). Interface also been verified hardware XC4013E-2 PQ208C FPGA. Included with LogiCOREPCI Master Slave Interface example design VIEWlogic based protocol test bench that verifies interface functions according test scenarios specified Local Specification Figure This test bench consists test scenarios, each designed test compliance specific operation. Refer LogiCORE Interface Protocol Checklist complete list supported test scenarios (see Xilinx Documents section).
Master
X7952
Ping Reference Design
Xilinx LogiCORE "PING" Application Example, delivered VHDL Verilog, been developed provide easy-to-understand example which demonstrates many principles techniques required successfully LogiCOREPCI macro System Chip solution.
Master Slave Interfaces Version 1.2.0 Figure Protocol Testbench
faketarg Target Functional Mode lc_pci_i LogiCORE Interface testbnch Initiator Protocol Test User Application pci_test
HighGate Design 12380 Saratoga-Sunnyvale Road, Suite Saratoga, 95070-3090, Phone: 408-255-7160 Fax: 408-255-7162 E-mail: highgate@highgatedesign.com URL: www.highgatedesign.com Memec Design Services 1819 Dobson Rd., Ste. Mesa, Arizona 85202, Phone: 602-491-4311 Fax: 602-491-4907 E-mail: info@memecdesign.com URL: www.memecdesign.com Comit Systems 1250 Oakmead Pkwy, Suite Sunnyvale, 94088, Phone: 408-988-2988 Fax: 408-988-2133 E-mail: preeth@comit.com URL: www.comit.com
Simple Arbiter fakearb X7951
Recommended Design Experience
LogiCORE interface pre-implemented allowing engineering focus unique back-end functions design. Regardless, high-performance system that challenging implement technology, ASIC FPGA. Therefore, recommend previous experience with building high-performance, pipelined FPGA designs using Xilinx implementation software, Floorplanner, TIMESPECs, guide files. challenge implement complete design including back-end functions varies depending configuration functionality your application. Contact your local Xilinx representative closer review estimation your specific requirements. Table Part Numbers Product Part Number LC-DI-PCIM-C LogiCOREPCI Master (Intiator/Target) LC-DI-PCIS-C LogiCOREPCI Slave (Target Only) Supplier Xilinx, Inc.
Special Interest Group (PCI-SIG) Publications
PCI-SIG publishes various specifications related documents such Local Specification, Compliance Checklist System Design Guide. Special Interest Group 2575 Kathryn Hillsboro, 97124 Phone: 800-433-5177 (inside 503-693-6232 (outside Fax: 503-693-8344 Office hours: 8:30am 4:00pm E-mail: info@pcisig.com URL: www.pcisig.com
Xilinx, Inc.
Ordering Information
Table shows part numbers LogiCOREproducts. Before placing order, please read sign attached LogiCORElicense agreement Xilinx 408-879-4780. pricing availability please contact your local Xilinx sales office.
Xilinx Documents
More related information available Xilinx Web:
Related Information
Recommended Design Centers
Listed below design centers design consultants that have experience with LogiCORE products.
XILINX LOGICORE"PCI MASTER INTERFACE" "PCI SLAVE INTERFACE" LICENSE XILINX LOGICORE"PCI MASTER INTERFACE" "PCI SLAVE INTERFACE" LICENSE AGREEMENT AGREEMENT
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LogiCOREFacts Core Specifics Device Family CLBs Used IOBs Used5 S

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