| |
Datasheet Home \ Datasheet Details
Download
PDF Abstract Text:
DB-25 Connector and Cable
JTAG D2 D1
DB-25 Connector and Cable
JTAG D2 D1
Header
J3 15 D ERROR (WHITE)
VCC SENSE
R1 100
1N5817
1N5817 FPGA J1 Header
R14 100 J3 13 SELECT (BROWN) 74HC125 U2 74HC125 3 100 1 2
R13 R8 5.1K 1K C5 0.01UF
R2 J2 2 GND GND J1 2 R9 2 U1 GND C1 100PF 1 3 100 J1 4
(2) D6, BUSY, and PE connected at the DB25 end of data cable.
D / P (3) U1 and U2 power:
J3 6 D4 (BLUE)
R3 300 GND
VDD - pin 14 GND - pin 7
R10 J2 5 100 J1
U1 74HC125 J3 2 D0 (RED) J3 5 D3 (GREEN) J3 3 B D1 (ORANGE) R6 9 300 10 C3 100PF 8 100 J1 3 U1 74HC125
R4 5 300 4 C2 100PF 6
U2 74HC125 5 4 6
R5 300
GND U2 74HC125
U2 74HC125 12 11 13
GND U1 74HC125 J3 4 D2 (YELLOW) J3 20 GND (BLACK) J3 A 25 J3 11 SHIELD J3 PC Chassis Ground CGND 4 3 2 12 Comments: GND
R7 12 300 13 C4 100PF 11
R12 100 J1 6
See note (2)
BUSY PE
Title: JTAG / Parallel
Download
Cable
Date:July Sheet
Ver:02 Rev: 1
Size:
This information is being furnished as a service Xilinx customers. Xilinx Inc. and its employees shall not be held financially or legally responsible for any usage or application of this information.
|