Series Software Synopsys FPGA Compiler Implementation Flow M
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Synopsys FPGA Compiler Implementation Flow
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0010418
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Synopsys FPGA Compiler Information
Guide Overview
Device Architecture Support
FPGA Product Family Spartan Virtex XC4000X CPLD Product Family XC9500
Create project
menu File define project. files processed FPGA Compiler must done through project.
files project analyze files
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
After creating project, design files added project. After adding design files, FPGA Compiler will automatically analyze files.
Implement design
Select top-level module/entity Design Sources window implement button will highlighted. Click implement button specify target die, speed grade package. Strategies synthesis specified during implementation.
Enter constraints
Chips window, select implementation. Right-click selected implementation select Edit Constraints. window will appear where various constraints edited. After entering constraints, save constraints closing constraints window.
Synopsys Contacts Technical Support
World Wide Web: http://www.synopsys.com United States 1-800-245-8005 support_center@synopsys.com
Optimize design
Click optimize button located next implement button synthesize design select menu Synthesis Optimize Chip
Place Route EDIF file with A2.1i
0010418
After optimization, write EDIF file clicking Export Netlist button next implement button. Place Route EDIF file using A2.1i implementation tools with Design Manager shell based commands.
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