Series Software Synopsys Design Compiler Implementation Flow
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Synopsys Design Compiler Implementation Flow
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Synopsys Design Compiler Information
Guide Overview
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FPGA Product Family Spartan Virtex XC4000X CPLD Product Family XC9500
Setup Design Compiler .synopsys_dc.setup file
template .synopsys_dc.setup examples $XILINX/synopsys/examples. correct information your target speed grade. Modify paths your setup.
Recommended Settings
Please refer your A2.1i software installation example: .synopsys_dc.setup .synopsys_vss.setup runscript files $XILINX/synopsys/examples
Create compile script read your input files
example compile scripts $XILINX/synopsys/examples guide. Create compile script read files design.
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
Synthesize design running compile script with dc_shell design_analyzer
Compile design running: dc_shell runscript run.log design analyzer Either step will produce .sedif file
Synopsys Contacts Technical Support
World Wide Web: http://www.synopsys.com United States 1-800-245-8005 support_center@synopsys.com
Place Route .sedif file using A2.1i software
Place route synthesized design UNIX A2.1i commands Design Manager GUI.
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