Series Software Exemplar Implementation Flow Module Generato

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Series Software Exemplar Implementation Flow Module Generato

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ALLIANCE
Series Software
Exemplar Implementation Flow
Module Generators
LogiBLOX
.VHD .NGC= Xilinx Binary Netlist
CORE Generator
.NGC
.VEI .VHI
.VEO .VHO
Verilog VHDL Instantiation
Renoir Renoir
VHDL Verilog VHDL Verilog
Schematic Design Schematic Design Editor Editor
Editor Editor
VHDL Verilog
EDIF
VHDL Verilog
Requirements
Timing
.EDN
Functional Simulation Flow CORE Generator VHDL Verilog Timing Simulation Flow EDIF
LogiBLOX
Party
Xilinx
Tools
Design Constraints EDIF
UNIFIED Gates UniSim VITAL Verilog
VHDL Verilog
JEDEC
SimPrim VITAL, Verilog, Gates Test Bench
EDIF Netlist
STAMP Model
Reports
User Constraints File
.VHD
Command File Test Vectors
0010420
Functional Simulation Flow Note: primitives only. Timing information passed from schematic.
ALLIANCE
Series Software
Exemplar Information
Guide Overview
Device Architecture Support
FPGA Product Family Spartan Virtex XC4000X CPLD Product Family XC9500
Invoke Leonardo Spectrum
Invoke Leonardo Spectrum synthesis tool When dialog appears, select Leonardo Spectrum Level appropriate.
Recommended Settings
recommended settings, http://www.xilinx.com "Product" "Software Solutions"
Synthesis Wizard Users
When tool first invokes, synthesis wizard will appear. wizard provides step-by-step guide through synthesis process users.
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
Tab-based Advanced Users
advanced users, cancel wizard. full featured tab-based Leonardo Spectrum Level window will appear. There ways using tab-based GUI: Quick Setup individual tabs until output which provide more control options.
Specify Input Files
instantiate Xilinx component, Click right mouse button Technology input file.
Exemplar Contacts Technical Support
World Wide Web: http://www.exemplar.com Hill, Xilinx Relationship Manager 1-503-685-7750 Dina, Technical Support Manager 1-510-337-3700
Select Target Architecture
Select Target device speed grade.
Synthesis Commands
individual tabs options constraints with more control. Please refer online documentation information specify options constraints.
Library Language Support
Libraries meet Standards IEEE 1076, -87, -93, IEEE 1164 VHDL Verilog-XL Libraries include: std_logic_1164 std_logic_arith std_logic_signed std_logic_unsigned attributes
Synthesize
Push Flow button synthesize.
0010420

Series Software Exemplar Implementation Flow Module Generato

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