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Xilinx CORE Generator System Compatibility Guide September 1999
XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Archindry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, Timing Wizard, TRACE registered trademarks Xilinx, Inc. XC-prefix product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACTPerformance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation Series, AllianceCORE, BITA, Configurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardWire, LCA, Logic Cell, LogiCore, LogiBLOX, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, Select-RAM, SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, ZERO+ trademarks Xilinx, Inc. Programmable Logic Company Programmable Gate Array Company service marks Xilinx, Inc. other trademarks property their respective owners. Xilinx does assume liability arising application product described shown herein; does convey license under patents, copyrights, maskwork rights rights others. Xilinx reserves right make changes, time, order improve reliability, function design supply best product possible. Xilinx will assume responsibility circuitry described herein other than circuitry entirely embodied products. Xilinx devices products protected under more following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; 34,363, 34,444, 34,808. Other U.S. foreign patents pending. Xilinx, Inc. does represent that devices shown products described herein free from patent infringement from other third party right. Xilinx assumes obligation correct errors contained herein advise user this text correction such made. Xilinx will assume liability accuracy correctness engineering software support assistance provided user. Xilinx products intended life support appliances, devices, systems. Xilinx product such applications without written consent appropriate Xilinx officer prohibited. Copyright 1997 Xilinx, Inc. Rights Reserved.
Overview Latch Based Register Register. Single Output Gate Gate Gated with Control Multiplexer Multiplexer Dynamic Constant Coefficient Multiplier Variable Parallel Multiplier
Overview
This manual collection compatibility guides various Xilinx cores. Each compatibility guide shows some detail core changes stays same when supported various Xillinx core generation tools, namely, LogiBlox CORE Generator System V1.5 CORE Generator System V2.1 purpose this guide help customers quickly identify features when switching different version core generation tool. easy navigation, have presented information tables.
Manual Contents
compatibility guides this manual describe following features specific core: Name Functionality Port name Parameters
CORE Generator 2.1i User Guide
Preface
-viii
Xilinx Inc.
Xilinx LogiCORE
Compatibility Guide: Data Register
Latch Based Register
Table Functionality Comparison CORE Generator System V2.1 LogiBlox CORE Generator System V2.1 CORE Generator System V1.5
CORE Generator System V2.1 Latch Based Register Core functionally similar LogiBlox Latch core.
Table Core Name Cross Reference Tool LogiBlox CORE Generator System V1.5 CORE Generator System V2.1 Core Name Data Register Style Latches Location Tree Data Registers
LD-based Register
Basic Elements Registers, Shifters Pipelining
Table Port Name Cross Reference LogiBlox D_IN[N:0] Q_OUT[N:0] GATE GATE_EN ASYNC_CTRL SYNC_CTRL Notes:
LogiBlox, ASYNC_CTRL loads value assigned ASYNC_VAL attribute CORE Generator System V2.1, AINIT loads value assigned AINIT_VAL attribute. LogiBlox, SYNC_CTRL loads value assigned SYNC_VAL attribute CORE Generator System V2.1, SINIT loads value assigned SINIT_VAL attribute.
CORE Generator System V1.5
CORE Generator System V2.1 later D[N:0] Q[N:0] ASET ACLR AINIT SSET SCLR SINIT
Direction Input Output Input Input Input Input Input Input Input Input
Description Data Input Data Output Gate Gate Enable Asynchronous Asynchronous Clear Asynchronous Initialize Synchronous toAll Synchronous Clear Synchronous Initialize
Page
September 1999
Table Parameter Names Cross Reference LogiBlox (.mod) module DATA_REG STYLE CLB_LD Symbol BUS_WIDTH COREGenerator V1.5 (.log) COREGenerator V2.1 later (.xco) SELECT LD_Latch Type COREGenerator V2.1 Default setting
component_name data_width gate_enable ge_overrides
String Integer Keyword Keyword
blank false sync_controls_overrid e_ge none none clear_overrides_set true
ASYNC_VAL SYNC_VAL USE_RPM Notes:
asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority create_rpm
Keyword Keyword Keyword Keyword
Check respective datasheet syntax, definition, default value each keyword.
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Data Register
Register
Table Functionality Comparison CORE Generator System V2.1 LogiBlox Similar functionality CORE Generator System V2.1 CORE Generator System V1.5 CORE Generator System V2.1 supports data width opposed CORE Generator System V1.5 CORE Generator System V2.1 supports optional Clock Enable input opposed providing default CORE Generator System V2.1 supports optional Asynchronous Set, Clear Init opposed supporting only Asynchronous Reset V1.5 CORE Generator System V2.1 supports Synchronous Set, Clear Init which available CORE Generator System V1.5
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Core Name Data Register Style D-Type Register Location Tree Data Registers
LogiCORE-> Basic Elements
Register
Basic Elements Registers, Shifters Pipelining
Table Port Name Cross Reference LogiBlox D_IN[N:0] Q_OUT[N:0] CLOCK CLK_EN ASYNC_CTRL SYNC_CTRL Notes:
LogiBlox, ASYNC_CTRL loads value assigned ASYNC_VAL attribute CORE Generator System V2.1, AINIT loads value assigned AINIT_VAL attribute. LogiBlox, SYNC_CTRL loads value assigned SYNC_VAL attribute CORE Generator System V2.1, SINIT loads value assigned SINIT_VAL attribute.
COREGenerator System V1.5 D[N:0] Q[N:0]
COREGenerator System V2.1 later D[N:0] Q[N:0] ASET ACLR AINIT SSET SCLR SINIT
Direction Input Output Input Input Input Input Input Input Input Input
Description Data Input Data Output Clock Clock Enable Asynchronous toAll Asynchronous Clear Asynchronous Initialize Synchronous Synchronous Clear Synchronous Initialize
Page
September 1999
Table Parameter Names Cross Reference LogiBlox (.mod) Symbol BUS_WIDTH COREGenerator V1.5 (.log) component_Name port_width COREGenerator V2.1 later (.xco) component_name data_width clock_enable ce_overrides Type String Integer Keyword Keyword COREGenerator V2.1 Default setting blank false sync_controls_overrid e_ce none none clear_overrides_set true
ASYNC_VAL SYNC_VAL USE_RPM Notes:
asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority create_rpm
Keyword Keyword Keyword Keyword
Check respective datasheet syntax, definition, default value each keyword. generate module which equivalent functionality CORE Generator System V1.5, clock_enable should true asynchronous_settings should clear. other parameters labeled "N/A" should their respective default values.
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Gate
Single Output Gate
Table Functionality Comparison CORE Generator V2.1 LogiBlox CORE Generator System V2.1 supports type implementation, Normal Gates, whereas LogiBlox supports five styles: Edge Decode, Maximum Speed, Minimum Area, Normal Gates, Wired AND. CORE Generator System V2.1 selectable registered non-registered output opposed combinatorial only LogiBlox. CORE Generator System V2.1 CORE Generator System V1.5
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Core Name Simple Gates Location Tree Simple Gates
Gate
Basic Elements Logic Gates Buffers
Table Port Name Cross Reference LogiBlox A[N:0] COREGenerator V1.5 COREGenerator V2.1 later I[N:0] Q[0:0] ASET ACLR SSET SCLR Direction Description Gate Input non-registered output registered output Clock Clock Enable Asynchronous Asynchronous Clear Synchronous Synchronous Clear
Page
September 1999
Table Parameter Names Cross Reference CORE Generator System V1.5 (.log) CORE Generator System V2.1 later (.xco) SELECT Bit_Gate CORE Generator System V2.1 Default Setting
LogiBlox (.mod)
Type
OPTYPE=TYPE_1 STYLE NORMAL_GATES symbol BUS_WIDTH module(3) INVMASK DECODEMASK Notes:
component_name number_of_inputs gate_type(4) input_inversion_mask output_options clock_enable ce_overrides asynchronous_settings power_on_reset_value synchronous_settings set_clear_priority create_rpm
String Integer Keyword Keyword Keyword Keyword Keyword Keyword Keyword Keyword
blank registered false sync_controls_override_ce none none clear_overrides_set false
Check respective datasheet syntax, definition, default value each keyword. INVMASK DECODEMASK attributes opposite polarities achieve same effect. different modules supported are: AND, NAND, NOR, XOR, XNOR, INVERT. different gate_type supported are: and, nand, nor, xor, xnor. INVERTER BUFFER supported under Gate Core.
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Gate
Gate
Table Functionality Comparison CORE Generator V2.1 LogiBlox CORE Generator System V2.1 supports type implementation, Normal Gates, whereas LogiBlox supports three styles: Maximum Speed, Minimum Area Normal Gates. CORE Generator System V2.1 selectable registered non-registered output opposed combinatorial only LogiBlox. CORE Generator System V2.1 supports maximum input buses opposed input buses LogiBlox. CORE Generator V2.1 CORE Generator V1.5
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Table Port Name Cross Reference LogiBlox A[N:0]. B[N:0] O[N:0] COREGenerator V1.5 COREGenerator V2.1 later IA[N:0]. ID[N:0] O[N:0] Q[N:0] ASET ACLR AINIT SSET SCLR SINIT Direction Input Output Output Input Input Input Input Input Input Input Input Description Input Buses Output non-registered gate Output registered gate Clock Clock Enable Asynchronous Asynchronous Clear Asynchronous Initialize Synchronous Synchronous Clear Synchronous Initialize Core Name Simple Gates Location Tree Simple Gates
Gate
Basic Elements Logic Gates Buffers
Page
September 1999
Table Parameter Names Cross Reference CORE Generator System V1.5 (.log) CORE Generator System V2.1 later (.xco) SELECT Bus_Gate CORE Generator System V2.1 Default setting
LogiBlox (.mod)
Type
OPTYPE=TYPE_3 STYLE NORMAL_GATES symbol INPUT_BUSSES BUS_WIDTH module(3) Notes:
component_name number_of_input_buses input_bus_width gate_type(4) input_a_inversion_mask input_b_inversion_mask input_c_inversion_mask input_d_inversion_mask output_options clock_enable ce_overrides asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority create_rpm
String Integer Keyword Keyword Keyword Keyword Keyword Keyword Keyword Keyword
blank registered false sync_controls_override_ce none none clear_overrides_set true
Check respective datasheet syntax, definition, default values each keyword. different modules supported are: AND, NAND, NOR, XOR, XNOR, INVERT. different gate_type supported are: and, nand, nor, xor, xnor, inverter buffer. number input busses supported Inverter Buffer
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Gate
Gated with Control
Table Functionality Comparison CORE Generator System V2.1 LogiBlox CORE Generator System V2.1 supports type implementation, Normal Gates, whereas LogiBlox supports three types implementation: Maximum Speed, Minimum Area, Normal Gates. CORE Generator System V2.1 selectable registered nonregistered output opposed combinatorial only LogiBlox. CORE Generator System V2.1 CORE Generator System V1.5
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Core Name Simple Gates Location Tree Simple Gates
Gate
Basic Elements Logic Gates Buffers
Table Port Name Cross Reference LogiBlox B[N:0] O[N:0] COREGenerator V1.5 COREGenerator V2.1 later I[N:0] CTRL O[N:0] Q[N:0] ASET ACLR SSET SCLR Direction Input Input Output Output Input Input Input Input Input Input Description Input Control Output non-registered gate Output registered gate Clock Clock Enable Asynchronous Asynchronous Clear Synchronous Synchronous Clear
Page
September 1999
Table Parameter Names Cross Reference CORE Generator System V1.5 (.log)
LogiBlox (.mod)
CORE Generator System V2.1 later (.xco)
Type
CORE Generator System V2.1 Default Setting
OPTYPE TYPE_2 SYTLE NORMAL_GATES symbol BUS_WIDTH module INVMASK DECODEMASK Notes:
SELECT Bit_Bus_Gate
component_name input_bus_width gate_type input_inversion_mask output_options clock_enable ce_overrides asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority create_rpm
String Integer Keyword Keyword Keyword Keyword Keyword Keyword Keyword Keyword
blank registered false sync_controls_override_ce none none clear_overrides_set true
Check respective datasheet syntax, definition, default value each keyword. INVMASK DECODEMASK attributes opposite polarities achieve same effect. different modules supported are: AND, NAND, NOR, XOR, XNOR, INVERT. different gate_type supported are: and, nand, nor, xor, xnor. INVERTER BUFFER supported under Gate Core.
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Multiplexers
Multiplexer
Table Functionality Difference CORE Generator V2.1 LogiBlox CORE Generator System V2.1 supports type implementation, Normal Gates, whereas LogiBlox supports four types implementation: Maximum Speed, Minimum Area, Normal Gates, Wired AND. CORE Generator System V2.1 Multiplexer Select input always Binary encoded opposed Encoding styles supported LogiBlox (One Hot, Binary). CORE Generator System V2.1 selectable registered non-registered output opposed combinatorial output only LogiBlox Multiplexer. CORE Generator V2.1 CORE Generator V1.5
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Core Name Multiplexers Location Tree Multiplexers
Multiplexer
Basic Elements Multiplexer
Table Port Name Cross Reference LogiBlox M[N:0] S[M:0] COREGenerator V1.5 COREGenerator V2.1 later Mn-1 Q[0:0] S[M:0] ASET ACLR SSET SCLR Direction Input Output Output Input Input Input Input Input Input Input Description Multiplexer Inputs Output non-registered Output registered Binary encoded select inputs Clock Clock Enable Asynchronous Asynchronous Clear Synchronous Synchronous Clear
Page
September 1999
Table Parameter Names Cross Reference LogiBlox (.mod) module OPTYPE=TYPE_1 STYLE=NORMAL_GATES symbol BUS_WIDTH CORE Generator V1.5 (.log) CORE Generator V2.1 later (.xco) SELECT Bit_Multiplexer Type CORE Generator V2.1 Default setting
component_name number_of_inputs output_options clock_enable ce_overrides
String Integer Keyword Keyword Keyword
blank registered false sync_controls_overrid e_ce none none clear_overrides_set false
Notes:
asynchronous_settings power_on_reset_value synchronous_settings set_clear_priority create_rpm
Keyword Keyword Keyword Keyword
Check respective datasheet syntax, definition, default value ofeach keyword.
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Multiplexer
Multiplexer
Table Functionality Comparison CORE Generator V2.1 LogiBlox CORE Generator System V2.1 supports types implementation, BUFT-based LUT- based, whereas LogiBlox supports Maximum Speed, Minimum Area, Normal Gates Wired AND. LUT-based equivalent Normal Gates BUFT-based equivalent Wired AND. CORE Generator System V2.1 Multiplexer Select input always Binary encoded opposed Encoding styles supported LogiBlox (One Hot, Binary). CORE Generator System V2.1 selectable registered non-registered output opposed combinatorial only LogiBlox Multiplexer output. CORE Generator V2.1 CORE Generator V1.5 CORE Generator System V2.1 supports types implementation, BUFT-based LUT-based, whereas CORE Generator System V1.5 supports only Normal Gates (Equivalent LUT). CORE Generator System V2.1 selectable registered non-registered output opposed combinatorial only CORE Generator System V1.5.
Table Core Name Cross Reference Xilinx Tool LogiBlox CORE Generator System V1.5 CORE Generator System V2.1 Core Name Multiplexers Multiplexer, Multiplexer, Multiplexer Multiplexer Core Location Tree Multiplexers LogiCORE-> Basic Elements-> Multiplexers
Basic Elements Multiplexer
Table Port Name Cross Reference LogiBlox MA[N:0]. MH[N:0] O[N:0] S[M:0] COREGenerator V1.5 D0[N:0] D3[N:0] O[N:0] COREGenerator V2.1 later MA[N:0]. MH[N:0] O[N:0] Q[N:0] S[M:0] ASET ACLR AINIT SSET SCLR SINIT Direction Input Output Output Input Input Input Input Input Input Input Input Input Input Description Multiplexer input buses Output non-registered gate Output registered gate Binary encoded select inputs Output Enable (BUFT based) Clock Clock Enable Asynchronous toAll Asynchronous Clear toAll Asynchronous Initialize Synchronous toAll Synchronous Clear toAll Synchronous Initialize
Page
September 1999
Table Parameter Names Cross Reference LogiBlox (.mod) module OPTYPE=TYPE_2 symbol INPUT_BUSSES BUS_WIDTH STYLE GATES Port_Width COREGenerator V1.5 (.log) 2-1, 3-1, Multiplexer COREGenerator V2.1 later (.xco) SELECT Bus_Multiplexer Type COREGenerator V2.1 Default setting
Component_Name
component_name number_of_input_buses input_bus_width multiplexer_construction output_options output_enable clock_enable ce_overrides
String Integer Keyword Keyword Keyword Keyword Keyword
blank lut_based registered false false sync_controls_overrid e_ce none none clear_overrides_set true
asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority Create_RPM Notes:
Check respective datasheet syntax, definition, default value each keyword. STYLE WIRED equivalent multiplexer-construction buft-based.
Keyword Keyword Keyword Keyword
create_rpm
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Multiplier
Dynamic Constant Coefficient Multiplier
Table Funtionality Comparison CORE Generator V2.1 LogiBlox CORE Generator V2.1 CORE Generator V1.5 CORE Generator System V2.1 Dynamic Constant Coefficient Multiplier subset CORE Generator System V1.5 Constant Coefficient Multiplier. CORE Generator System V2.1 supports reloadable constants opposed fixed constant CORE Generator System V1.5. CORE Generator System V2.1 provides selectable sign input data opposed pre-defined signed unsigned input CORE Generator System V1.5.
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Core Name Pipelined/Non-pipelined Constant Coefficient Multiplier Dynamic Constant Coefficient Multiplier Location Tree LogiCORE-> Math Multipliers Constant Coefficient Multipliers Math Functions Multipliers Constant Coefficient
Table Port Name Cross Reference LogiBlox COREGenerator V1.5 A[N:0] COREGenerator V2.1 later DATAA[N:0] SIGNEDA DATAB[M:0] LOADB Direction Input Input Input Input Description Parallel Data Input Dataa sign/unsigned status Constant Data Input Reload internal coefficients with Datab Clock Enable Clock pipelined version only Parallel Data Output High during reloadable time
PROD[M+N+1:0]
PROD[M+N+1:0] BUSY
Input Input Output Output
Page
September 1999
Table Parameter Names Cross Reference LogiBlox (.mod) COREGenerator V1.5 (.log) Non-pipelined Constant Coefficient Multiplier Pipelined Constant Coefficient Multiplier Component_Name A_Width Signed_Input_Data Coef_Width COREGenerator V2.1 later (.xco) SELECT Dynamic_Constant_Coeffi cient_Multiplier Type COREGenerator V2.1 Default setting
component_name variable_a_bit_width constant_coefficient_bit_wi constant_coefficient constant_coefficient_sign hex_coefficient pipeline clock_enable
String Integer Boolean Integer
blank true
Notes:
Coefficient Signed_Coefficient
Integer Boolean Boolean Boolean Boolean
false true true true
Check respective datasheet syntax, definition, default value ofeach keyword. COREGenerator V1.5 coefficient values always defined integer .log file pipeline parameter supported COREGenerator V1.5 instead seperate cores available: non-pipelined Constant Coefficient Multiplier Pipelined Constant Coefficient Multiplier.
September 1999
Page
Xilinx LogiCORE
Compatibility Guide: Multipliers
Variable Parallel Multiplier
Table Functionality Comparison CORE Generator V2.1 LogiBlox CORE Generator V2.1 CORE Generator V1.5 CORE Generator System V2.1 supports type implementation, whereas CORE Generator System V1.5 supports types implementation: Area Optimized Speed Optimized. unique implementation used CORE Generator System V2.1 Parallel Multiplier satisfies both area speed requirements. CORE Generator System V2.1 Multiplier core does have registered inputs which results less clock latency than that CORE Generator System V1.5. CORE Generator System V2.1 supports combinatorial architecture pipelined with without output register whereas CORE Generator System V1.5 supports only fully pipelined multipliers. CORE Generator System V2.1 supports optional Clock Enable, Asynchronous Clear/Set Synchronous Clear/Set whereas CORE Generator System V1.5 always provides Clock Clock Enable input.
Table Core Name Cross Reference Tool LogiBlox COREGenerator System V1.5 COREGenerator System V2.1 Core Name Parallel multiplier: Area optimized Location Tree Logicore Math Multipliers
Variable Parallel Multiplier
Math Function Multipliers Parallel Multiplier
Table Port Name Cross Reference LogiBlox COREGenerator V1.5 A[N:0] B[M:0] P[M+N+1:0] COREGenerator V2.1 later A[N:0] B[M:0] P[M+N+1:0] ASET ACLR SSET SCLR Direction Input Input Output Input Input Input Input Input Input Description Input Input Output Data (Product) Clock Clock Enable Asynchronous Asynchronous Clear Synchronous Synchronous Clear
Page
September 1999
Table Parameter Names Cross Reference LogiBlox (.mod) CORE Generator V1.5 (.log) Component_Name A_Width B_Width Signed CORE Generator V2.1 later (.xco) component_name a_width b_width pipelined_registers output_registers signed_type clock_enable ce_overrides Type String Integer Integer Keyword Keyword Keyword Keyword Keyword CORE Generator V2.1 Default setting blank registered registered signed false sync_controls_overrid e_ce none none clear_overrides_set
Notes:
asynchronous_settings synchronous_settings set_clear_priority
Keyword Keyword Keyword
Check respective datasheet syntax, definition, default value each keyword.
September 1999
Page

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