Virtex Delay-Locked Loops (DLL) Supporting highest bandwidth data

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Virtex Delay-Locked Loops (DLL) Supporting highest bandwidth data

Datasheet Thumbnail

Top Searches for this datasheet

Tech Topics
Virtex Delay-Locked Loops (DLL)
Supporting highest bandwidth data rates between devices requires advanced clock management technology such digital delay-lock loops (DLLs). circuitry allows very precise synchronization external internal clocks. Xilinx first deliver DLLs programmable logic offering four DLLs every Virtex device. Virtex-E family takes this technology next level with devices containing eight DLLs capable over .Figure shows block diagram circuitry. Virtex Series DLLs provide precise clock edges through phase shifting, frequency multiplication, frequency division. precise duty cycle generation critical high performance applications (like Double Data Rate, DDR) which slight shift duty cycle dramatically decrease overall system performance.
History
Phase-locked loops (PLL) have been used since 1940's analog implementations. Recent emphasis digital methods made desirable match signal phases digitally. digital delay-locked loop (DLL) place analog eliminates need separate noise-free ground power planes. Virtex DLLs also ensures reliable frequency range over variations manufacturing processes, temperature voltages.
Voltage Controlled Oscillator
Delay Locked Loop
CLKOUT Clock Distribution Network
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270
CLKIN
Control CLKFB
CLK2X CLKDV LOCKED
Figure Block Diagram Phased-locked loops implemented using either analog digital techniques, there trade-off each implementation. analog designed with finer timing resolution more frequency synthesis features small silicon area. However, PLLs have disadvantages that make their high-speed designs problematic, particularly when both high performance high reliability required. voltage-controlled oscillator (VCO) greatest source problems. Variations temperature, supply voltage, manufacturing process affect stability operating performance PLLs. DLLs, however, immune these problems. simplest form inserts variable delay line between external clock internal clock. clock tree distributes clock registers then back feedback DLL. control circuit adjusts delays that rising edges feedback clock align with input clock. Once edges clocks aligned, locked, both input buffer delay clock skew reduced zero. major advantages DLLs precision, stability, power management, noise sensitivity, jitter performance.
1/12/00 www.xilinx.com 1-800-255-7778
Virtex Delay-Locked Loops (DLL) Virtex FPGA series provides eight fully digital dedicated on-chip circuits which provide system clock generation, de-skewing clock signals distributed throughout device and/or board, other advanced clock domain control. addition frequency synthesis, optionally provides duty cycle correction phase shift.
DLLs
Digital Delay Locked Loops provide significant system benefits:
Achieving zero clock skew, effectively eliminating clock-distribution delay allowing digital closed-loop control. This control provides system clock rates ranging from Mb/s with 100-ps resolution. greatly reduces clock latency device, which turn reduces clock-to-out timing. Precise control system clocks, both internally device level well externally other devices board using independent DLLs Virtex Virtex-E device. Clock mirroring synchronize external devices. This also reduces system cost eliminating need external devices (Cypress Roboclock). DLLs support clock mirroring with less than skew. output clock taken off-chip synchronize external devices, thus eliminating race conditions improving chip-to-chip performance. assure synchronous start devices, LOCK output signal. startup PROGRAMMING DONE signal asserted TRUE state until lock achieved. shown Figure clock also connected feedback DLL, thereby de-skewing board's system clock less than
Input
Clock Mirror LVTTL LVTTL
Output
Feedback from External Trace
Figure Using Clock Mirror De-skew System Clock
www.xilinx.com 1-800-255-7778
1/12/00
Virtex Delay-Locked Loops (DLL) Multiply divide external clock produce clock device, allowing multiple clock domains. Designers also phase-shift clocks order support clock multiplexed systems. 2X-4X: Double quadruple incoming clock frequency, supporting designs that need fast internal operation slower external clock. This gives designer number choices. example, clocks routed board kept lower frequencies thus avoiding signal-to-noise issues while FPGA runs maximum speed same time. multiplied clocks have synchronized edges. Internal device clock speeds high MHz. Figure shows clock multiplication example.
Clock Multiplication (Multiply
Figure Clock Multiplication
CLK_DV: Divide clock 1.5, 2.5, optional 50/50 duty cycle correction available well. Often times applications monitor data high frequency, process data much lower clock frequency (e.g. read data MHz, processes data 38.5 MHz). Support clock-multiplexed applications creating four quadrant clock phases (0/90/180/ 270). Input four sequential bits clock period. Phase shift. Used with clock divider (e.g. data applied registered four clocks shifted degrees each). example adjusting clock phase shown Figure Figure illustrates dramatic impact multiple divide techniques phase shift conditioning noisy external clock. Selectable Division Values 1.5, 2.0, 2.5, 50/50 duty cycle correction available pair combine functions
1/12/00
www.xilinx.com 1-800-255-7778
Virtex Delay-Locked Loops (DLL)
180° Phase Shift Phase)
(180° Shift)
Figure Clock Phase Shift
Input
180° Phase Shift Used (180° Shift) (Divide (Multiply (180° Shift)
180° Phase Shift Clock Multiply Clock Divide Figure Phase Shift with Clock Multiply Divide
www.xilinx.com 1-800-255-7778
1/12/00
Virtex Delay-Locked Loops (DLL) Deliver superior chip-to-chip clock performance Mb/s LVDS LVPECL performance Virtex-E pairs SelectLinktechnology high speed Virtex-to-Virtex device communication Mb/s Virtex-to-Virtex device Mb/s Virtex-E device Virtex-E device pins) ZBTSRAM, Virtex-E device 125MHz SDRAM/SGRAM, SDRAM. precise 50/50 duty cycle achieve high-speed interface external devices Virtex Double Data Rate Virtex-E Double Data Rate Supply flexible power management. Analog PLLs require continuous clock. other hand, designers techniques stop, then restart, clock without acquiring lock, which would require several microseconds. This feature allows designer build "power save" mode into final application. Provide greater stability. DLLs operate reliably waveforms with frequency drifts adding maximum only jitter. This stability beyond typical (0.01%) most oscillators, where input jitter reflected output. Most analog PLLs filter jitter reference clock, intrinsic oscillator noise will still present. VCOs tend especially sensitive switching, variations, ground bounce. addition, less than optimal loop filter amplify jitter. Each loop filter must matched multiplier value, oscillator frequency, various parameters such analog frequency, phase gain. Digital Delay Locked Loops have such limitations, there finely tuned analog control elements. implemented with completely digital feedback mechanism that adjusts phase steps 50-60ps increments. Most discrete PLLs designed with specific application mind. Once external pins connected resistors, capacitors, power, ground, designer must insure signal couples into interferes with these pins. noise result either high jitter locking. Otherwise, designer experience significant signal integrity problems. today's high-speed circuit boards this puts additional burden design layout engineer provide separate power ground connections.
Eight High Performance DLLs
Drop-in Bandwidth Optimization with Virtex-E devices
Supporting high bandwidth data rates between devices requires advanced clock management technology offered DLLs. circuitry allows very precise synchronization external internal clocks. DLLs also provide precise clock edges during phase shifting, frequency multiplication, frequency division. Virtex-E bandwidth critical specifications listed Table Precise duty cycle generation critical high performance applications, such Double Data Rate (DDR) where slight shift duty cycle dramatically decrease overall system performance. Virtex-E family offers eight DLLs, allowing both internal external de-skew four systems clocks (Figure
1/12/00
www.xilinx.com 1-800-255-7778
Virtex Delay-Locked Loops (DLL) Table Bandwidth Critical Specifications Virtex-E Parameter Maximum Output Frequency Maximum Output Jitter Output Frequency Duty Cycle Based Virtex-E speed grade product Value MHz* 100ps
Zero Delay Internal Clocks CLK0 CLK0
Zero Delay External Clocks CLK0
CLK1
CLK1
CLK1
CLK2
CLK2
CLK2
CLK3
CLK3
CLK3
Each Clock Multiplied/Divided External Clocks Translated Figure Four System Clocks De-skewed
Maximizing Bandwidth
technique increasing bandwidth particular data port have signals change both edges clock, commonly referred Double Data Rate technique. Memory suppliers have already started support this type high performance technique increase memory bandwidth their devices. high frequencies, signal integrity limits clock performance, which limits bandwidth data. Bandwidth port immediately doubled architecture change data each edge system clock. precise clock duty cycle critical this technique. Since Virtex-E DLLs generate clocks with duty cycle guaranteed within 50%, system designers achieve maximum memory bandwidth application. Figure demonstrates Virtex-E DLLs help achieve maximum bandwidth application.
1/12/00
www.xilinx.com 1-800-255-7778
Virtex Delay-Locked Loops (DLL)
Internal External
SDRAM
Double Data Rate
Figure Virtex-E FPGA Interfacing SDRAM Memory
Virtex Advantages
comparison performance flexibility DLLs versus PLLs Table shows value designers obtain they Xilinx Virtex Series. DLLs beneficial designers require external interface performance above MHz. This includes interfacing memory devices numerous applications, well networking telecommunications applications. DLLs superior designs that have clock fan-out greater than when multiple clocks required. DLLs critical achieve maximum performance Double Data Rate (DDR) applications. DLLs required complete internal external clocks de-skew. With DLLs, Virtex-E allows four system clocks managed. Altera's APEX family only four PLLs, only their APEX family. Only maximum four PLLs available Altera APEX product support LVDS. eight DLLs Virtex-E support LVDS. DLLs require separate power ground planes. Altera's APEX APEX families' PLLs require designers PCBs with separate noise-free power ground planes. Table Virtex versus APEX Technology Feature Architecture Technology Quantity Output (MHz) Input Duty Cycle Output Duty Cycle Input Clock (MHz) Virtex 100% Digital Virtex-E 100% Digital APEX 100% Analog APEX-E 100% Analog
1/12/00
www.xilinx.com 1-800-255-7778
Virtex Delay-Locked Loops (DLL)
References
Related Xilinx Documents
XAPP132: "Using Virtex Delay-Locked Loop"
1999 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners.
www.xilinx.com 1-800-255-7778
1/12/00

Virtex Delay-Locked Loops (DLL) Supporting highest bandwidth data

Top Searches for this datasheet

Other recent searches