Virtex Million-Gate 100-MHz FPGA Technology Leading process

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Virtex Million-Gate 100-MHz FPGA Technology Leading process

Datasheet Thumbnail

Top Searches for this datasheet

PRODUCT INFORMATION-COMPONENTS
Virtex
Million-Gate 100-MHz FPGA Technology
Leading process technology, architectural innovation, intellectual property cores, ASIC design methodology combined Xilinx Virtex series.
dards simultaneously, eliminating challenges multiple signal standards system design. Virtex architecture, with 2.5volt supply voltage, offers industry's first devices capable directly interfacing beyond CMOS logic. Virtex series also supports important low-voltage standards such LVTTL, LVCMOS, GTL+, SSTL3.
irtex next generation Xilinx FPGA technology; series high-performance, high-density, system-level devices with revolutionary architecture, built with leading 0.25 micron process technology. These FPGAs meet rapidly growing demand high-speed system-level functions, helping create smaller, lower power, more reliable products with more features. begin Virtex begin designs today, because Xilinx been working Virtex designs today, closely with partners provide immediate because Xilinx been delivery Xilinx working closely with Alliance Series software libraries. This developEDA partners provide ment software solution ASIC designers provides immediate delivery higher performance, faster Xilinx Alliance Series compile times, unique innovations that make software libraries.d much easier develop very high-density, very high-performance FPGA designs. Virtex series, combined with Xilinx software, represents approach system-level design.
SelectRAM+
Virtex SelectRAM+ feature allows distributed RAM, block RAM, high-speed access external RAM. common example system-level designs requiring fast access varied configurations video processing application; where video frame data stored megabytes, line data stored kilobytes, pixel coefficient data stored bytes. megabytes storage, Virtex SelectI/O feature provides external synchronous DRAM access compatible with SSTL3 standard. Kilobytes data stored block SelectRAM memory; Virtex series offers blocks 133-MHz dual-port synchronous SRAM, yielding internal memory bandwidth gigabytes/second. bytes data, Virtex offers distributed SelectRAM memory. Pioneered Xilinx XC4000 family, distributed SelectRAM allows create fast flexible dual-port synchronous SRAMs.
SelectI/O
Virtex SelectI/O interface allows single device interface with multiple stan-
Architecture
Virtex architecture based logic cells, which 4-input look-up tables with register. Each contains four these logic cells. Each also contains special circuitry propagating carry, addition special circuitry implementing efficient multipliers. Combining these features with abundance registers makes very easy create very high speed, pipelined multipliers other applications.
accurately model interconnect delays Virtex Series, without placement information.
Cores
Because would take many designeryears create million-gate system from scratch, Xilinx made Virtex architecture very adaptable cores. optimizing segmented interconnect capability create fundamentally faster architecture, Xilinx reduced need architecture-specific cores. Therefore, easily implement cores with highly predictable performance using high-level languages.
Vector-Based Interconnect
Virtex series uses vector-based, variable-length, segmented routing architecture, optimized allow minimal interconnect delays; this routing faster more predictable than that non-segmented architectures. Vectorbased routing results short, predictable delays that sensitive minor changes placement. This allows synthesis tools
Availability
first Virtex device contains 250,000 system gates user pins. expected sampling second quarter 1998. Virtex devices that offer million system gates expected second half 1998.
Figure Virtex Functional Block Diagram
Xilinx Virtex architecture features Xilinx SelectRAM+ memory with distributed block RAM, plus high-speed access external SSTL3 standard, phase locked loops (PLL), Xilinx SelectI/O pins, Xilinx segmented-routing, vector-based interconnect.

Virtex Million-Gate 100-MHz FPGA Technology Leading process

Top Searches for this datasheet

Other recent searches