Shelly Davis, HardWire Marketing Manager, sdavis@xilinx.com Rapid

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Shelly Davis, HardWire Marketing Manager, sdavis@xilinx.com Rapid

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FPGAs ASICs
Shelly Davis, HardWire Marketing Manager, sdavis@xilinx.com
Rapidly Changing ASIC Conversion Market
programmable logic devices continue grow density, designers increasingly using FPGAs where they previously used ASICs. advantages off-the-shelf availability rapid prototyping make FPGAs very attractive solution. However, must answer question: will FPGAs both development production volumes, will convert design some form ASIC, such gate array standard cell, cost reduction?
FPGA-to-ASIC conversion market been dynamic over past years. Several companies have entered market, only find themselves financial trouble. Microchip Technologies exited after months business D.I.I. group purchased Orbit Semiconductor took $60M loss last quarter difficulties they continue experience. lack conversion business marketyou place that problems caused FPGAs both small ASIC vendor. problem caused instead difficulty accurately condevelopment verting todays complex PLDs. There production several factors contributing this. Most third party FPGA-to-ASIC convervolumes, will sion companies gate array technology convert translation. features todays FPGAs, such compliance design some ability implement bits form ASIC, such more, exceeds capability most gate array vendors. addition, growing gate array requirement fast, on-chip standard cell, perfectly suited SRAM-based FPGAs, fully diffused standard cell embedded cost reduction? RAM, gate array processes. Even most efficient gate array process will require gates convert FPGA ASIC RAM. design with bits RAM, this translate into minimum gates gate array. Therefore, design that
Third-Party ASIC Conversion Problems
slated cost reduction from FPGA smaller gate array achieve only small cost reduction because increase area required RAM. Gate array price erosion been fierce past years. While this price reduction benefited companies using gate arrays, some smaller gate array vendors poor financial condition, making difficult those companies sustain innovation. This lack product development causing them have difficulty converting many more complex FPGA designs. Leaving FPGA conversion third party gate array company complicated, well suited technologically, doesnt offer much cost reduction because 100K-gate FPGA often becomes 500K gate array under these circumstances.
Will
Limitation
True limitation achieved when there such abundance gates available device, that size determined solely number required pads. standard cell providers, with their dense core offerings, have been limited some time. process geometries below 0.5µ, many architectures, including FPGAs gate arrays, become limited. FPGAto-ASIC conversion company, depends achieving cost reduction through area shrink, limitation reduces cost benefit gate array. many cases, because customer needs pads provided FPGA, gate array device will equal size, order include same number pads. Size reduction translating programmable SRAM gates much smaller metal vias nullified. While features performance FPGAs continually increase include many ASIC-like features, actual implementation design methodology becoming dissimilar; architectur-
Diverging Architectures
ally, FPGA technology ASIC technology diverging. ability architecture converted other will require more than just re-targeting specific ASIC vendors libraries. Gate array processes without embedded structures that specific original FPGA will quickly exceed gate count capability. addition, indepth knowledge FPGAs functionality detailed specifications industry standards like will basic requirements. Furthermore, ability provide accurate timing I/Os critical system performance will essential convert these newer, more complex designs. FPGA designers depend ASIC cost reductions will find their options changing over next months. Many smaller ASIC vendors will de-emphasize FPGA conversions because they lack capability convert them cost-efficient technically effective manner. meantime, FPGA price gate continues decline point that, system gates below, FPGAs considered production volume formerly ASIC applications. Companies that continue provide FPGA-to-ASIC conversions will need offer increasingly FPGA-specific solutions, because generic gate array process will serve requirements features. Xilinx example company that provides specialized solution FPGA conversions. Xilinx HardWire Business Unit continues develop ASIC technologies suitable converting complex, RAM-intensive FPGAs. Xilinx recently introduced FpgASIC architecture which provides dense gate array logic surrounded ring that replicates Xilinx FPGA I/O. FPGA features built into base arrays, further reducing risk conversion problems. Xilinx HardWire devices excellent cost reduction path FPGAs above system gates especially suited most dense FPGAs. Another company specializing Clear Logic Corporation, offers solution Altera FPGAs only. Clear Logic offers their proprietary ClearFire technique laser cutting metal fuses base arrays which closely resemble logic resources Altera Flex8000 family FPGAs. advantage customer that optimizing processes, libraries, feature sets convert Altera PLDs exclusively, risk con-
Architecture
verting design incorrectly reduced. future, this type focus will required provide accurate FPGA cost reductions. future, FPGA technology will increasingly suited applications previously considered gate array standard cell territory. Many logic designers realizing that they take advantage FPGA time-to-market benefits still achieve gate array cost point volume production. However, options translating FPGA ASIC changing. Because complexity FPGA features density RAM, many smaller gate array conversion vendors dropping market. limitation both FPGAs gate arrays minimize cost reduction benefits unless creative options implemented. Architecturally, FPGAs gate arrays also diverging. Differing design methodology implementations very inefficient specifically accounted conversion process. models success conversion market will companies specialize converting single architecture, such Clear Logic with Altera devices, Lucent with MACOand Xilinx with HardWire FpgASICs. These will options that provide closest match most expertise 200K+ gate FPGAs today.
Figure Architecture
Conclusion

Shelly Davis, HardWire Marketing Manager, sdavis@xilinx.com Rapid

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