Programmable Logic Mixed Voltage Applications advanced, deep-subm

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Programmable Logic Mixed Voltage Applications advanced, deep-subm

Datasheet Thumbnail

Top Searches for this datasheet

5V3V
Programmable Logic Mixed Voltage Applications
advanced, deep-submicron
components directly interface with 3.3V devices. Table lists Xilinx component product families that employed mixed-voltage systems. Xilinx device inputs maintain their excellent protection against electrostatic discharge (ESD), even mixed-voltage applications.
fabrication processes resulting rapidly increasing density performance programmable logic devices. However, device geometries shrink below microns, smallest transistors cannot withstand volts without damage. Thus, largest fastest devices based lower supply voltages. example, XC4000XL FPGA family, featuring industry's highest-capacity, high-performance FPGAs, based 3.3V standard. reap benefits advanced process technology including increased performance, increased density, lower power consumption, lower price many programmable logic users making transition from standard lower voltages. This transition affects only supply voltage, also signaling levels. Xilinx actively taking lead working with programmable logic users plan orderly transition lower voltage standard. Xilinx introduced Zero+ product line, industry's first 3.3V introduced FPGAs, 1993. Since then, number 3.3V product offerings Zero+ product line, increased dramatically. However, many other system components industry's first remain available versions only. Thus, mixed-voltage systems em3.3V FPGAs, ploying 3.3V com1993. Since then, ponents likely rule exception number 3.3V rather than future. immediate Xilinx products have been product offerings designed with this mixed-voltage increased environment mind. input tolerance been designed into dramatically.d many Xilinx 3.3V devices; these devices accept signals I/Os drive levels into device, eliminating interface issues. Many Xilinx
Mixing 3.3V Devices
When mixing 3.3V devices same board, signaling levels compatible with both types components needed signals lines connecting types components. Since both types supply share common ground, there problems interfacing logic levels either direction, there compatibility issues logic High levels.
3.3V Devices Driving Inputs Devices
lowest output High voltage (VOH) device must exceed requirements device. Minimum Xilinx 3.3V devices 2.4V, well above 2.0V minimum High level signaling. (This includes XC3000L, XC3100L, XC4000XL FPGA families XC9500 CPLD family when VCCIO 3.3V.) Thus, Xilinx 3.3V devices drive inputs devices with TTL-compatible input thresholds, including Xilinx devices. (Note: Some Xilinx devices programmed CMOS input thresholds; these devices must configured TTL-compatible inputs directly driven from 3.3V device.)
Xilinx
Devices Driving Inputs 3.3V Devices
highest device output voltage must force excessive current into input 3.3V device. input structures Xilinx 3.3V FPGAs include input protection circuits. These protection circuits XC3000L
Single Supply
Device Family XC3000A XC3100A XC4000E/EX XC5200 XC9500 Device Family XC3000L XC3100L XC4000XL
Accepts 3.3V Compatible Inputs1
Drives 3.3V Devices With limiting resistor With limiting resistor With limiting resistor With limiting resistor Drives Devices
Features quiescent current High performance Highest density performance Cost-effective in-system-programmable, locking
Table Xilinx products supply voltage options
Note: Inputs must configured thresholds
Single Supply 3.3V
Accepts Compatible Inputs With limiting resistor With limiting resistor
Features Very powerdown quiescent current High performance Highest density performance
Device Family Dual Supply
VCCIO/VTT 3.3V XC9500
Accepts Compatible Inputs
Drives Devices
Features
Mixed-voltage system capable
XC3100L devices designed 3.3V inputs. However, protection circuits XC4000XL devices designed withstand levels. Most devices have complementary CMOS outputs where reach rail. (All Xilinx FPGAs CPLDs, except XC4000 series devices, have complementary CMOS outputs.) When driving XC3000L XC3100L inputs (and most other 3.3V devices) from such device, then input current must limited series resistor less than 150. This guarantees input current below 10mA, flowing through input protection diode backwards into 3.3V supply. That amount input current generally considered safe, causing neither metal migration latch-up problems. Care must taken avoid forcing nominally 3.3V supply voltage above 3.6V maximum whenever large number active High inputs drive 3.3V device, potentially causing 3.3V supply current reverse direction. 3.3V power should before driving device inputs from device. structures XC4000XL FPGAs have been designed tolerate being driven rail low-impedance source. These
3.3V FPGAs directly driven devices with either CMOS outputs. Power supply sequencing problem; inputs driven either before after 3.3V power supplied without risking damage devices. mixed voltage systems, XC7300 XC9500 CPLDs driven directly inputs when 3.3V operation (i.e., CCIO 3.3V). input protection diodes these CPLDs always connected power line, allowing them tolerate inputs without need currentlimiting resistors.
device "totem-pole" n-channel-only outputs XC4000E/EX FPGA series), reduced threshold series resistor eliminated, provided nominally supply does exceed 5.25. Thus, XC4000E XC4000EX FPGAs directly drive 3.3V device without need current-limiting resistors.

Programmable Logic Mixed Voltage Applications advanced, deep-subm

Top Searches for this datasheet

Other recent searches