PETER ALFKE (peter@xilinx.com) article will give overview device

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PETER ALFKE (peter@xilinx.com) article will give overview device

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CMOS Characteristics
PETER ALFKE (peter@xilinx.com)
article will give overview device characteristics, help create better, more reliable designs. Xilinx devices CMOS technology, which means there types transistors: N-channel transistors, turned positive gate voltage. P-channel transistors, turned negative gate voltage. either transistor, turn-on voltage must exceed ~1-V threshold voltage. Figure shows complementary inverter, consisting p-channel pull-up transistor n-channel pull-down transistor with both gates driven common.
Figure Complementary Inverter Buffer.
Outputs
Xilinx devices, except XC9500 family original XC4000 family, have complementary outputs. However, XC4000E, XC4000EX, Spartan families, must specify this option explicitly. default these devices "TTL output" described below. Complementary outputs (See Figure pulled "rail-to-rail," maximizing output swing, especially desirable when driving other CMOS logic. With load, output voltage swings precisely between ground with voltage drop (the device output specifications 3.86-V refer particular loading conditions). "TTL outputs" (See Figure have reduced voltage swing, which achieves faster performance, especially High-to-Low transition when measured usual 1.5-V level. term "TTL output" actually misnomer, derived from similarity with "totem-pole" structure bipolar outputs that only transistors pull-down pull-up. Similarly, "TTL output" structure CMOS uses only n-channel transistors pull-down pull-up. This reduces
output High voltage (Voh) threshold voltage, 1.5-V) below Vcc. 3.3-V supply voltages (and lower), complementary "rail-torail" CMOS only available (and meaningful) output option. output impedance FPGAs state, High state. output impedance XC9500 CPLDs state, High state XC9500 original XC4000 devices have TTL-level outputs only. XC4000E, XC4000EX, Spartan devices, TTL-output default, changed complementary output. data sheet specifies >3.5-V, complementary output. specified 2.4-V, TTL-level output. Note that output driving long interconnect line board trace reflections that drive output well above well below ground. Such reflections usually last just nanoseconds (<10 usually suppressed protection diodes.
Figure Totem-Pole "TTL Output" Buffer
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CMOS
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Inputs
input thresholds compatible with older systems, popular bus-oriented systems. therefore default most popular input option. means that voltage below 1.2-V interpreted Low, while voltage above 1.4-V interpreted High. This mimics behavior bipolar circuits where this threshold determined forward-biased silicon diodes. Xilinx FPGAs, this "TTL" threshold achieved reduced supply voltage input buffers, controlled global option that affects device inputs. CMOS inputs specified such that voltage below half supply voltage interpreted Low, voltage above half interpreted High. actual threshold usually somewhat lower than
Vcc. XC4000XL devices 38-40% Vcc. devices, input threshold globally selectable either "TTL" "CMOS"; CMOS input option offers additional noise immunity reduces static power consumption. Inputs have small amount hysteresis, which makes threshold rising edge little higher than falling edge. Slow transitions will, therefore, switch cleanly, long there system noise greater than real system, this hysteresis does make much difference. Slow transitions data, control, other combinatorial inputs just cause extra unpredictable delay. Slow transitions with more than rise- fall-time very dangerous, since they invite noise ground-bounce cause double triggering.

PETER ALFKE (peter@xilinx.com) article will give overview device

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