XAPP077 January, 1997 (Version 1.0) Summary Metastability unavoid

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XAPP077 January, 1997 (Version 1.0) Summary Metastability unavoid

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Metastability Considerations
XAPP077 January, 1997 (Version 1.0) Summary
Metastability unavoidable asynchronous systems. However, using formulas test measurements supplied here, designers calculate probability failure. Design techniques minimizing metastability also provided. Xilinx Families XC7300, XC9500
Introduction
Metastability digital systems occur when data input flip-flop asynchronous clock, which lead setup hold time violations. Metastability appear flip-flop that switches late doesn't switch all. present brief pulse flip-flop output (called runt pulse) cause flip-flop output oscillations. these conditions cause system failures. usual cause metastability setup time violation, demonstrated Figure setup time violation unavoidable, possible calculate frequently flip-flop will fail. industry standard formula Mean Time Between Failures (MTBF) metastable flip-flop given MTBF (e(-C2*tMET)) (C1*Fc*Fd) where: 2.718281828. tMET time delay metastability resolve itself clocking frequency data frequency constant representing metastability catching setup time window constant describing speed with which metastable condition resolved
This formula been used over last years found accurate. variables expression functions flip-flop design, process technology, clocking rate, data switching speed, which discussed following sections.
fDATA
fCLK
Figure Metastability Measurement Circuit
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Metastability Considerations
Metastability Measurement
test metastability, flip-flop isolated within CPLD clock applied with asynchronous data input. data applied independent clocking source that related signal attached flip-flop clock input. flip-flop eventually encounters metastable state, which observed comparing state flipflop with it's state subsequent time, before state should have changed again. state samples match, metastable condition occurred counter incremented. other questions must also answered, given time parameters corresponding their longevity: often does metastability occur (related C1)? long does metastable state persist when does occur (related C2)?
Metastability Constants Xilinx CPLDs
shown Figure data applied flip-flop asynchronously with respect clock input. output flip-flop passes other flip-flops simple comparison outputs made. Note that flip-flop clocked inverted clock. flip-flop identical, logical will captured flip flop indicating metastable event occurred. degrees with volts, several XC7300 XC9500 devices were repeatedly measured. knowing MTBF values tMET times, constants obtained through following expressions: e(-C2* tMET (MTBF Fc*Fd) MTBF) tMET Frequency clock (10Mhz these tests) Frequency data (1Mhz these tests) tMET (Ln(MTBF C1))
MTBF inversely proportional clock rate (Fc) data rate (Fd). designs having asynchronous data, most designers know their data rate, difficult estimate MTBF accurately. Usually, small time period considered seconds, example) number clocks data transitions during small time used define time delay increased, number failures decreases dramatically. counting number failures over time, MTBF directly calculated. values derived formula which includes counts number failures time delays sampling.
XC7300 family: 3.49 *109 1.0238 10-15
XC9500 family 6.1172 *109 9.554 *10-18
shown Figure MTBF goes dramatically additional time delay sampling outputs increases. point reference, year about 31.5 million seconds.
Month
XC9500
MTBF (sec.)
Hour
XC7000
tMET (ns)
Figure MTBF versus tMET
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XAPP077 January, 1997 (Version 1.0)
Design Considerations
determine safely flip-flop, using previous equation: Determine desired MTBF. Insert values into equation chosen flip-flop. Determine whether data transitions asynchronous synchronous with respect clock. they asynchronous, average data switching rate calculated step follows. they synchronous, quoted setup hold times. Calculate tMET using formula: tMET (Ln(MTBF C1)) flip-flop passes through output that causes have delays, that delay tMET expression. Another decrease effects metastability cascade multiple flip-flops. Because metastability statistical effect, possibility metastability diminishes cascaded flip-flops. Figure shows typical application. Synchronizing Flip-Flop
Also, setup hold time violations unavoidable, additional time delay added provide more settling time.
Conclusion
Metastability unavoidable asynchronous systems careful attention design usually prevent problem violating setup hold times. Other design techniques exist improving metastability performance described following references.
References
ANSI/IEEE Std. 1014-1987, IEEE Standard Versatile Backplane Bus: VMEbus, Appendix (Metastability Synchronization), 281-295 Metastable behavior digital systems, Kleeman Cantoni, IEEE Design Test Computers, Dec. 1987 Measured Flip-Flop Responses Marginal Triggering. IEEE Transaction Computers, vol. C-32, Dec. 1983, 1207-1209. High Speed Digital Design Handbook Black Magic), H.W. Johnson Graham, Prentice-Hall, 1993,
Stable State
Figure Synchronizing with Cascaded Flip-Flop
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XAPP077 January, 1997 (Version 1.0) Summary Metastability unavoid

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