XC4000XV FPGA family delivers densities 500,000 system gates (20,000 l

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XC4000XV FPGA family delivers densities 500,000 system gates (20,000 l

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XC4000XV:
XC4000XV FPGA family delivers densities 500,000 system gates (20,000 logic cells). This family includes four devices, offering system performance greater than MHz, featuring 2.5-volt internal operation with 3.3-volt I/Os allow optimum performance compatibility with existing voltage standards. announced five-year roadmap last January, which clearly defined plans provide higher-density FPGA families advanced processes. course months, have delivered members XC4000XL family high-density high-performance FPGAs. These widely accepted customers leaders density performance," said Roelandts, Xilinx president chief executive officer. "With migration 0.25-micron process, XC4000XV FPGA family represents next leadership step bring benefits FPGA reconfigurability time-to-market advantages traditional ASIC users demand high-performance high-density logic."
Introducing Industry's First 500K Gate FPGA Family
advanced product, System Explorer. using XC40125XV, highest density programmable logic device available today, able achieve these density levels."
Architectural Advantages XC4000X Series
XC4000XV family more advanced implementation XC4000EX/ architecture, which uses segmented routing distributed RAM. These features make ideal platform implementing cores. example, segmented routing architecture allows predictable performance regardless device size much logic employed. With non-segmented routing used competitors, cores will slow down unpredictably surrounding logic added when designs moved larger devices. performance predictability requirement designs using intellectual property (cores) because want choose cores independently device density, expect core's performance remain same design evolves. addition, footprint-compatibility advantages, current XC4000XL customers easily immediately upgrade higher-density XC4000XV products.
Delivering ASIC Performance Density, Today
Digital designers have traditionally used custom ASIC devices considering time-to-market benefits that Xilinx high-density, high-performance FPGAs offer. According Jordan Selburn, principal analyst Dataquest, Xilinx XC4000XV family, conjunction with Xilinx HardWire ASIC capability, address approximately percent 1997 gatearray design starts, based XC4000XV maximum performance density levels. Vincent Coli, director product marketing Aptix, leader reconfigurable system prototyping solutions, says Xilinx their density because it's here today. customers demanding several million gates programmable logic most
XC4000XV Family
Device Logic Cells System Gates XC40125XV 10,982 80,000 265,000 XC40150XV 12,312 100,000 300,000 XC40200XV 16,758 130,000 400,000 XC40250XV 20,102 180,000 500,000 Available Q198 1H98 1H98

XC4000XV FPGA family delivers densities 500,000 system gates (20,000 l

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