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Tech Topics Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS) Introduction
need higher bandwidth accelerates, system designers choosing differential signaling satisfy high bandwidth requirements while reducing power, increasing noise immunity, decreasing emissions. LVDS swing, differential signaling technology providing very fast data transmission, common-mode noise rejection, power consumption over broad frequency range. Virtex-E family delivers programmable industry's highest bandwidth most flexible differential signaling solution direct interfacing industry-standard LVDS devices. With pairs operating Megabits second (Mb/s) pairs operating over Mb/s, Virtex-E family supports multiple Gb/s ports while maintaining high signal integrity with power consumption. Unlike other solutions, Virtex-E LVDS I/Os support input, output, signaling, providing system designer unparalleled flexibility board layout. Table summarizes LVDS support Virtex-E family. Table Virtex-E High-Bandwidth LVDS Support Summary LVDS Configuration Point-to-Point Multi-Drop Bandwidth pairs Mb/s pairs Mb/s pairs Mb/s
LVDS Standard
LVDS defined industry standards: ANSI/TIA/EIA-644 IEEE 1596.3 SCI-LVDS. ANSI/TIA/EIA-644 standard defines LVDS electrical specs including driver output receiver input electrical characteristics. does cover functional specifications, protocols, transmission medium characteristics since these application dependent. ANSI/TIA/EIA-644 more generic standards, intended multiple applications. IEEE 1596.3 SCI-LVDS standard subset (Scalable Coherent Interface). SCI-LVDS standard defines electrical specifications physical layer interface SCI. similar ANSI/TIA/EIA-644 standard differs intended usage interface. IEEE committee created SCI-LVDS standard communication between nodes. Virtex-E LVDS solution conforms ANSI/TIA/EIA-644 standard. Table summarizes pertinent Virtex-E LVDS specifications.
12/17/99
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Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS) Table LVDS Specifications Parameter VCCO Output High Voltage Output Voltage Differential Output Voltage High High Output Common-Mode Voltage Differential Input Voltage High High Input Common-Mode Voltage Differential input voltage 1.25 across signals Common-mode input voltage 1.25 1.125 1.25 1.375 across signals across signals across signals Conditions 2.375 1.25 1.425 1.075 2.625 1.25 Units
Advantages
LVDS specified technology process independent. LVDS tolerant. Common-mode noise equally removed conductors rejected receiver. transmission medium defined standard. medium tailored meet specific application requirements. typical LVDS voltage swing resulting higher transfer rate lower power consumption.
Configurations
There configurations that used LVDS applications, point-to-point multi-drop. Virtex-E family supports both LVDS configurations. Point-to-Point point-to-point configuration, there transmitter receiver. LVDS driver current source that drives differential pair lines. typical current drive receiver high impedance. majority driver current flows across termination resistor generating about receiver inputs (Figure Multi-Drop multi-drop LVDS configuration transmitter multiple receivers. differential termination resistor placed close last receiver (Figure
Applications
Applications LVDS include: Switches Repeaters Hubs Routers Wireless base stations Flat panel displays Digital cameras Printers Copiers
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Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS) Multimedia peripherals Backplane applications
Terminations
LVDS widely used high-speed point-to-point interface well multi-drop applications. Depending exact interconnect topology, precision resistors required match specific impedance characteristics minimize reflection ensure high signal integrity. Virtex-E family supports most flexible LVDS high-speed interface supporting flexible external termination scheme. This enables system designers select resistor values most appropriate maximum performance.
Point-to-Point
Figure shows schematic standard LVDS driver driving Virtex-E receiver. LVDS driver drives transmission lines into Virtex-E LVDS receiver. single-ended transmission lines micro-strip, strip-line, differential twisted pair, similar balanced differential transmission line.
Standard LVDS Driver
LVDS_IN DATA Transmit LVDS_IN DATA Receive
VIRTEX-E FPGA
x232_02_092499
Figure Standard LVDS Driver Driving Virtex-E LVDS Receiver Figure shows complete schematic Virtex-E LVDS line driver receiver. standard LVDS termination resistor connected across LVDS_OUT LVDS_OUT outputs transmission line. resistors RDIV attenuate signals from Virtex-E LVDS drivers provide matched source impedance (series termination) transmission lines. Standard termination packs available from Bourns. Other resistor vendors provide termination networks with 16-pins pack.
Virtex-E FPGA 2.5V DATA Transmit VCCO 2.5V LVDS Output
Bourns Part Number CAT16-LV4F12 RDIV
Bourns Part Number CAT16-PT4F4 LVDS_OUT LVDS_OUT
Virtex-E FPGA
DATA Receive
x232_05_100499
Figure Virtex-E LVDS Line Driver Receiver Schematic Virtex-E LVDS driver meets ANSI/TIA/EIA-644 LVDS specifications. matched source impedance Virtex-E LVDS driver absorbs nearly differential reflections from
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Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS) capacitive load LVDS destination, reducing standing waves, undershoot, signal swing data bursts clocks. Data clocks transmitted over cables longer than electrical length, limited only quality cable (the cable attenuation caused skin effect losses high frequencies). Mb/s data rate, clock achievable with Virtex-E speed grade devices. "XAPP233: LVDS Transceivers Mb/s using General-Purpose I/O" details reference design.
Multi-Drop
Multi-drop LVDS configuration allows many receivers driven Virtex-E LVDS driver. With simple source differential termination, Virtex-E LVDS driver drive lines with fanouts making Virtex-E LVDS I/Os suitable broad variety high-load applications. Figure illustrates Virtex-E LVDS driver driving LVDS receivers multi-drop configuration. receivers either Virtex-E receivers other off-the-shelf LVDS receivers. LVDS signal driven from Virtex-E LVDS driver, daisy-chained with transmission lines stubs LVDS receivers. Each LVDS receiver connected main multi-drop lines every 2.5" multi-drop line length 50". Each LVDS receiver line maximum stub length with transmission line impedance ground, differential impedance between stubs. termination resistor placed across differential lines close last LVDS receiver. Resistors RDIV attenuate signals from Virtex-E drivers provide source impedance (series termination) transmission lines. source impedance used because added load LVDS receivers brings line down effective average impedance capacitor CSLEW reduces slew rate from Virtex-E LVDS driver, resulting smaller reflections less ringing receivers.
VIRTEX-E FPGA
61.9 2.5" 2.5" 2.5" LVDS_TERM
2.5V
DATA Rdiv 63.4 Cslew 2.5" 61.9 Stubs: (165 OUT1 Virtex-E other LVDS Receivers OUT1 OUT2 OUT2 OUT20 OUT20 2.5" 2.5" LVDS_TERM
Vcco 2.5V
DATA
DATA
DATA
x231_04_092099
Figure Virtex-E 20-load Multi-Drop LVDS Schematic
single-ended transmission lines micro-strip, strip-line, single-ended equivalent twisted pair, similar balanced differential transmission line.
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Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS) resistors RDIV should placed close Virtex-E driver outputs. parallel termination resistor should placed close last LVDS receiver inputs multi-drop line. capacitor CSLEW should placed close resistors RDIV. Virtex-E multi-drop LVDS driver adheres ANSI/TIA/EIA-644 LVDS standard input level specifications, fully compatible with LVDS receivers from National Semiconductor other companies. maximum data rate Mb/s clock 155.5 Virtex-E speed grade device. Reliable data transmission possible LVDS receivers over multi-drop line length inches, limited only skin effect losses trace.
Waveform
typical LVDS output waveform Virtex-E devices shown Figure
Swing 1.25 mid-point.
Computed Signal Differential
Figure LVDS Output Waveform
Virtex Advantages
Virtex-E devices first programmable logic devices available market incorporating advanced LVDS capability with support other differential standards (Bus LVDS LVPECL). Unlike other announced architectures (for example, APEX VirtexE LVDS capability provides abundance LVDS-capable user clock pins, architectural flexibility shown Table address true high-speed system issues. This capability works concert with robust delay locked loop (DLL) technology enabling designers achieve maximum performance their LVDS applications.
12/17/99
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Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS)
Table Virtex-E High-Bandwidth LVDS Solution Summary Feature Offer LVDS standard feature LVDS LVDS LVPECL LVDS Configurations Maximum Bandwidth Termination High-Speed Differential Clock Pairs Maximum differential pairs Maximum Speed Serializer/Deserializer Clock Recovery
Virtex-E Yes, devices, packages, speeds Point-to-point, Multi-drop, Multi-point Gb/s (622 Mb/s/pair pairs) Gb/s (311 Mb/s/pair pairs) Flexible External Termination In/Out Mb/s Flexible
APEX Large device only, fast speed only (More Point-to-point Multi-drop Gb/s (622 Mb/s pairs) Inflexible Internal Termination Outputs Dedicated input output pairs. layout friendly. Mb/s Dedicated
APEX internal termination outputs cannot guarantee high signal integrity inability impedance match.
Unlike other solutions that only offer LVDS capability most expensive highest speed grade options, Virtex-E LVDS capabilities standard features available Virtex-E device/package combinations. Virtex-E family offers option LVDS pairs operating Mb/s LVDS pairs operating over Mb/s achieve over Gb/s aggregate bandwidth. This enables system designers support multiple Gb/s ports architecture high-performance data communication systems. Table demonstrates high-bandwidth LVDS solution provided Virtex-E family. addition offering high-performance highly flexible LVDS solution, Xilinx also works closely with other component vendors (e.g., Bourn resistor pack) ensure interoperability help system designers further reduce overall design complexity system cost. Table Virtex-E High-Bandwidth LVDS Solution Summary Standard Virtex-E LVDS APEX LVDS Type Differential Differential Mb/s Mb/s Gb/s Gb/s Gb/s Gb/s
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Virtex-E High Performance Differential Solutions: Voltage Differential Signalling (LVDS)
References
Standards
ANSI/TIA/EIA-644 http://www.eia.org/eng IEEE1596.3 http://www.ieee.org
Related Xilinx Documents
XAPP230: "The LVDS Standard" XAPP231: "Multi-drop LVDS" XAPP232: "The LVDS Drivers Receivers: Interface Guidelines"
XAPP233: "LVDS Transceivers Mb/s using General Purpose I/O"
1999 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners.
12/17/99
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