Core Specifics Supported Family Device Tested CLBs Clock IOBs IOBs1 Pe

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Core Specifics Supported Family Device Tested CLBs Clock IOBs IOBs1 Pe

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ADPCM
Core Specifics Supported Family Device Tested CLBs Clock IOBs IOBs1 Performance Xilinx Tools Special Features Virtex V150-6 1530 M1.5i Distributed Provided with Core Documentation User Guide, Design Guide Design File Formats EDIF netlist, VHDL available extra Constraints File xpcmcod_pads.ucf Verification Testbench, Test Vectors Instantiation Templates VHDL, Verilog Reference Designs Application Notes None Additional Items Bit-accurate model Simulation Tool Used Synopsys VSS, ModelSim Support Support provided
Note: Assumming core I/0s routed off-chip Using coding, 8-bit wide
Integrated Silicon Systems, Ltd.
Malone Belfast Northern Ireland Phone: 1232 664664 Fax: 1232 669664 E-Mail: info@iss-dsp.com URL: www.iss-dsp.com
Features
Supports Spartan, SpartanTM-II, VirtexTM, VirtexTM-E devices Supports, G.721, G.723, G.726, G.726a, G.727, G.727a standards channel duplex encoding decoding Online configurable different compression rates, µ-law A-law each encoding decoding channel generic parameter VHDL version Coding (encode decode) data sample clock cycles (min) work both burst continuous modes Multiplication mapped onto single multiplier compact implementation Conforms fully test vectors
Applications
Digital Enhanced Cordless Telecommunications (DECT) Video conferencing Telecommunications
January 2000
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ADPCM
ENCODER kbit/s Input Input Signal Difference Signal Signal Estimate Reconstructed Signal
[13/7:0] ChCFG[7:4] ChAddrIn[3:0]
ChReset
Convert Uniform
Adaptive Quantizer Predictor
[4:0]
ADPCM Output
Channel Memory
Adaptive Predictor
Quantized Difference Signal
Inverse Adaptive Quantizer
ADPCM Input
[4:0] ID[4:0] ChCFG[3:0] ChAddrin[3:0] ChADDRIn[3:0]
ChReset
Inverse Convert Adaptive Uniform Quantizer
Quantized Difference Signal
Reconstructed Signal
Signal Estimate
Convert
Synchronous Adaptive Coding Predictor Adjustment
[13/7:0]
kbit/s Output
Channel Memory
Adaptive Predictor
x8943
ChAddrIn[3:0] ChCFG[3:0] DECODER
Figure ADPCM Block Diagram
General Description
standard, G.726 includes specifications standards, G.721, G.723, G.726a, G.727, G.727a. specifies requirements conversion kbit/s pulse code modulation (PCM) channel from kbit/s channel, using Adaptive Differential Pulse Code Modulation (ADPCM) transcoding technique. ADPCM core compliant with G.726 standard supports duplex channel coding. input channel multiplexing serial parallel conversion circuitry added suit target system required. core online configurable terms compression rates. been tested verified fully compliant using standard test vectors.
Functional Description
ADPCM partitioned into modules shown Figure described below.
namely Convert Uniform block, Channel Memory block, Adaptive Quantizer block, Inverse Adaptive Quantizer block, Adaptive Predictor block. Subsequent conversion A-law µ-Law input signal uniform PCM, difference signal obtained, subtraction estimate input signal from input signal itself. adaptive 31-, 15-, 4-level quantizer used assign five, four, three binary bits, respectively, value difference signal transmission. inverse quantizer produces quantized difference signal from these same five, four, three binary bits, respectively. signal estimate added this quantized difference signal produce reconstructed version input signal. Both reconstructed signal quantized difference signal operated upon Adaptive Predictor, which produces estimate input signal, thereby completing feedback loop. CLK, DSS, ChReset signals control encoder's operation each duplex channel. When ChReset signal asserted, control word, ChCFG, will loaded corresponding Channel Memory, which specified channel address, ChAddrIn. Meanwhile, busy signal, high indicate that
Encoder Operation
ADPCM encoder consists five functional blocks, 3-72
January 2000
Integrated Silicon Systems, Ltd. encoder operation. When encoder procedure completed, returned low. During encoding process, signal, ESI, used indicate when valid result output. ChReset signals control decoder's operation each duplex channel.
Core Modifications
ADPCM core modified meet specific design needs. Modifications include: Number channels Compression ratios supported Coding laws supported (A-law m-law)
Convert Uniform
When asserted, Convert Uniform block reads data from input, loads control word from Channel Memory convert data uniform signal.
Channel Memory
This bits wide bits deep number channels this implementation) memory that stores control word, ChCFG, specified channel address, ChAddrIn. Channel Memory embedded within core uses distributed memory FPGA.
Pinout
Pinout ADPCM core been fixed specific FPGA I/O, allowing flexibility with user's application. Signal names described Table
Verification Methods
Complete functional timing simulation been performed using Synopsys Model Technology ModelSim.
Adaptive Quantizer
Adaptive Quantizer block provides specified compression rate, e.g. specified channel control word, ChCFG, quantize difference signal transmission.
Recommended Design Experience
Users should familiar with design methodology Xilinx design flows including VHDL/Verilog language syntax, component instantiation, synthesis, simulation.
Inverse Adaptive Quantizer
Inverse Adaptive Quantizer block produces quantized version difference signal scaling factor specified ChCFG.
Ordering Information
information ADPCM core, please contact Integrated Silicon Systems directly from address available first page this datasheet.
Adpative Predictor
primary function Adaptive Predictor block compute signal estimate from quantized difference signal. adaptive predictor structures used, sixth order section that model zeros second order section that models poles input signal.
Decoder Operation
decoder includes structure similar Inverse Adaptive Quantizer block Adaptive Predictor block encoder, together with uniform A-law µ-law conversion synchronous adjustment.
Convert
This block counterpart Convert Uniform block encoder. performs uniform A-law µ-law conversion.
Synchronous Coding Adjustment
Synchronous Coding Adjustment block prevents cumulative distortion occurring synchronous tandem coding (ADPCM-PCM-ADPCM, etc., digital connections) under certain conditions. synchronous coding adjustment achieved adjusting output codes manner that attempts eliminate quantizing distortion next ADPCM encoding stage. encoder, CLK,
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ADPCM Table Core Signal Pinout Signal Description Direction Input Interface Signals S[13/7:0] Input word encoding. Uniform input uses bits, S[13:0] (A-law) bits, S[12:0] law). Input input uses bits, S[7:0] ID[4:0] ADPCM input word ID[4] no.1 polarity ID[4:3] 2-bit ADPCM word ID[4:2] 3-bit ADPCM word ID[4:1] 4-bit ADPCM word Input ID[4:0] 5-bit ADPCM word ChCFG[7:0] Configuration word ChCFG[7]:Encoding Law: A-law, µ-law ChCFG[6]:Encoding Even Inversion: Yes, ChCFG[5:4]:Encoding compress rates:00=16, 01=24, 10=32 11=40 ChCFG[3]:Decoding Law: A-law, µ-law ChCFG[2]:Decoding Even Inversion:1= Yes, ChCFG[1:0]:Decoding compress rates:00=16, 01=24, Input 10=32 11=40 Data strobe signal, active Input high ChAddrIn[3:0] Channel address associated Input with input data ChReset Individual channel reset input associated with ChAdInput drIn Input Global reset input Clock input-rising edge Input active I[4:0] ADPCM output word. I[4]: no.1 polarity I[4:3]: 2-bit ADPCM output I[4:2]: 3-bit ADPCM output I[4:1]: 4-bit ADPCM output Output I[4:0]: 5-bit ADPCM output SD[13/7:0] output word. Uniform uses bits, Output SD[13:0] (A-law) bits, SD[12:0] (µ-law). uses bits, SD[7:0] Signal Table Core Signal Pinout (Continued) Signal Output Output Output Signal Direction Description Codec operation indicator. operation free Encoding status indicator Decoding status indicator
Related Information
European Telecommunications Standards Institute
information European digital broadcasting systems standards contact: European Telecommunications Standards Institute 6921 Sophia Antipolis Cedex France Phone: Fax:
Xilinx Programmable Logic
information Xilinx programmable logic development system software, contact your local Xilinx sales office, Xilinx, Inc. 2100 Logic Drive Jose, 95214 Phone: 408-559-7778 Fax: 408-559-7114 URL: www.xilinx.com general Xilinx literature, contact: Phone: E-mail: 800-231-3386 (inside 408-879-5017 (outside literature@xilinx.com
AllianceCORE specific information, contact: Phone: E-mail: Phone: E-mail: URL: 408-879-5381 alliancecore 408-879-5381 alliancecore@xilinx.com tblpart.htm
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Core Specifics Supported Family Device Tested CLBs Clock IOBs IOBs1 Pe

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