Functional Description binary counter used create counters, down

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Functional Description binary counter used create counters, down

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Binary Counter V1.0.2
Functional Description
binary counter used create counters, down counters up/down counters with outputs bits wide. Support provided threshold signals that programmed become active when counter reaches user defined count. upper limit count user programmable, counter's increment value user defined provided external port. Options provided Clock Enable, Asynchronous Set, Clear, Init, Synchronous Set, Clear Init. optional Load capability also provided which load value Load port directly into output register. module optionally generated Relationally
Features
Drop-in module Virtex, Virtex-E Spartan2 families Generates Down Up/Down Counters Supports counts ranging from bits wide Optional load capability
Figure Main Binary Counter Parameterization Screen October 1999
Figure Binary Counter Register Options Parameterization Screen
Binary Counter V1.0.2 Placed Macro (RPM) unplaced logic. When generated logic placed column. Table Core Signal Pinout Signal L[N:0] LOAD IV[N:0] Signal Direction Input Input Input Input Description Load data port Load Control signal Count Increment Value Controls count direction up/down counter. Counts when High, Down when Clock Enable Clock rising edge clock signal Asynchronous forces registered output High state when driven Asynchronous Clear forces outputs state when driven Synchronous forces registered output High state next concurrent clock edge Synchronous Clear forces registered output state next concurrent clock edge Asynchronous Initialize forces registered outputs user defined state when driven Synchronous Initialize forces registered outputs user defined state next concurrent clock edge User programmable threshold signal Registered user programmable threshold signal User programmable threshold signal Registered user programmable threshold signal Output registered module
Pinout
Signal names schematic symbol shown Figure described Table
CORE Generator Parameters
main CORE Generator parameterization screen this module shown Figure parameters follows: Component Name: component name used base name output files generated this module. Names must begin with letter must composed from following characters: "_". Output Width: Enter width counter. valid range default value Operation: Select appropriate radio button operation required. default setting Count Style: module incremented constant value, have count value supplied IV[N:0] port. default setting Count Constant. Count Restrictions: Count Value: Enter count increment value. This text only enabled Count Style Count Constant. When Restrict Count check unchecked Count Value MAX) valid range 2Output Width When Restrict Count check checked valid settings Count Value governed equation: (Count Value Count Value Integer default value Restrict Count: When this check checked counter will only count value specified Count Value box. When unchecked counter will count maximum value that represented using specified output width.The default count restriction. Count Value: Enter count limit value keyword (which corresponds each counter output bits). valid range values 2Output Width 1.This text only enabled when Restrict Count check checked. default value
ASET
Input Input Input
Input
SSET
Input
Input
AINIT
Input
SINIT
Input
THRESH0 Q_THRESH0 THRESH1 Q_THRESH1 Q[N:0]
Note:
Output Output Output Output Output
control inputs Active High. Should Active input required particular control inverter must placed path pin. inverter will absorbed appropriately during mapping.
October 1999
Xilinx, Inc. loaded into output register next active clock edge. This check only available registered module. default LOAD generated. Override Load: This parameter controls whether LOAD input qualified When this checked activation LOAD signal will also enable output register. When this unchecked register needs have active order load port data. default this check checked. Load Sense: LOAD only that parameter control active sense. This because selection Active bypass results significant area savings module. default this parameter Active High that conforms with active sense other control signals. Create RPM: When this checked module will generated with relative location attributes attached. resulting placement module will column with bits slice. default setting create RPM. Register Options parameterization screen this module shown Figure parameters follows: Clock Enable: When this checked module generated with clock enable input. default setting unchecked. Overrides: This parameter controls whether SSET, SCLR, SINIT inputs qualified This parameter only enabled when Clock Enable input been requested. When Overrides Sync Controls selected active level synchronous control inputs will only acted upon when Active. Note that this that dedicated inputs flipflop primitives work, setting Overrides parameter Overrides Sync Controls will force synchronous control functionality implemented using logic Look Tables (LUTs) preceding output register. This results increased resource utilization even when asynchronous controls present. When Sync Controls override selected active level synchronous control inputs will acted upon irrespective state pin. This setting more efficient when asynchronous inputs present because allows dedicated inputs flip-flop primitives used synchronous control functions. less efficient when presence asynchronous inputs force synchronous control functionality implemented using logic LUTs preceding output register. This because signal gated with synchronous control inputs that they generate signal flip-flops, slowing down path resulting slower overall operation module.
ASET SSET L[N:0] LOAD IV[N:0] ACLR SCLR AINIT
THRESH0 Q_THRESH0 THRESH1 Q_THRESH1 Q[N:0] SINIT
X9080 Figure Core Schematic Symbol Output Options: Threshold When this check checked Threshold output(s) (registered, non-registered, both) will generated. default generate Threshold output.Threshold Value: Enter value which THRESH_0 value will activated value keyword (which corresponds each counter output bits). valid range values Count Value.This text only enabled when Threshold check checked. default value MAX. Threshold When this check checked Threshold output(s) (registered, non-registered, both) will generated. default generate Threshold output. Threshold Value: Enter value which THRESH_1 value will activated value keyword (which corresponds each counter output bits). valid range values Count Value.This text only enabled when Threshold check checked. default value MAX. Output Options: Select appropriate radio button types outputs required Threshold signals. default setting Registered. Register Options: This button only enabled when registered output been requested Output Options. Clicking this button brings Register Options parameterization screen (see figure Load: Activating LOAD allows value L[N:0] input port pass through logic
October 1999
Binary Counter V1.0.2 default setting Sync Controls Override that more efficient implementation generated. Asynchronous Settings: asynchronous controls implemented using dedicated inputs flipflop primitives. module generated with following asynchronous control inputs clicking appropriate button: None: asynchronous control inputs. This default setting. Set: ASET input generated. Clear: ACLR input generated. Clear: Both ASET ACLR input pins generated. ACLR priority over ASET when both asserted same time. Init: AINIT input generated which, when asserted, will asynchronously output register value defined Asynchronous Init Value text box. Asynchronous Init Value: This text accepts value whose width must less than equal Output Width. value entered that fewer bits than data width output register padded with zeros. invalid value highlighted text box. value specified this text also functions power reset value output register. default value Synchronous Settings: When asynchronous controls implemented (i.e. Asynchronous Setting None) synchronous controls implemented using dedicated inputs flip-flop primitives. There exceptions this, description Set/Clear Priority Overrides parameters. When asynchronous controls present synchronous control functionality must implemented using logic Look Tables (LUTs) preceding output register. case when non-registered output present, this logic some cases) absorbed into same LUTs used implement gate function. cases where this possible synchronous control logic will require additional output bit. module generated with following synchronous control inputs clicking appropriate button: None: synchronous control inputs. This default setting. Set: SSET input generated. Clear: SCLR input generated. Clear: Both SSET SCLR input pins generated. SCLR/SSET priority defined setting Set/Clear Priority parameter. Init: SINIT input generated which, when asserted, will asynchronously output register value defined Synchronous Init Value text box. Set/Clear Priority: selecting appropriate radio button priority synchronous clear synchronous controlled. This parameter only enabled when both synchronous synchronous clear have been requested. possible override Clear when synchronous control functionality implemented using dedicated inputs flip-flop primitives. This only implemented using logic LUTs preceding output register. default setting Clear Overrides that more efficient implementation generated. Synchronous Init Value: This text accepts value whose width must less than equal Output Width. value entered that fewer bits than data width register padded with zeros. invalid value highlighted text box. This parameter only enabled when Synchronous Settings parameter Init. default value
Parameter Values File
Names file parameters their parameter values identical names values shown GUI, except that underscore characters used instead spaces. text file case insensitive. Table shows file parameters values, summarizes defaults. following example CSET parameters file: CSET component_name abc123 CSET synchronous_settings none CSET count_to_value CSET threshold_0_value CSET count_by_value CSET output_options non_registered CSET ce_overrides ce_overrides_sync_controls CSET count_style count_by_constant CSET load FALSE CSET threshold_1 FALSE CSET sync_init_value CSET threshold_0 FALSE CSET ce_override_for_load FALSE CSET async_init_value CSET operation CSET set_clear_priority clear_overrides_set CSET output_width CSET clock_enable FALSE CSET asynchronous_settings none CSET threshold_1_value CSET load_sense active_high CSET restrict_count FALSE CSET create_rpm TRUE
October 1999
Xilinx, Inc.
Core Resource Utilization
cases described below, this module utilizes Look Table (LUT) output bit. When registered outputs requested flip-flop used output bit. following cases will utilize LUTs output addition output register: down counter with following control signals: Asynchronous Controls Active Bypass Synchronous Synchronous Clear up/down counter with asynchronous controls following: Active Bypass Synchronous Synchronous Clear Synchronous Init up/down counter with active high bypass
When synchronous control functionality cannot implemented using dedicated control inputs flipflop (i.e. when asynchronous controls also requested) Overrides Sync Controls Override additional module required.
Ordering Information
This core downloadable free charge from Xilinx Center (www.xilinx.com/ipcenter), with version 2.1i later versions Xilinx Core Generator System. Core Generator Syste bundled with Alliance Foundation implementation tools. order Xilinx software contact your local Xilinx sales representative. information Xilinx sales office nearest you, please refer http://www.xilinx.com/company/ sales.htm.
October 1999
Binary Counter V1.0.2
Table Default Values File Values Parameter component_name File values ASCII text starting with letter based upon following character set: a.z, Integer range following keywords: down up_down following keywords: count_by_constant count_by_variable value range count_to_value that meets following restriction: (count_to_value count_by_value Integer following keywords: true, false keyword (which corresponds setting output_width value range output_width following keywords: true, false keyword "MAX" value range count_to_value following keywords: true, false keyword "MAX" value range count_to_value following keywords: non_registered, registered both following keywords: true, false following keywords: true, false following keywords: active_high active_low following keywords: true, false following keywords: true, false following keywords: sync_controls_override_ce, ce_overrides_sync_controls following keywords: none, set, clear, set_and_clear, init value whose value does exceed output_width following keywords: none, set, clear, set_and_clear, init value whose value does exceed output_width following keywords: clear_overrides_set set_overrides_clear Default Setting blank
output_width operation count_style count_by_value
count_by_constant
restrict_count count_to_value
false
threshold_0 threshold_0_value threshold_1 threshold_1_value output_options load ce_override_for_load load_sense create_rpm clock_enable ce_overrides
false false non_registered false false active_high true false sync_controls_override_ce
asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority
none none clear_overrides_set
October 1999

Functional Description binary counter used create counters, down

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