Functional Description Binary Decoder module converts binary inpu

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Functional Description Binary Decoder module converts binary inpu

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Binary Decoder V1.0.3
Functional Description
Binary Decoder module converts binary input presented input One-Hot output output buses. activity outputs globally enabled disabled using optional enable control input. Outputs registered non-registered. When registered output selected options also provided Clock Enable, Asynchronous Set, Clear, Init, Synchronous Set, Clear Init. module optionally generated Relationally Placed Macro (RPM) unplaced logic.
Xilinx Inc. 2100 Logic Drive Jose, 95124 Phone: 408-559-7778 Fax: 408-559-7114 URL: www.xilinx.com/ipcenter
Features
Drop-in module Virtex, VirtexTM-E, SpartanTM-II FPGAs Generates One-Hot output from binary coded input Optional registered output with optional clock enable asynchronous synchronous controls Incorporates Xilinx Smart-IP technology maximum performance used with version 2.1i later Xilinx CORE Generator System
Figure Main Binary Decoder Parameterization Screen December 1999
Figure Binary Decoder Register Options Parameterization Screen
Binary Decoder V1.0.3 Table Core Signal Pinout Signal S[N:0] ASET Signal Direction Input Input Input Input Input Description Binary Input Enable control Clock Enable Clock: rising edge clock signal Asynchronous Set: forces registered output High state when driven Asynchronous Clear: forces outputs state when driven Synchronous Set: forces registered output High state next concurrent clock edge Synchronous Clear: forces registered output state next concurrent clock edge Asynchronous Initialize: forces registered outputs user defined state when driven Synchronous Initialize: forces registered outputs user defined state next concurrent clock edge Asynchronous output Synchronous One-Hot output
ASET SSET S[N:0] ACLR SCLR AINIT SINIT
O[M:0] Q[M:0]
Input
x9089
SSET
Input
Figure Core Schematic Symbol
Input
AINIT
Input
SINIT
Input
O[M:0] Q[M:0]
Output Output
Note: control inputs Active High. Should Active input required particular control pin, inverter must placed path pin. inverter will absorbed appropriately during mapping.
Pinout
Signal names schematic symbol shown Figure described Table
CORE Generator Parameters
main CORE Generator parameterization screen this module shown Figure parameters follows: Component Name: component name used base name output files generated this module. Names must begin with letter must composed from following characters: "_".
Number Outputs: Enter number One-Hot outputs required. required number inputs derived from this calculating Log2(Number Outputs), result integer, rounding nearest integer. valid range default value Decoder Enable: This check controls presence module. global Decoder Enable function which, when active, forces outputs inactive. default, this check checked. Output Options: Select appropriate radio button types outputs required. output options settings selected here apply outputs. default setting Registered. Register Options: This button only enabled when registered output been requested Output Options. Clicking this button brings Register Options parameterization screen (see Figure Output Sense: decoder outputs Active High Active depending setting this parameter. default outputs Active High Create RPM: When this checked module generated with relative location attributes attached. resulting placement module column with bits slice. default operation create RPM. Note that when module created possible that more module dimensions exceed those device being targeted. this case mapping errors will occur compilation process will fail. this case module should regenerated with Create checkbox unchecked. This will reduce performance module since placement will longer controlled.
December 1999
Xilinx, Inc. Register Options parameterization screen this module shown Figure parameters follows: Clock Enable: When this checked module generated with clock enable input. default setting unchecked. Overrides: This parameter controls whether SSET, SCLR, SINIT inputs qualified This parameter only enabled when Clock Enable input been requested. When Overrides Sync Controls selected active level synchronous control inputs will only acted upon when also Active. Note that this that dedicated inputs flip-flop primitives work, setting Overrides parameter Overrides Sync Controls will force synchronous control functionality implemented using logic Look Tables (LUTs) preceding output register. This results increased resource utilization. When Sync Controls Override selected active level synchronous control inputs acted upon irrespective state pin. This setting allows dedicated inputs flip-flop primitives used synchronous control functions provided that asynchronous controls requested. both asynchronous synchronous controls requested, synchronous control functionality must implemented using logic LUTs preceding output register. this case, input gated with synchronous control inputs that each synchronous control input input generate signal flip-flops. This results performance degradation module additional gating path. default setting Sync Controls Override that more efficient implementation generated. Asynchronous Settings: asynchronous controls implemented using dedicated inputs flipflop primitives. module generated with following asynchronous control inputs clicking appropriate button: None: asynchronous control inputs. This default setting. Set: ASET control generated. Clear: ACLR control generated. Clear: Both ASET ACLR control pins generated. ACLR priority over ASET when both asserted same time. Init: AINIT control generated which, when asserted, will asynchronously output register value defined Asynchronous Init Value text box. Asynchronous Init Value: This text accepts value whose equivalent width must less than December 1999 equal Number Outputs. value entered that fewer bits than Number Outputs padded with zeros. invalid value highlighted text box. value specified this text also functions power reset value output register. default value Synchronous Settings: When asynchronous controls requested (i.e. Asynchronous Setting None) synchronous controls implemented using dedicated inputs flip-flop primitives. There exceptions this which described sections Set/Clear Priority Overrides parameters. When asynchronous controls present synchronous control functionality must implemented using logic Look Tables (LUTs) preceding output register. With modules where non-registered output required there combinations parameters that allow this logic absorbed into same LUTs used implement function. cases where this absorption possible synchronous control logic will require additional output bit. module generated with following synchronous control inputs clicking appropriate button: None: synchronous control inputs. This default setting. Set: SSET control generated. Clear: SCLR control generated. Clear: Both SSET SCLR control pins generated. SCLR/SSET priority defined setting Set/Clear Priority parameter. Init: SINIT control generated which, when asserted, will synchronously output register value defined Synchronous Init Value text box. Set/Clear Priority: selecting appropriate radio button relative priority SCLR SSET controlled. This parameter only enabled when Clear selected Synchronous Settings. setting Clear Overrides corresponds native operation flip-flop primitive. This setting will result more efficient implementation when asynchronous controls requested. setting Overrides Clear only implemented using logic LUTs preceding output register. default setting Clear Overrides that dedicated inputs flip-flops used available. Synchronous Init Value: This text accepts value whose equivalent width must less than equal Number Outputs. value entered that fewer bits than Number Outputs padded with zeros. invalid value highlighted
Binary Decoder V1.0.3 text box. This parameter only enabled when Synchronous Settings parameter Init. default value
Core Resource Utilization
resource utilization figures output this core shown Table When registered outputs required single flip-flop used each output. figures should multiplied number outputs full resource count module. When synchronous control functionality cannot implemented using dedicated control inputs flipflop (i.e. when asynchronous controls also requested) Overrides Sync Controls Override additional module required.
Parameter Values File
Names file parameters their parameter values identical names values shown GUI, except that underscore characters used instead spaces. text file case insensitive. Table shows file parameters values, summarizes defaults. following example CSET parameters file: CSET component_name abc123 CSET number_of_outputs CSET decoder_enable FALSE CSET output_options registered CSET output_sense active_high CSET clock_enable FALSE CSET ce_overrides sync_controls_override_ce CSET asynchronous_settings none CSET async_init_value CSET synchronous_settings none CSET sync_init_value CSET set_clear_priority clear_overrides_set CSET create_rpm TRUE
Ordering Information
This core downloadable free charge from Xilinx Center (www.xilinx.com/ipcenter), with version 2.1i later Xilinx CORE Generator System. CORE Generator System bundled with Alliance Foundation implementation tools. order Xilinx software contact your local Xilinx sales representative. information Xilinx sales office nearest you, please refer http://www.xilinx.com/company/ sales.htm.
December 1999
Xilinx, Inc. Table File Values Default Values Parameter component_name File Values ASCII text starting with letter based upon following character set: a.z, Integer range following keywords: true, false following keywords: non_registered, registered, both following keywords: active_high, active_low following keywords: true, false following keywords: true, false following keywords: sync_controls_override_ce, ce_overrides_sync_controls following keywords: none, set, clear, set_and_clear, init value whose value does exceed number_of_outputs following keywords: none, set, clear, set_and_clear, init value whose value does exceed number_of_outputs following keywords: clear_overrides_set, set_overrides_clear Default Setting blank
number_of_outputs decoder_enable output_options output_sense create_rpm clock_enable ce_overrides
false registered active_high true false sync_controls_override_ce
asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority
none none clear_overrides_set
December 1999
Table Count Number Inputs Different Output Options Output Options Registered Registered Non-Registered sync. Sync. Control implemented sync. Non-registered controls logic controls Sync. Control implemented implemented implemented logic control control logic logic input inputs
Number Inputs

Functional Description Binary Decoder module converts binary inpu

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