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FPGA Product Family Spartan Virtex XC4000X CPLD Product Family XC9500
Invoke tools
Start Programs Model Tech UNIX Separate programs vlib, vmap, vcom, vlog, vsim ModelSim
Create/map working library
File Change Directory {path design directory} Library Create Library library logical mapping {work} {relative path work} Command {path design directory} vlib work vmap work ./work
About Model Technology
VHDL, Verilog Cosimulation VHDL Verilog Full Language Support: VHDL IEEE-STD-1076 -'87, -'93 Standard Logic IEEE-STD-1164 VITAL IEEE-STD-1076.4 (VITAL) Verilog IEEE-STD-1364
technology libraries
Library Create Library existing library: {Unisim xc4000xl*or Simprim} *Verilog Unisim: specific technology name {path library} Command vmap {library name} {path compiled library}
Recommended Settings
recommended settings, http://www.xilinx.com Solutions"
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
Compile input files
Compile Library: {work} Filename: {name file} Compile Done Command vcom -work work {file} vlog -work work {file}
Simulate
Model Technology Contacts Technical Support
World Wide Web: http://www.model.com Telephone E-Mail 1-503-641-1340 support@model.com
0010419
VSIM Design Simulator Resolution: Library: work Simulate: {select testbench} File Load Design Library: {Select library name} Simulate: {Select testbench} SDF: {Select dile} Load View Signals {Select signals} View wave Selected signals vsim ns-lib* work -sdftyp /UUT*= Command {SDF file} {testbench} Verilog *Substitute top-level design instance
name within testbench
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