Series Software Synopsys Design Compiler Information Guide O

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Series Software Synopsys Design Compiler Information Guide O

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ALLIANCE
Series Software
Synopsys Design Compiler Information
Guide Overview
XC4000(E, XC5000 XC9000 XC9000XL
Device Architecture Support
FPGA XC3000(A, XC4000(EX, XLA) Virtex Spartan Spartan-XL CPLD XC9500 XC9500XL
Setup FPGA Compiler .synopsys_dc.setup file
template synopsys_dc.setup_dc examples $XILINX/synopsys/examples. correct information your target speed grade. Modify paths your setup.
Recommended Settings
Please refer your A1.5 software installation example: .synopsys_dc.setup .synopsys_vss.setup runscript files $XILINX/synopsys/examples
Create compile script read your input files
example compile scripts $XILINX/synopsys/examples guide. Create compile script read files design.
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
Synthesize design running compile script with dc_shell design_analyzer
Compile design running: dc_shell runscript |tee run.log design analyzer Either step will produce .sedif file
Synopsys Contacts Technical Support
World Wide Web: http://www.synopsys.com United States 1-800-245-8005 support_center@synopsys.com
Printed U.S.A. X8452
Place Route .sedif file using A1.5 software
Place route synthesized design UNIX A1.5 commands Design Manager GUI.
0010335

Series Software Synopsys Design Compiler Information Guide O

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