Series Software Synopsys FPGA Express Information Guide Over

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Series Software Synopsys FPGA Express Information Guide Over

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Series Software
Synopsys FPGA Express Information
Guide Overview
XC4000(E, XC5000 XC9000 XC9000XL
Device Architecture Support
FPGA XC3000(A, XC4000(EX, XLA) Virtex Spartan Spartan-XL CPLD XC9500 XC9500XL
X8454
Create project
menu define project. files processed FPGA Express must done through project.
files project analyze files
Recommended Settings
Please refer your A1.5 software installation examples: .synopsys_dc.setup .synopsys_vss.setup runscript files $XILINX/synopsys/examples
After creating project, design files added project. After adding design files, FPGA Express will automatically analyze files.
Implement design
Select top-level module/entity Design Sources window implement button will highlighted. Click implement button specify target die, speed grade package. Strategies synthesis specified during implementation.
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
Enter constraints
Chips window, select implementation. Right-click selected implementation select Edit Constraints. window will appear where various constraints edited. After entering constraints, save constraints closing constraints window.
Optimize design
Click optimize button located next implement button synthesize design select menu Optimize Chip
Synopsys Contacts Technical Support
World Wide Web: http://www.synopsys.com United States 1-800-245-8005 support_center@synopsys.com
Printed U.S.A.
Place&Route file with A1.5
After optimization, write file clicking Export Netlist button next implement button. Place Route file using A1.5 implementation tools with Design Manager shell based commands.
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Series Software Synopsys FPGA Express Information Guide Over

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