Series Software Model Technology (MTI) Information Guide Ove
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Series Software
Model Technology (MTI) Information
Guide Overview
XC4000(E, XC5000 XC9000 XC9000XL
Device Architecture Support
FPGA XC3000(A, XC4000(EX, XLA) Virtex Spartan Spartan-XL CPLD XC9500 XC9500XL
UNIX
Invoke tools
Model ModelSim Separate programs vlib, vmap, vcom, vlog, vsim
Create/map working library
{path design directory} work Library: work Directory: ./work {path design directory} Command vlib work vmap work ./work
About Model Technology
ModelSim unification Mentor Graphics QuickHDL Model Technology's V-System supports following: UNIX v5.1+, v4.7+ VHDL, Verilog plus Cosimulation VHDL Verilog Full Language Support: VHDL IEEE-STD-1076 -'87, -'93 Standard Logic IEEE-STD-1164 Verilog IEEE-STD-1364 VITAL IEEE-STD-1076.4 (VITAL)
technology libraries
Library: Unisim xc4000xl*or Simprim *Verilog Unisim: specific technology name Directory: {path compiled library} vmap {library name} Command {path compiled library}
Recommended Settings
recommended settings, http://www.xilinx.com "Software Solutions"
Compile input files
{select Compile* (VHDL) *Buttom order, target library work {select Compile (Verilog) Command vcom -work work {file} vlog -work work {file}
Xilinx Contacts Technical Support
World Wide Web: http://www.xilinx.com North America 1-800-255-7778 hotline@xilinx.com United Kingdom 1932-820821 ukhelp@xilinx.com France 1-3463-0100 frhelp@xilinx.com Japan 3-3297-9163 jhotline@xilinx.com
Simulate
Model Technology Contacts Technical Support
World Wide Web: http://www.model.com Telephone E-Mail 1-503-641-1340 support@model.com
Printed U.S.A.
Design Simulator Resolution: Library: work Simulate: {select testbench} SDF, File: {SDF file}, Signals Design Signals Design {length testbench Command vsim ns-lib* work -sdftyp /UUT*= {SDF file} {testbench} Verilog *Substitute top-level design instance
name within testbench
{length testbench
X8451 0010336
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