Quality Assurance Reliability February 2000 (v3.0) Quality A

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Quality Assurance Reliability February 2000 (v3.0) Quality A

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Quality Assurance Reliability
February 2000 (v3.0)
Quality Assurance Program
aspects Quality Assurance Program Xilinx have been designed eliminate root cause defects prevention, rather than remove defects through inspection. quality management system place which fully compliant with requirements ISO9001. Xilinx found full compliance 9001:1994 independent auditor registered November 1997. that time Xilinx registered "the design, manufacturing testing programmable logic devices". Also November 1997, DSCC found Xilinx full compliance with requirements 38535 granted Xilinx full status supplier. Those aspects compliance which place Xilinx include following seventeen points: Management Review: comprehensive system management attention direction aspects company performance which directly affect customers. These include (among others) Xilinx performance areas Quality, Reliability On-Time Delivery. Management assures that this quality policy understood, implemented maintained levels organization. Quality Systems: place ensure that Xilinx products conform customer specifications. These systems facilitate, measure continuously improve Xilinx performance those areas which affect customer satisfaction. Xilinx remains committed achieving 100% customer satisfaction. Contract Review: conducted ensure that each contract adequately defines documents customer requirements, that differences between customer Xilinx standard specifications mutually satisfactorily resolved, that Xilinx capability meet contract requirements. Document Control: procedures established maintained control documents data that relate performance Xilinx business processing requirements. organizations need access such documentation during performance their functions assured availability latest, controlled versions that documentation. Purchasing: procedures place ensure that purchased products conform specified requirements. Xilinx "fabless" manufacturing company, special attention paid subcontract partners. They required demonstrate type control capabilities that customers require
Xilinx subcontract partners certified. Product Identification Traceability: maintained throughout manufacturing process. Traceability back starting materials available through unique product identification techniques markings. Process Control: assured identifying planning those processes which directly affect quality products, whether those processes performed directly Xilinx, subcontract partners. Inspection Test: performed ensure that incoming product used processed until been verified conforming required specifications. This inspection done jointly Xilinx subcontract partners. Inspection, Measuring Test Equipment: calibrated conformance with requirements ANSI/NCSL Z540-I-1994 (and former 45662) and/or other international standards. Equipment maintained such manner ensure that measurement uncertainty known consistent with specification accuracy requirements. Inspection Test Status: product uniquely identified throughout manufacturing process both Xilinx subcontract partners. Records kept identify authority responsible release conforming production. Control Non-Conforming Product: assured through disposition procedures which defined such manner prevent shipping non-conforming products. responsibility authority disposition such products well defined. Corrective Action: processes documented implemented prevent recurrence nonconforming product. These processes implementing Xilinx strategy eliminating root causes nonconformity, rather that apply inspection remove nonconformity. Handling, Storage, Packing Delivery: procedures defined implemented prevent damage deterioration product once manufacturing process complete. Quality Records: procedures established maintained identification, collection, indexing, filing, storage, maintenance disposition quality records.
February 2000 (v3.0)
Quality Assurance Reliability
Internal Quality Audits: carried verify whether quality activities comply with planned arrangements determine effectiveness quality system. These audits regularly supplemented quality audits performed customers, independent auditors. Training: procedures have been established maintained identify training needs personnel affecting quality during production Xilinx products. Personnel performing such activities qualified based upon appropriate education, training and/or experience. Statistical Techniques: place Xilinx subcontract partners verifying acceptability process capability product characteristics.
Device Reliability
Device reliability often expressed measurement called Failures Time (FITs). this measure equals failure billion (109) device operating hours. failure rate FITS must include operating temperature meaningful. Hence failure rates often expressed FITS 55°C some other temperature excess application). Since billion hours well excess 100,000 years, rate modern only measured accelerating failure rate testing higher junction temperature (usually 125°C 145°C). Extensive testing Xilinx devices (performed actual production devices taken directly from finished goods) been done continuously since 1989 reported quarterly. Quarterly reports reliability Xilinx products available through your Xilinx sales representative WebLINX site During last years, over 20,000 devices have accumulated total over 50,000,000 hours both static dynamic operation 125°C (equivalent) yield rates shown Figure Figure
These requirements place Xilinx subcontract partners ensure ability achieve customer satisfaction through on-time delivery quality products that meet customer requirements reliable.
Failure Rate
XC1700E/L (0.6 XC3000 (0.65, 0.7, XC4000 (0.8, 0.65, XC4000E (0.65, 0.6, 0.5, 0.35 XC4000EX (0.5 XC5000 (0.6, XC9500 (0.6
Dec-95 Dec-96 Mar-97 Jun-97 Sep-97 Dec-97 Mar-98 Jun-98 Sep-98 Dec-98 Mar-99 Jun-99
Sep-99
Time
Figure Failure Rate FITS 55°C Mature Products-XSJ
February 2000 (v3.0)
Quality Assurance Reliability
XC4000XL (0.35
XCSXXX (0.35 XC4000XLA (0.25 XC4000XV(0.25 XCVXXX (0.25 XC9500XL 0.35
Failure Rate
Dec-95 Jun-97 Sep-97 Dec-97 Mar-98 Jun-98 Sep-98 Dec-98 Mar-99 Jun-99 Sep-99
Time
Figure Failure Rate FITS 55°C Products-XSJ
Testing Facilities
Xilinx facilitated laboratory perform High Temperature Life Testing, Thermal Shock, Temperature Cycling, Biased Moisture Life Test, Unbiased Pressure Pot, Solderability Hermeticity site, well having complete Failure Analysis capabilities house. Table Table show typical qualification requirements and/or
changed process flows. Table list current failure analyses capabilities. These laboratories dedicated exclusively increasing customer satisfaction through continuous improvements processes technologies.
February 2000 (v3.0)
Quality Assurance Reliability
Table Plastic Package/Product Qualification Requirements
Assy Techniques (Mat'l/Process/Method Test Test Description (note Acc# S.Size (note Assy Plant Lead Frame Attach Type Type Type (note3) (note4) Design (note5) Coat Wire Bond Mold Lead Finish Device Mask (note6) Proc Full Qual
Phy. Dimension Resist. Solvents Solderability Test (note Solder Heat Test (Optn'l) Auto Clave (SPP)(Optn'l) 0/76 Ball Shear/Bond Pull (note X-Ray (note S.A.T/Dye Test (note Adhesion L/Finish (Optn'l)
0/15 0/76 0/10 0/25 0/76 0/22 0/76 0/77 0/76 0/76 0/30 0/30 0/11 0/22 0/22 E.Good E.Reject Total
External Visual (note Internal Visual (note Shear (note Flammability Test (note C1-A High Temp Life Test C1-B Temp Life Test (note C2-A:HAST (0/22) C2-B: 85/85 (HBM) High Temp Storage (Optn'l) Lead Integrity Thermal Shock (Optn'l) Temp Cycle Electrical Test Data Electrical Characterization T.D.D.B (note Latch-up Electromigration (note Photosensitivity (Optn'l) Data Retention Bake EPLD Input/Output Capacitance Power Cycling (Optn'l) required
Notes: Test method stress conditions available upon request.2) QUAL which does meet standard requirements, approval from Product Engineering Product required. package which been qualified qualified assembly facility. package where same body size with different lead pitch been qualified. leadframe design whereby paddle size larger than existing leadframe paddle size used same qualified package. mask from same device family, only high temp life test, ESD, Latch Capacitance required. In-process monitor data used satisfy this requirement. Electrical rejects used test sample. This non-destructive test, sample re-used.
February 2000 (v3.0)
Quality Assurance Reliability
Table Hermetic Package/Product Qualification Requirements (Commercial)
Assy Techniques (Mat'l/Process/Method Test Test Description (note Acc# S.Size (note Assy Plant Lead Frame Attach Family Qual (note3) Family (note4) Coat Wire Type Lead Bond Seal Finish Cavity Device Size (note6) (note6) Proc Full Qual
Solder Heat Test (Optn'l) Resist. Solvents (note Solderability Test (note Shear/Stud Pull (note Bond Pull (note External Visual (note Internal Visual (note
0/15 0/25 0/76 0/22 0/77 0/15 0/32 0/32 0/15 0/45 0/30 0/30 0/11 0/22 E.Good E.Reject Total
C1-A High Temp Life Test C1-B Temp Life Test (note High Temp Storage (Optn'l) (HBM) Phy. Dimension Lead Integrity Thermal Shock Temp Cycl Moisture Resistance Mech. Shock Vibration Constant Acceleration Salt Atmosphere Internal Vapor Content (note Adhesion L/Finish (Optn'l) Torque Temp Cycle Electrical Test Data Electrical Characterization T.D.D.B (note Latch-up Electromigration (note Photosensitivity (Optn'l) Data Retention Bake Input/Output Capacitance required
Notes: Test method stress conditions available upon request. QUAL which does meet standard requirements, approval from Product Engineering Product required. Package Family package type with same package, material, Package construction techniques, terminal pitch, lead shape, spacing with identical package assembly tech. Package Type package with unique case outline, configuration, material, piece parts assembly process. Application piece parts leadframe where cavity size larger than largest cavity size same package. mask from same device family, only high temp life test, ESP, Latch Capacitance required. In-process monitor data used satisfy this requirement, Qual data, data from Assy. traveler maybe used. Electrical rejects used test samples
February 2000 (v3.0)
Quality Assurance Reliability
Table Failure Analysis Equipment List
Item Equipment Scanning Electron Microscope Gold Sputter (SEM Sample Prep) Energy Dispersive X-Ray F.I.B. Focused Beam Workstation Vendor JEOL ANATECH OXFORD INST. F.E.I. Model Number JMS-6401F Hummer VIII LINK ISIS-L200C FIB-600 FXS-100.10 Micro-Scan 4HF-200 MBS-200 XRF-5500 4330 Visionary 2000 Item Equipment Vendor KELLER Robotic Systems Robotic Systems Services Model Number ST2D RPS-202 004-012-0
Die-Shear Tester Steam Aging System Solder Wave/Pot Lead Fatigue Tester Conventional Oven (C.D.A.) Drill-bit open MQUADS
Decapping vise
Real-Time X-Ray Imaging Sys- FEIN FOCUS Scanning Acoustic Microscopy Ball Shear Strength Tester Lead Finish/Composition Measurement System Liquid Crystal Spot Detection System/Kit, with temp. Multilayer Inspection (EMMI) Sonix KELLER Twin City, Inc. Technology Associates Hypervision Services Scientific Instrument Company Scientific Instrument Company Associates Computer Modules
Color Printer Stud Pull Tester Work Benches Cabinets Facilities (Lab Area
Equipment Installation Costs)
Tektronic
Tektronic Phaser IISD 003-010-0
Emission Microscope Curve Tracer Metallurgical High Power
Microscope
quote (various) quote (various)
Tool Maker Microscope Flowhood Rinse Station Precision X-Sectioning Equipment
Stereozoom Power
Microscope video camera monitor
Micro-Etcher System Viseco Camera Interface with
High Power Microscope
Plasma Etcher E-Beam IDS-300
March Instruments
CS-1701
Hermeticity Test System
Fine Leak Gross Leak
Services -Trio-tech Veeco MS-17
Description Tests
Qualification
High Temperature Life: This test performed evaluate long-term reliability life characteristics die. defined Military Standard from which derived "Die-Related Test" contained Group Quality Conformance Tests. Because acceleration factor induced higher temperatures, (typically 125°C and/or 145°C) data representing large number equivalent hours normal temperature 25°C accumulated reasonable period time. Biased Moisture Life: This test performed evaluate reliability under conditions long-term exposure severe, high-moisture environments that could cause corrosion. Although clearly stresses package well, this test typically grouped under
die-related tests. device operated maximum rated voltage (Vccmax) exposed temperature 85°C relative humidity throughout test.
Package Integrity Assembly Qualification
Unbiased Pressure Pot: This test performed temperature 121°C pressure saturated steam evaluate ability plastic encapsulating material resist water vapor. Moisture penetrating package could induce corrosion bonding wires nonglassivated metal areas (bonding pads only FPGA devices). Under extreme conditions, moisture could cause drive-in corrosion under glassivation. Although difficult correlate this test actual field conditions, provides well-established method relative comparison plas-
February 2000 (v3.0)
Quality Assurance Reliability
packaging materials assembly molding techniques. Thermal Shock: This test performed evaluate resistance package cracking resistance bonding wires lead frame separation damage. involves nearly instantaneous change temperature from -65°C +150°C (known condition "C"). Temperature Cycling: This test performed evaluate long-term resistance package damage from alternating exposure temperature extremes. range temperatures -65°C +150°C (again condition "C"). transition time longer than that Thermal Shock test test conducted many more cycles. Salt Atmosphere: This test originally designed Navy evaluate resistance military-grade ship-board electronics corrosion from water. used more generally non-hermetic industrial commercial products test corrosion resistance package marking finish. Resistance Solvents: This test performed evaluate integrity package marking during exposure variety solvents. This especially important test, since increasing number board-level assemblies subjected severe conditions automated cleaning before system assembly. This test performed according methods specified MIL-STD-883. Solderability: This test performed evaluate solderability leads under conditions soldering temperature following exposure aging effects water vapor. Lead Fatigue: This test performed evaluate resistance completed assembly vibrations during storage, shipping, operation.
Data Integrity
Memory Cell Design FPGA Device:
important aspect SRAM-based FPGA device reliability robustness static memory cells used store configuration program. basic cell single-ended 5-transistor memory element (Figure eliminating sixth transistor, which would have been used pass transistor complementary line, higher circuit density achieved. During normal operation, outputs these cells fixed, since they determine user configuration. Write readback times, which have relation device performance during normal operation, will slower without extra transistor. return, user receives more functionality unit area. This explains basic cell, FPGA user assured high data integrity noisy environment? Consider three different situations: normal operation, Write operation Read operation
February 2000 (v3.0)
Quality Assurance Reliability
Configuration Data Shift Regiater
Read
lock
R/RD
Clock
Address QN-1
arge Memory Cell Circuit Memory Cell Word Line Driver Configuration Address Shift Regiater
Memory Cell Memory Cell Memory Cell Word Line Driver
X3124
Figure Configuration Memory Cell normal operation, data basic memory element changed. Since circularly linked inverters that hold data physically adjacent, supply transients result only small relative differences voltages. Each inverter truly complementary pair transistors. Therefore, whether output High Low, low-impedance path exists supply rail, resulting extremely high noise immunity. Power supply ground transients several volts have effect stored data. transistor driving line been carefully designed that whenever data written opposite data stored, easily override output feedback inverter. reliability Write operation guaranteed within tolerances manufacturing process. Read mode, line, which significant amount parasitic capacitance, precharged logic one. pass transistor then enabled driving word line High. stored value zero, line then discharged ground. Reliable reading memory cell achieved reducing word line High level during reading level that insures that cell will disturbed.
Electrostatic Discharge:
Electrostatic-discharge (ESD) protection each provided circuitry that uses distributed transistors, diodes and/or other structures, represented circles Figure older devices, these protection circuits conventional diffused structures. newer designs, Xilinx utilizes proprietary device structures which exhibit substantially enhanced protection.
February 2000 (v3.0)
Quality Assurance Reliability
Geometries doping levels chosen provide protection pads both positive negative voltages.
ROUT Output
Latchup
Latchup condition which parasitic bipolar transistors form positive feedback loop (Figure which quickly reaches current levels that permanently damage device. Xilinx uses techniques based doping levels circuit placement avoid this phenomenon. beta each parasitic transistor minimized increasing base width. This achieved with large physical spacings. butting contacts effectively short regions both wells, which makes each parasitic very close zero. This also makes parasitic transistors very hard forward bias. Finally, each well surrounded dummy collector, which forces each parasitic almost zero creates structure which base width each parasitic large, thus making latchup extremely difficult induce.
Ground
Input
Ground Symbol electrostatic discharge protection circuit
X3132
Figure Input/Output Protection Circuitry Table Performance Xilinx Components Device Family XC17xxE XCS17xx XC31xx/A XC3xxx/A XC4xxx/A XC4xxxE XC4xxxEX XC4xxxXL XC4xxxXLA XCxxxxXV XCVxxx XCSxx XCSxxXL XC5xxx XC95xxx XC95xxXL Model >3,000v >3,000v >1,750v >4,000v >1,000v >3,000v >3,000v >2,000v >2,000v >1500v >1400v >6,000v >3,000v >3,000v >2,000v >2,000v EIAJ Model >325v >325v >700v >325v >800v Model >1,000v >1,000v >1,000v >2,000v >2,000v >2,000v >2,000v >1,000v >500v
X1825
>1,000v >2,000v >2,000v >1,000v
Figure Model elevated temperatures, will cause latchup. room temperature, FPGA withstand more than without latchup; EPLD device withstand more than without latchup. However, avoid metal-migration problems, continuous currents excess recommended.
Whenever voltage approaches dangerous level, current flows through protective structures from power supply rail (VCC ground). addition, capacitance these structures integrate pulse provide sufficient time protection networks clamp input, avoiding damage circuit being protected.
High Temperature Performance
Though Xilinx guarantees parts perform only within specifications data sheet, high temperature life testing been done 145°C with excellent results.
February 2000 (v3.0)
Quality Assurance Reliability
Revision Control
Version Date 12/14/98 02/01/00 Revision Revised certification dates, updated Figure Rewritten year 2000 updates.
February 2000 (v3.0)

Quality Assurance Reliability February 2000 (v3.0) Quality A

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