XC95288XL High Performance CPLD June 1999 (Version 1.2) Prel
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XC95288XL High Performance CPLD
June 1999 (Version 1.2)
Preliminary Product Specification
Features
pin-to-pin logic delays System frequency macrocells with 6,400 usable gates Available small footprint packages 144-pin TQFP (117 user pins) 208-pin PQFP (168 user pins) 256-pin (192 user pins) 280-pin (192 user pins) Optimized high-performance systems power operation tolerant pins accept signals output capability Advanced 0.35 micron feature size CMOS FastFLASHtechnology Advanced system features In-system programmable Superior pin-locking routability with FastCONNECT IIswitch matrix Extra wide 54-input Function Blocks product-terms macrocell with individual product-term allocation Local clock inversion with global product-term clocks Individual output enable output Input hysteresis user boundary-scan inputs Bus-hold ciruitry user inputs Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control individual outputs Enhanced data security features Excellent quality reliability Endurance exceeding 10,000 program/erase cycles year data retention protection exceeding 2,000 Pin-compatible with V-core XC95288 device 208-pin HQFP package
Power Estimation
Power dissipation CPLDs vary substantially depending system frequency, design application output loading. help reduce power dissipation, each macrocell XC9500XL device configured low-power mode (from default high-performance mode). addition, unused product-terms macrocells automatically deactivated software further conserve power. general estimate ICC, following equation used:
(mA) MCHP(0.5) MCLP(0.3) MC(0.0045 mA/MHz)
Where: MCHP Macrocells high-performance (default) mode MCLP Macrocells low-power mode Total number macrocells used Clock frequency (MHz) This calculation based typical operating conditions using pattern 16-bit up/down counters each Function Block with output loading. actual value varies with design application should verified during normal system operation. Figure shows above estimation graphical form.
Typical (mA)
Description
XC95288XL CPLD targeted high-performance, low-voltage applications leading-edge communications computing systems. comprised sixteen 54V18 Function Blocks, providing 6,400 usable gates with propagation delays Figure architecture overview.
Clock Frequency (MHz)
x58288xl
Figure Typical Frequency XC95288XL
June 1999 (Version 1.2)
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XC95288XL High Performance CPLD
JTAG Port JTAG Controller
In-System Programming Controller
FastCONNECT Switch Matrix
Function Block Macrocells
Function Block Macrocells
Blocks I/O/GCK I/O/GSR I/O/GTS
Function Block Macrocells
Function Block Macrocells
Function Block Macrocells
X5922E
Figure XC95288XL Architecture
Function Block outputs (indicated bold line) drive Blocks directly.
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XC95288XL High Performance CPLD
Absolute Maximum Ratings
Symbol TSTG TSOL Description Supply voltage relative Input voltage relative (Note Voltage applied 3-state output (Note Storage temperature (ambient) Maximum soldering temperature (10s 1/16 Junction temperature Value -0.5 -0.5 -0.5 +150 +260 +150 Units
Note Maximum undershoot below must limited either whichever easier achieve. During transitions, device pins undershoot -2.0 overshoot +7.0 provided this over- undershoot lasts less than with forcing current being limited Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
Recommended Operation Conditions
Symbol VCCINT VCCIO Parameter Supply voltage internal logic Commercial 70oC input buffers Industrial -40oC +85oC Supply voltage output drivers operation Supply voltage output drivers operation Low-level input voltage High-level input voltage Output voltage 0.80 VCCIO Units
Quality Reliability Characteristics
Symbol VESD Parameter Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) 10,000 2,000 Units Years Cycles Volts
Characteristic Over Recommended Operating Conditions
Symbol Parameter Output high voltage outputs Output high voltage outputs Output voltage outputs Output voltage outputs Input leakage current high-Z leakage current capacitance Operating Supply Current (low power mode, active) Test Conditions -4.0 -500 GND, load VCCIO Units
10.0 10.0 10.0 85(Typ)
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XC95288XL High Performance CPLD
Characteristics
Symbol fSYSTEM tPSU tPCO tPOE tPOD tPAO tWLH tPLH Parameter output valid setup time before hold time after output valid Multiple internal operating frequency setup time before p-term clock input hold time after p-term clock input P-term clock output valid output valid output disable Product term output enabled Product term output disabled output valid P-term output valid pulse width (High Low) P-term clock pulse width (High Low) XC95288XL-6 Max1 Min1 151.5 10.8 11.6 Advance XC95288XL-7 XC95288XL-10 Min1 Max1 10.0 125.0 100.0 10.2 11.0 11.0 12.0 14.5 12.6 15.3 Preliminary Units
Note Please contact Xilinx up-to-date information advance specifications.
VTEST Device Output
Output Type
VCCIO
VTEST
X5906A
Figure Load Circuit
June 1999 (Version 1.2)
XC95288XL High Performance CPLD
Internal Timing Parameters
Symbol Parameter XC95288XL-6 Max1 Min1 10.0 Preliminary XC95288XL-7 Min1 Max1 XC95288XL-10 Min1 Max1 Units
Buffer Delays Input buffer delay tGCK buffer delay buffer delay tGSR tGTS buffer delay tOUT Output buffer delay Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register Combinatorial Delays tPDI Combinatorial logic propagation delay tSUI Register setup time Register hold time tECSU Register clock enable setup time tECHO Register clock enable hold time tCOI Register clock output valid time tAOI Register async. output delay tRAI Register async. recover before clock tLOGI Internal logic delay tLOGILP Internal power logic delay Feedback Delays FastCONNECT IIfeedback delay Time Adders tPTA Incremental product term allocator delay tSLEW Slew-rate limited delay
Advance Note Please contact Xilinx up-to-date information advance specifications.
June 1999 (Version 1.2)
XC95288XL High Performance CPLD
XC95288XL Pins
BScan Function Macrocell TQ144 PQ208 BG256 CS280 Order Block -861 BScan Function Macrocell TQ144 PQ208 BG256 CS280 Order Block -T1* -C2* -C1* -D3* -753
Global control
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XC95288XL High Performance CPLD
XC95288XL Pins (continued)
Function Block Macrocell TQ144 PQ208 BG256 CS280 143* 206* -W2* -BScan Order Function Block Macrocell TQ144 PQ208 BG256 CS280 -B10 -D10 -BScan Order
Global control
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XC95288XL High Performance CPLD
XC95288XL Pins (continued)
Function Block Macrocell TQ144 PQ208 BG256 CS280 -W10 -U10 -W12 -T12 -C14 -A14 -B13 -B11 -A10 -BScan Order Function Block Macrocell TQ144 PQ208 BG256 CS280 -W13 -U13 -W14 -U16 -W18 -B19 -B17 -A17 -C15 -D15 -BScan Order
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XC95288XL Pins (Continued)
Function Macrocell Block TQ144 PQ208 BG256 CS280 -V17 -V19 -T16 -R16 -P17 -G19 -F19 -F17 -E16 -D17 -BScan Order BScan Function Macrocell TQ144 PQ208 BG256 CS280 Order Block -P16 -N17 -N19 -L19 -L17 -L16 -K17 -J19 -H18 -H16 -105
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XC95288XL High Performance CPLD
XC95288XL Global, JTAG Power Pins
Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR VCCINT 3.3V TQ144 PQ208 124, 153, BG256 CS280 V10, U13, W18, T20, M19, F20, E17, B17, B14, A10, 109, D11, D15, D17, 105, 132, 157, 172, F17, L17, 181, R17, U10, U15, W10, 108, 114, 104,1 129, Y10, Y14, V15, U18, 123, 130, 141, 156, 163, R19, K20, G18, B16, 177, 190, D13, A11, J10, J11, J12, K10, K11, K12, L10, L11, L12, M10, M11, U12, V16, R17, M18, G18, D19, C18, A15, A11, T10, V14, V18, P18, K19, G17, C19, D14, D12, D11, R10, R11, R12, R13,R14, R15, P15, N15, M15, L15, K15, J15, H15, G15, F15, E15, E14, E13, E12, E11, E10, A19, A20, B19, W19, U17, B20, C19, A19, C17, W20,
VCCIO 2.5V/3.3
Connects
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XC95288XL High Performance CPLD
Ordering Information
Example:
Device Type
XC95288XL
Temperature Range Number Pins
Speed Grade
Package Type
Speed Options pin-to-pin delay pin-to-pin delay pin-to-pin delay
Packaging Options TQ144 144-Pin Thin Quad Flat Pack (TQFP) PQ208 208-Pin Plastic Quad Flat Pack (PQFP) BG256 256-Pin Plastic Ball Grid Array (BGA) CS280 280-Pin Chip Scale Package (CSP) Temperature Options Commercial +70oC Industrial -40oC +85oC
Component Availability
Pins Type Code XC95288XL Plastic TQFP TQ144 Plastic PQFP PQ208 Plastic BG256 Plastic CS280
Commercial +70oC) Industrial -40oC +85oC) Parenthesis indicate future product plans. Please contact Xilinx up-to-date availability information.
Revision Table
Date 09/28/98 12/10/98 2/5/99 6/7/99 Revision Original creation data sheet. Revision tables. V1.1 Updated pinouts reflect BG256 (replaces BG352). V1.2 speed CS280 package
June 1999 (Version 1.2)
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