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PSD813F1 / 80C31 Design Tutorial

Application Note 057

PSD813F1 / 80C31 Design Tutorial
Application Note 057
By Dan Harris and Mark Rootz
February, 1999
47280 Kato Road, Fremont, CA 94538 Telephone: (510)-656-5400 (800) TEAM-WSI (832-6974) Web Site: http://waferscale.com E-mail: info@wsipsd.com
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March 20, 1999-REV 1.2
PSD813F1 / 80C31 Design Tutorial
Application Note 057
By Dan Harris and Mark Rootz
Contents
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1 Introduction
This tutorial takes you step-by-step through the development cycle of a PSD813F based design, from design entry, to programming the device. The first part of this tutorial shows how a PSD813F1 can be used in conjunction with a handful of other ICs to implement an automatic gain control (AGC) design. The tutorial also shows how this design would be implemented using a discrete part solution, and Appendix E reveals the various benefits of using a PSD813F device versus the discrete solution. The members of the PSD813F family of programmable system devices are Flash-based peripherals for use with embedded microcontrollers (MCUs), and are In-System-Programmable (ISP). These PSDs are designed to easily interface to a variety of 8-bit MCUs and provide them with memory, logic, and I / O. Embedded designs are typically bound by cost, size, and power consumption. The market for products using embedded MCUs is extremely competitive. Time-to-market and quality featuresper-dollar define success. Using a PSD813F device will reduce your: Cost Time-to-market Power consumption Board space Design complexity Chip count. As you read this document, you will learn how the PSD813F can enhance your MCU, and meet its needs for: Flash memory EEPROM SRAM Configurable I / O pins Programmable logic (both sequential and combinatorial) Decoded address space Address expansion Backup power Code integrity Code security ISP. All of these features in one cost-effective PSD813F1 device allow the use of a low cost, minimal feature, ROM-less MCU device. In addition to giving step-by-step design entry information, this document highlights three areas: 1) ISP using concurrent memory or JTAG 2) MicroCell technology 3) The logic simulation capabilities of PSDsilosIII
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Note: The screen captures for this tutorial were taken using PSDsoft version 5.07. If you have a version prior to 5.07, you should update via our web site-http://waferscale.com. If you have a later version, some screens may look different, but the functionality should be the same.
1.1 Design Example
Implemented in this design example is a closed-loop Automatic Gain Control (AGC) function. An analog RF receiver section has a Programmable Gain Amplifier (PGA) to control the signal level that is output though an envelope detection circuit. The PGA gain must be adjusted in realtime to keep a constant signal level at the envelope detection output. This output is monitored by an Analog-to-Digital Converter (ADC). When the AGC function works properly, a constant signal level is output from the receiver. This signal can be used by other analog and digital circuitry for signal processing. The block diagram of the circuit is shown below.
A / D CONVERTER
PRE AMP
ENV OUT
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U1 80C31 MCU this MCU is using external memory since internal program and data storage is not sufficient. As a result, Port 0 and Port 1 are sacrificed for address and data. EPM7064SLC84-5 CPLD needed for address decoding, control logic, implementation of a paging / segmentation scheme for the Flash and EEPROM, and interfacing to the PGA and ADC. Refer to Appendix D for the complete design listing for U6. 29F010 Flash 128K x 8 program memory. Notice that address lines A14-A16 are driven by the CPLD to support additional address space. A128C256 EEPROM 32K x 8 boot memory. Allows concurrent programming of the Flash. Address lines A13-A14 are driven by the CPLD to support additional address space. DP8572A RTC programmable Real-time Clock used to time-stamp various data received by the MCU.
2K x 8 SRAM configured with battery backup protection. Generic 8-bit ADCconverts the target signal envelope into a digital value.
LH5116 the CPLD.
This IC is controlled by
Receiver Circuit collection of components that make up a signal receiver circuit, including: a PreAmp, a mixer, a Local Oscillator (LO), a PGA, and an Envelope Detector circuit. The circuit takes an RF signal through the antenna as input and outputs the signal envelope. 7414 Inverter with hysteresis U7B is used to provide a stable reset signal to the MCU (U1). U7A is part of the battery backup circuit for the SRAM.
U10 Generic OPAMP comparator part of the battery backup circuit for the SRAM. When Vcc sags below the battery voltage, the circuit switches over to the battery, which then powers the SRAM.
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EA / V P X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31
Pushbutton With Debounce Reset S 1
A T28C256
JTA G J1 C onnec t or
DO D1 D2 D3 D4 D5 D6 D7 INTR
DP8572A I / O I / O I / O 30 29 28 CO NTROL0 CO NTROL1 CO NTROL2
32.768 KH z
HEA DER 5X 2
Control0 Control1 Control2
RD C onvS tart CS
A NTENNA
U8 (Rec eiv er) A2 A1 A0 CS WR
F ilter
E nvelope D etec tor
LITHIUM B AT TERY
Doc ument Number 8X X T utor ia l- -B ef ore Integr ation Friday , J uly 17, 19 98 S heet 1 of 1
Figure 1
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DO D1 D2 D3 D4 D5 D6 D7 INTR
DP8572A
U1 EA / V P X1 X2 RES ET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PS EN A LE / P TX D RX D
Pushbutton With Debounce Reset S 1
1 7414 U7A 2 3 7414 U7B 4
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
A DIO0 A DIO1 A DIO2 A DIO3 A DIO4 A DIO5 A DIO6 A DIO7 A DIO8 A DIO9 A DIO10 A DIO11 A DIO12 A DIO13 A DIO14 A DIO15 CNTL1 CNTL0 CNTL2
Control0 Control1 Control2
PD0 PD1 PD2 RES ET PS D813F1
R S232 P ORT
3.6 V Ba ttery RX D
RD C onvS tart CS
A NTENNA
U6 (Rec eiv er) A0 A1 A2 CS WR
JTA G C onnec t or F ilter E nvelope D etec tor
S ignal Env elope
HEA DER 7X 2
Doc ument Number 8X X T utor ial - A f ter Integratio n Friday , J uly 17, 19 98 S heet 1 of 1
To Au dio A pplic ation
TMS TCK TDO
Figure 2
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1.2 Matching the Functions to a PSD813F1
Table 1 maps the functional areas of the discrete solution into the PSD813F1. The 80C31, running at 16 MHz, has a taviv (address valid to instruction valid time) of 207 ns. A PSD813F1-15 (150ns part) was selected to meet the 80C31 access time requirement. Table 1. Discrete solution compared to the PSD813F1 Design Example with Discrete Components
1. 2. 128KB Flash 32KB EEPROM
Functional Area
Matching PSD813F1 Function
Memory
Same Same Same Automatically taken care of internally by the DPLD, PSD page register, PSD VM register, and prioritized memory access. Use DPLD (Decoding PLD) Port A in latched address mode (A7-A0) Use one Output MicroCell per bit for each register
Memory Paging / Segmentation, and Control PLD / Control / Demux
3. 2KB SRAM Extra logic to drive the address lines, output enables, and chip selects to the Flash and EEPROM 1. Decoder (EPM7064S) 2. Address latch logic in CPLD Various registers used to hold data or control information to be used by external devices Latched data inputs and outputs on CPLD Combinatorial outputs on CPLD Automatic switch to battery backup
MCU I / O mode feature
same Built-in comparator automatically switches to battery power when the system voltage drops below the battery voltage on pin PC2 (Vstby) Utilizes standard JTAG and non-standard extensions (to speed programming) the JTAG port can be multiplexed with other I / O, and the memory and logic within the PSD is ISP via the JTAG port.
Supervisory / JTAG
Limited JTAG interface with no multiplexing of the JTAG port available, and no JTAG ISP of memory available
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2 The PSD813F Functional Blocks
The PSD813F provides five system-level functional blocks, and allows the user to define and configure these blocks to meet the design specification. 1. MCU Bus Interface Adapts the address, data, and control lines of a particular MCU to the PSD. Choices include multiplexed or non-multiplexed address / data bus and the associated control / handshake signals. 2. PLDs (Decode for memory and registers, General logic) The DPLD generates internal chip selects for the following PSD813F internal blocks: Flash memory EEPROM SRAM Control registers I / O Ports Peripheral I / O mode MicroCells. The CPLD implements general logical functions, such as state machines, shift registers, counters, and combinatorial logic. Both PLDs are based on Flash memory technology. 3. I / O Ports The PSD813F has four I / O ports: Ports A, B, C, and D. These ports have several modes of operation and may be selected within PSDsoft during design entry or by MCU firmware at runtime. Modes that are defined by PSDsoft are implemented with NonVolatile Memory (NVM) configuration bits that cannot be altered unless the device is reprogrammed. The remaining available I / O port operational modes are determined by the MCU writing to PSD control registers. See Application Note 55 for more details. 4. Memory The PSD813F1 has 128 Kbytes of Flash memory, 32 Kbytes of EEPROM, and 2 Kbytes of battery-backed SRAM. All of these memories may operate concurrently. That is to say that, while the MCU is executing code from one type of memory, the other memories may be written to, erased, or read. These memory blocks are placed in system address space using PSDsoft development software. The PSD813F also offers some run-time features that can be used to alter the system memory map on-the-fly, which is good for memory paging and ISP.
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5. JTAG ISC interface The PSD813F family includes a JTAG channel for In-System Programming (ISP). This ISP function is an extension of the typical JTAG boundary-scan function. It is an implementation of the JTAG-ISC (In-System Configuration) specification that is becoming an industry standard. The entire PSD device may be configured and programmed while soldered to the end product. The PSD can be completely blank before programming because the JTAG interface needs no assistance from the MCU. WSI has enhanced the standard four-wire IEEE 1149.1 JTAG interface by making two additional handshake lines available to speed-up programming. Refer to Application Note 54- JTAG Information - PSD8xxF for more information. The use of the JTAG interface and the two additional handshake lines are defined using PSDsoft. Also, the MCU has some control over the JTAG interface at runtime.
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3 PSDsoft Development Tools
3.1 PSDabel
3.2 PSD Configuration
This utility is used to specify the PSD MCU bus interface type, special I / O pin assignments, and particular internal PSD functions. The output of this module is the .glc configuration file, which is also used by the PSDsoft Fitter.
3.3 PSD Fitter
PSD Fitter has two main functions: the Fitter and the Address Translator. The Fitter accepts input from PSDabel and PSD Configuration, synthesizes this user logic and configuration, and fits the design to the PSD silicon. The Address Translator process allows the user to map the MCU firmware from a cross-compiler (in Intel HEX or S-Record format) into the NVM memory blocks within the PSD. As a result, the MCU firmware is merged with the logic and configuration definition of the PSD. The combined output of the Fitter and Address Translator is the .obj file that can be used by a programmer to program the PSD device. This .obj file can also be used to program a PSD813F using the JTAG FlashLink cable. The .obj file is comprised of the configuration, PLD fusemap, and MCU firmware.
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3.4 PSD Simulator
3.5 Parallel Programmer
Interface to the PSDpro programming device. It accepts the .obj file as input, allows viewing and editing of the .obj file, and programs and erases the PSD device.
3.6 JTAG Programmer
Interface to the FlashLink cable. It accepts the .obj file as input, and allows the PSD device to be programmed and erased in-system via the JTAG compatible FlashLink cable.
3.7 C code Generation
This is a new feature of PSDsoft that automatically generates C code functions and headers for controlling Flash PSD devices. These functions and headers are ANSI-C compatible. The generated files (.c and .h) may be edited to suit the particular application, then compiled and linked with the rest of the code. Afterwards, the linker output of the cross-compiler (usually in Intel HEX or Motorola S-record format) is merged with the configuration file of the PSD device in the Address Translate utility of PSDsoft. The functions and headers provided by PSDsoft will cover key PSD operations such as: Flash memory program and erase algorithms, EEPROM program algorithms, I / O control and definition, memory management, and power management.
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4 Design Flow
This section describes the design flow of a project-from entering the design in PSDabel- to programming the device and simulation. Figure 3 (right) shows the PSDsoft Design Flow utility. This is the first window to appear after you invoke PSDsoft. By double clicking on each box, the associated process is initiated. While this is a convenient method to navigate through the steps, this tutorial shows how to step through the process using menus and toolbars since this approach is less obvious. Section 5 takes you step-by-step through a tutorial design.
Figure 3-PSDsoft Design Flow
4.1 PSDsoft Program Flow
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5 813F Tutorial Example
5.1 Managing the Project
Each new project may have its own working directory where all the files generated by PSDsoft reside. Once you specify the new project name, PSDsoft passes the working directory and pertinent information to other functional modules. In the following sections, you will be guided through a full sample design process, and key windows are displayed to help you follow the example.
1. Start PSDsoft a dialog box titled "PSDsoft" pops up, inquiring if you want to open and existing project or create a new one. Select "Open an existing project", and click OK.
The "Open Project" dialog box appears. Click the Browse.. button.
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Click on the OK button, which closes the "Open Project" dialog box.
5.2 The PSDabel File
Your design file should now be open, as shown below.
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Compiling the Tutor Design
To compile the tutor8xx.abl file, take the following steps:
1. Click on the Options menu and select ABEL Compiler Options..
The "ABEL Compiler Options" dialog box appears. Click on each of the options, and read the description in the "Description" box to get a feel for what each option will do. Then set up the options as shown below, with the Standard Listing selected under "Listing options" and the Retain redundancy box checked. For a better description of the various options available, refer to the PSDabel HDL Reference Manual.
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Select the "Optimization Options" tab, and set up the options as shown below. Use Default should be the only item selected.
Click on the OK button when you have finished setting up the options.
Or, click on the "abl Com" button on the tool bar.
The PSDabel compiler generates an error file-tutor8xx.err (even if no errors are present), and writes to the log file-tutor8xx.plg. The compiler also generates a PLA output file, tutor8xx.tt2, which is used by PSDsoft for fitting, and is optimized based on the reduction algorithm specified in the "Optimization Options" under the Options menu.
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After compilation, you can display the optimized PLD logic equations that will be used by the Fitter by pulling down the VIEW menu and select the Compiled Equations this opens the tutor8xx.eq2 file.
Simulating your design using ABEL simulation
You can do a very simplistic functional simulation of the blocks that make up the PLD using the simulator that is included with PSDabel. It is important to note that only the functions that are generated within the .abl file can be simulated using test vectors at the end of the file. For chiplevel functional simulation, you must have the version of PSDsoft that includes the PSDsilosIII simulation software. To use the simulator that comes with PSDabel, take the following steps:
1. Click on the Options menu and select ABEL Compiler Options.. Once the "ABEL Compiler Options" dialog box appears, click on the "Simulator Options" tab, and set up the window as shown: under "Format", choose Table format. Ensure that the X-value 0 and Z-value 0 are selected in their respective boxes, and that Brief trace is selected in the "Trace" box. For the "Register" box, select the Register powerup 0, and make sure that the "Use .TMV file" box is not checked. Click on the OK button to save your changes.
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If you select Simulate Results in the View menu, PSDabel will automatically start the simulation process, and display the simulation results based on the logic equations and test vectors in the .abl file. Note: the ABEL file has four lines that should be commented out for the ABEL simulation only. If these lines are not commented out, you will get a message that 0 of 7 vectors passed in the ABEL simulation instead of the display below. The lines that need to be commented out are highlighted in the "CPLD equations" section. If you decide to edit the ABEL file, and wish to run the PSDSilosIII simulation later, you must un-comment the lines.
Your simulation results should look like the screen capture below. (See above note.)
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5.3 PSDsoft Configuration
The PSD813F has a programmable MCU bus interface and is able to interface directly to many microcontrollers. Using PSD Configuration, you can specify how to interface to the MCU you have chosen for your design. You can also configure functions specific to the PSD device you are using. This tutorial design is based on the Intel 80C31 microcontroller, which has an 8-bit multiplexed bus with / RD, / WR, and / PSEN as the control signals, and an active-high level address latch enable (ALE). To perform the configuration, take the following steps:
1. Pull down the PSDsoft menu in the main PSDsoft window and choose PSD Configuration, click the "Configuration" button, or click on "Device Config" in the "PSDsoft Design Flow" window.
A dialog box opens titled "PSD Configuration". Make sure the "MCU Bus Configuration" tab is selected. Set up the configuration as shown: Ensure 8-Bit is selected under "Data Bus Width" Mux is selected under "Address / Data Mode" High is selected under "Address Latch / Strobe Setup" The "Enable Chip-Select Input ( / CSI)" box is not checked The / WR, / RD, / PSEN is selected under "Control Setting" Data Space is selected under "Flash" Program Space is checked under "EEPROM". This arrangement for program and data space allows the MCU to boot from EEPROM in program space and download to Flash memory in data space if needed. Afterwards, the MCU can override this arrangement if, for example, it wanted to move Flash memory to program space. This can be done by the MCU writing the VM register.
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Click on the "Other Configuration" tab, and ensure that the Enable Standby Voltage Input (PC2) box is checked under "Standby Voltage", Edge is selected under "Mode of Loading MicroCell by MCU", and all other boxes are unchecked.
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Click on the "Sector Protection" tab, and ensure that none of the boxes are checked. The appropriate sector box should only be checked if it is desired that the selected sector be write protected. These bits can be changed later through the JTAG port or the device programmer.
When you are finished with the configuration settings, click on the OK button, which saves the configuration. The PSD813F configuration is now completed.
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5.4 PSD Fitter : Fitting and Address Translation
PSD Fitter consists of the Fitter and the Address Translator. The Fitter accepts input from PSDabel and PSD Configuration, synthesizes the user logic and configuration, and fits the design to the PSD813F silicon. The Address Translator process allows the user to map the MCU firmware from a cross-compiler (in Intel HEX or S-Record format) into the NVM memory blocks within the PSD. As a result, the MCU firmware is merged with the logic and configuration definition of the PSD. The combined output of the Fitter and Address Translator is the tutor8xx.obj file. 5.4.1 Fitting the Design
The input files to the Fitter are: tutor8xx.tt2PLA file generated by PSDabel. tutor8xx.glcPSD813F configuration file generated by PSD Configuration. The output files generated by the Fitter are : tutor8xx.fobPLD fusemap and PSD813F configuration file. tutor8xx.afuGenerated for use by PSDSilosIII. tutor8xx.pfuGenerated for use by PSDSilosIII. tutor8xx.objObject file (PLD and Configuration portion only). tutor8xx.frpFitter report file. To Fit a Design
1. Click on the Options Menu, and select the "Fitter Options."
For the tutorial, choose Keep Current under "Pin Assignment", and ensure that the "Enable Product Term Expansion" and "Perform Register Synthesis" boxes are checked, as shown. Click OK to save the Fitter options.
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Do This
4. Pull down the PSDsoft menu and choose PSD Fitter. Then, pull down the Fitter menu and choose Fitting.
OR This
Or, click the "Fitter" and then the "Fit" button on the tool bar.
Or This
Or, click the "Logic Synthesis and Fitting" box in the design flow and the Fitter automatically runs.
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Before we cover the Address Translator, you should be aware of a new PSDsoft feature unique to Flash PSD devices-automatic C code generation. 5.4.2 Generating C code
1. Pull down the Tools menu in the PSDsoft window and choose Generate C Code.., as shown. Alternately, click the "C Code Gen" button in the Design Flow window.
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The "C Code Generation" dialog box should appear:
The "Functions / Headers" dialog box has the following sections:
Note: the file psd813F1.h contains define statements for each individual C function within the PSD813F1.c file. Later, edit psd813F1.h, and simply remove the comment delimiters ( / / ) from the define statement for any C function that you would like to be compiled with the rest of your C source code.
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Click on the "Coded Examples" tab at the top of the dialog box.
This sheet contains several examples that you may use as a basis for building your own C code application. These are complete projects (main, functions, and headers) targeted toward a particular MCU. You may copy these files to some folder to browse them for ideas, or cut and paste sections from the examples into your own crosscompiler environment. There are three sections:
ExampleSpecify the folder that you would like to place the example project files generated by PSDsoft by clicking on the Browse.. button and selecting a folder. Example SelectionThere are several areas for which you may generate C code. Each category implements a high-level system function, such as memory paging or UART downloads to Flash memory. Description-Describes each of the coded examples in the "Example Section"
Once the C code generated by PSDsoft is integrated into your own C application and is successfully compiled and linked by your MCU cross-compiler, you are ready for address translation. Choose the desired example and click Apply for each example that you want generated. Click OK when you have finished making your selections.
Performing the Address Translation
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To perform the address translation, take the following steps:
1. Pull down the PSDsoft menu, and choose PSD Fitter. Then, pull down the Fitter menu and choose Address Translate or click the "Address Translate" button on the tool bar.
Or, select "MCU Code Mapping" in the design flow.
You will get the following message upon starting Address Translate:
This warning is a reminder to ensure that you take paging into account when entering the start / stop addresses and file names. Click OK. 2. The "Address Translate" dialog box appears. The Address Translation dialog box has the following sections: Memory Select NameName of the PSD memory segment that will be selected when the associated equation is true. Memory Select EquationsEach cell shows the equation for the appropriate PSD memory segment. These are the optimized equations from the PSDabel file. They are displayed for convenience, and cannot be modified in this window. File Address StartStarting MCU system address from MCU compiler / linker that will be mapped to a PSD memory segment. File Address StopEnding MCU system address from MCU compiler / linker that will be mapped to a PSD memory segment. File NameMCU firmware file that is generated by your MCU Compiler / Linker. Record TypeThe supported formats are Intel HEX or Motorola S-Record. Mapping ModeTwo modes of mapping are supported, direct and relative. For more information, consult the PSDsoft User Manual.
Notice that PSDsoft attempted to fill in the File Start and File Stop Addresses based on your PSDabel equations. However, if paging is used (as in this tutorial), these file addresses must be
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handled carefully since PSDsoft does not know how your MCU cross-compiler and linker handles paging. As we progress, this process should become clear.
Memory Select
FS0 FS1 FS2 FS3 FS4 FS5 FS6 FS7 EES0 EES1 EES2 EES3
File Start Address
0000 4000 8000 C000 8000 C000 8000 C000 0000 2000 -
File Stop Address
3FFF 7FFF BFFF FFFF BFFF FFFF BFFF FFFF 1FFF 3FFF -
File Name
In this design, a different file name was used for each of several sections of code in Flash memory because of the address space overlap of the segments. This file scheme is used because, even though these sections of code physically reside on different memory pages, some linkers will place them in overlapping absolute address space. The method you use depends on your linker. Alternatively, you can use a single file name across many memory chip selects if your linker automatically appends extra address bits that represent your paging scheme. You would then, for example, enter 18-bit addresses to accompany the single file name (which is passed to the Address Translate utility), instead of 16-bit addresses to accompany several file names. NOTE: Optionally, you can specify only the EEPROM contents to be programmed by the device programmer. It may be desired to load system code into Flash memory while in-system, not on a device programmer. In this case, only information for EES0 and EES1 should be entered in the Address Translate utility.
5. 6. 7. Ensure that Direct Mapping is selected in the "Mapping Mode" box. Select Intel Hex Record in the "Record Type" box. Click on OK to perform the address translation. If no errors are indicated, then tutor8xx.obj will be appended.
If your copy of PSDsoft includes the PSDsilosIII simulator, you should simulate and verify your design before programming the PSD813F. Refer to the next section on how to simulate the tutorial design.
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5.5 PSD813F Chip Simulation
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Running the Logic Simulator
To run the simulator, take the following steps:
1. 2. Review the stimulus file (tutor8xx.stl) listed in Appendix B. Pull down the PSDsoft menu in the main PSDsoft window and select PSD Simulator or click the "simulator" button on the tool bar. This open up the tutor8xx.stl stimulus file for editing within PSDsoft.
The tutor8xx.stl file is automatically opened in PSDsoft, as shown.
At this point, you could edit the stimulus file, but since we have a complete stimulus file, click on LogicSim to invoke the PSDsilosIII simulator.
Note: to go directly to the PSDsilos simulator, click on the "Logic Sim" box in the design flow.
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The following events happen automatically as a result of clicking on the LogicSim button: The PSDsilosIII simulator automatically starts The simulator automatically loads the project tutor8xx.spj, PSDsoft.run, and a window displaying the tutor8xx.stl file, as shown.
Click on the "Go" button, which automatically opens an "Output" window (shown below) for viewing the results of the simulation:
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Running the Analyzer
Now that the logic simulation is complete, the results can be displayed with the PSDsilosIII Data Analyzer by performing the following steps:
1. Pull down the Window menu and select Open New Data Analyzer, press F6, or click on the appropriate button on the tool bar.
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Working With the Explorer
The Explorer in PSD SilosIII can be used in conjunction with the Data Analyzer to add and trace signals.
For more information on the Explorer or Data Analyzer, see the on-line help and the PSDsilosIII User Manual. Also, refer to this manual for information on how to us the PSDsilosIII Watch Window, which is not covered because it is beyond the scope of this tutorial.
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5.6 Programming the PSD813F
Programming the PSD813F using PSDsoft can be accomplished two ways: using the parallel programmer called PSDpro or the serial programmer called Flashlink. Section 5.6.1 is dedicated to the PSDpro, and section 5.6.2 is for the Flashlink. Either interface can perform the following operations: 5.6.1 Blank Testcheck to see if the device is blank. Uploadupload the contents of the device. Programprogram the device with the .obj file. Verifyverify the programmed device against the .obj file in the buffer. Erasecompletely erase the device. PSDpro
Pull down the PSDsoft menu in the main PSDsoft window and choose PSD Programmer, click the appropriate button on the tool bar, or click on the "Device Prog" box in the design flow. Any of these actions will open the tutor8xx.obj file, as shown below.
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To correct this problem, refer to your computer hardware user manual and the user manual for MS Windows or Windows NT. If you have your PSDpro properly connected to the parallel port, you should see the red power light come on upon entering the Parallel Programming software. If your green "good" light is on, you may skip to the programming portion of this section. If the red power light is on, but the green "good" light is not, take the following steps to set up the PSDpro"
Once the "PSD Programmer - Hardware Setup" dialog box appears, under the "Hardware Section:", select PSDpro. Next, you will see that the Auto Select option becomes active. This means that PSDsoft will automatically detect which PC parallel port your PSDpro is connected to. Just click OK and the PSDpro will be detected and configured if the connections are good. You should now see that the green "good" LED is on. If you get a self-test failure like the one shown above, there is most likely a problem with your parallel port. Getting the parallel port working correctly is beyond the scope of this document.
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To go any further, you must have your PSDpro working properly, and a PSD813F device ready for programming. Assuming this is the case, take the following steps to program the device using a PSDpro programmer:
The "PSD Programmer - Program Confirmation" dialog box appears, which enables the user to program the Flash, EEPROM or PLD / ACR (PSD Configuration) regions of the device. Select "All", as shown. You may choose to enable Software Data Protect (SDP) for the EEPROM. By doing so, the MCU will have to "unlock" the EEPROM (just like Flash) before writing or erasing. Devices are shipped from the factory with SDP disabled. See the PSD813F Family Data sheet for details. Place the PSD device into the programmer using the correct orientation, and snap the lid down on the device carrier. Then, click on the OK button. As programming takes place, the PSDpro programmer checks each location after it is programmed to make sure it matches the .obj file contents. If a particular location cannot be programmed properly, an error message will appear. If this occurs, you must start over and program a fully erased and functional part.
Note: if your device is not blank, you will get the following message (or a similar one) after you click OK. Put in a blank part or proceed as desired.
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Once the programming operation has completed, assuming there were no errors, you should see a message similar to the following. (If you used the tutor8xx.obj file, you should see the same checksum numbers.) Congratulations, you have now successfully programmed a part. You are now ready to proceed with your own design.
JTAG-FlashLink
If you intend to use JTAG to program your PSD, you should read this section. Note: before you proceed, ensure that you have the latest version of PSDsoft by visiting our web site- http://waferscale.com. The first part deals with setting up your FlashLink cable. If you have already confirmed that your FlashLink cable is working properly, you can skip to the second part that deals with the programming process. Before you proceed, you should start the JTAG Programmer under PSDsoft. To do so, pull down the PSDsoft menu and choose JTAG Programming, click the "JTAG" button on the toolbar, or click on "JTAG Prog" in the design flow.
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You should now see the following screen. Figure 5-JTAG Chain Setup Dialog Box
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We will now perform the Loopback Test. To do so, click on the Loop Test button. The "FlashLink Loop Test" information screen will pop up. Follow the instructions for the Test, and click OK.
If you get this message, your parallel port is working properly. Click OK, and go on to the next section.
If you get this message, the FlashLink is not receiving information from the parallel port. Try changing your selection in the "Hardware Setting" dialog box under "Parallel Port:" to whichever parallel port number you have your FlashLink cable connected, and rerun the test above. If you are still experiencing problems, you will need to get your parallel port working properly before you can continue, which is beyond the scope of this document.
If you get this message, ensure that Vcc and Ground wires are connected to the correct pins and that the pins are at the correct voltage potential. You should have between 4.5 and 5.5 V for non low-power parts (parts with no V suffix) and between 2.7 and 3.3 V for low-power parts with the V suffix. If you have the correct voltage, you should not see this message.
Once you have determined that your Parallel port is working properly (because your FlashLink Loop Test passed), you are now ready to attempt to program your part. The next part covers how to program the part using your FlashLink cable.
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1. Right-click on line # 1 in the "Chain Information" box and select Properties .., as shown.
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You should see the "JTAG Chain Setup Properties." Ensure that the "Set Pins / Flow Control" tab is selected, and set up the window with the following selections based Figure 2 of this tutorial (proper selections shown right): Under "Flow Control", select Option 3. In the "Set Pins" box, set up the ports as follows: Port A: set all the pins to "OUTPUT LOW (CMOS)" Port B: set pins pb7 to pb3 to "INPUT (HI-Z)", and pins pb2 to pb0 to "OUTPUT LOW CMOS)" Port C: change pc3 to "TSTAT (CMOS)", and pc4 to "TERR (CMOS)". Leave the rest of the pins as is. Port D: set pins pd1 and pd0 to "INPUT (HI-Z)", and pd2 to "OUTPUT HIGH (CMOS)" Click on the Apply button if you made any changes. This saves any changes you have made so far.
Click the "JTAG Attributes" tab. You will see the screen shown. If you are using the tutor8xx.jcf file, there is nothing for you to do here. If you are using your own JTAG Chain File, read the following note and go to the appropriate section below.
Note: the "Device Name", "Instruction Register Length:", and "JTAG Device ID:" are all grayed out because this information is automatically entered whenever you select a PSD813F device. If you wanted to enter information about a non-PSD device that would be included in your chain, here is the place to do it. If you did add another device, you would need to enter valid information in the "JTAG Attributes" section. Also, note that if you select the "JTAG Device ID:" box, PSDsoft will verify the JTAG ID before programming or erasing the device.
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Click on the "User Code" tab. If you enter a value in the "User Code" box, the value will be compared with the User Code already programmed into the device before any JTAG operation occurs (e.g. Erase, Program, etc.). If you leave this area blank, no comparison will be done. Enter ABCDEF12 in the "User Code" box. Then press Apply (which grays the "Apply" button out), and finally press OK.
Now, you should be back to the "JTAG Chain Setup" window (Figure 5). Rightclick on the same line as you did in step 1, only this time, choose Program.
You should now see the "Operation: Program" dialog box. Ensure that All is checked in the "Regions:" section.
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Your "JTAG Chain Setup" should now have the following look. Select Go, and the PSD will be programmed with the information in the tutor8xx.obj file.
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Setting up a JTAG Chain
The following rules apply for setting up a JTAG chain:
A JTAG chain of one to or more devices must be defined. All JTAG compatible devices that are connected to the JTAG bus, including the PSD813F
and non-PSD devices from other vendors compose a JTAG chain.
Non-PSD devices that are part of the JTAG chain will be placed in bypass mode
automatically.
The length of the instruction register, along with a name and device ID must be entered for
each non-PSD device. (In future versions of PSDsoft, you will be able to automatically load this information with a BSDL file.)
Before programming the PSD device(s), the user must have a valid .obj file for each PSD
device in the chain. Please refer to document titled JTAG Information - PSD8xxF (Application Note 54) for information in these areas: JTAG Spec Compliance Programming Support Program / Erase Flow Control SVF / BSDL file information Enhanced ISP functions Multiplexed JTAG pin functions Dedicated JTAG pin functions WSI JTAG ISP connector JTAG Chaining Electrical Considerations.
1. If you are currently using the JTAG Programming software, exit it by clicking on the button in the upper right-hand corner of the "JTAG Chain Setup" dialog box.
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You should see a "JTAG Chain Setup" dialog box that is "blank, " as shown below. Go to the "Chain Information" box and click the Browse.. button.
The "Open" window pops up. tutor8xx.obj file and click Open.
Select the
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Your "JTAG Chain Setup" window should now look like this:
Note: If the device name (PSD813F1 in this case) does not automatically appear in the "Device Name" window, click on the down arrow next to "Device Name", and select the PSD813F1.
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Click the Add button. Your "JTAG Chain Setup" window should look like this:
Save your work in a JTAG Chain File for future use. To do so, click on the Save button. This action brings up the "Save As" dialog box. Type tutor8xx in the "File name:" box, and click Save. The file tutor8xx.jcf will be created. This is now identical to the file we were working with before.
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Now, the "JTAG Chain Setup" window should look like this:
Note: if you need to load this .jcf file in the future, you will have to click on the top Browse.. button, which would bring up the "Open" dialog box. Choose the tutor8xx.jcf file, and click Open.
10. If you wanted to add any more devices to the JTAG chain file, you would repeat Steps 4 through 8.
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ISP and the PSD813F
The PSD813F may be programmed in-system, with or without participation from the MCU. For ISP with the MCU, see Appendix F for UART download information and considerations. For ISP without MCU participation, see section 5.6.2 and Application Note 54, JTAG Information PSD8XXF for FlashLink JTAG programming within the PSDsoft environment.
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Appendix AABEL Design FileTutor8xx.abl
" Bus Interface signal declarations / / The reserved signal names are automatically assigned to the appropriate pin / / The following are inputs from the MCU wr pin "CNTL0 Input:(pin 47)- write strobe rd pin "CNTL1 Input:(pin 50)- read strobe psen pin "CNTL2 Input:(pin 49)- program store enable ale pin "PD0 Input:(pin 10)- address latch enable reset pin "Input:(pin 48)- system reset a15.a0 pin "Input:(pins 46.39, 37.30)- demuxed address
Port A, B, C, D pin declaration
/ / Port D I / O / / pd0 (pin 10) is assigned above to the ALE signal from the microcontroller. / / Any external chip selects that are generated by decoding an address should be placed on / / Port D when possible to save as many resources as possible. RTCcsn pin 8 "Real Time Clock (RTC) chip select / JTAG TDO clkin pin "Port D pin pd1 (pin 9) System clock
"This signal is needed to save product terms "True when the measured signal equals the desired signal level
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It is used to enable
/ / The following page register bit definitions are an example of how to manipulate memory to / / facilitate ISP. This scheme is explained in Appendix F of Application note 57.
node 117
DEFINITIONS
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CPLD equations
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Appendix BStimulus FileTutor8xx.stl
/ / Title: / / Function: / / Designed by: / / Design Date: / / Description: / / / / / / / / / / / / / / / / / / tutor8xx.stl Simulation file for the PSD8xx Tutorial Dan Harris 6-23-98 This file is intended to be used in the PSDsilosIII environment as a stimulus file for the PSD8xx Tutorial. The idea of this file is not to show how the Verilog-HDL language works, but rather the format of a .stl file, and how it applies to this tutorial example. The main parts of this file are: Parameter declarations which make the file more readable Read, write and "PSEN / " bus cycle tasks for the 80C31 An area where the user may wish to add to the file in order to test more functions The actual stimulus of the design
/ / +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ / / Parameters declarations for the address offsets for the CSIOP address space / / +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ / / Port A parameter parameter parameter parameter / / Port B parameter parameter parameter parameter
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/ / Latch the address lines / / Read the valid address (adio defined in .top file) / / Ale inactive / / Write operation / / Write pulse / / Write ends / / Z16 defined in .top file
the 80C31 read bus cycle timing
/ / Latch the address lines / / Read the valid address / / Ale inactive / / Float address bus (Z8 defined in .top) / / Read pulse / / Read ends
the 80C31 psen program fetch bus cycle
/ / Latch the address lines / / Set-up the right address / / Ale inactive / / Float address bus / / Read pulse / / Read ends
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Appendix CList of PSD813F Simulation Signals
This is a list of signals from the Explorer that can be viewed using the PSDsilosIII Data Analyzer. This list is based on the tutor8xx.abl file, and predefined signals. The list will vary depending on the names in your .abl file, but most of the signals will be the same. Note: to get at some of the internal PSD813F signals, you will have to click on the plus sign to expand the list. See circle below.
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Table C1Predefined Signal Names and their Descriptions Signal / Bus Name
Description
VM register Address / Data bus high byte Address / Data bus low byte Port x control register Non-multiplexed 8-bit data bus Port x data in register Port x direction register Port x data out register Port x drive register External chip select output n EEPROM output enable EEPROM power down signal PSD security and EEPROM sector protection EEPROM ready / busy signal EEPROM software data protection disable bit EEPROM software data protection enable bit EEPROM toggle signal EEPROM final chip select Enable to port x driver Flash sector protection register (read only) Flash output enable Flash data polling bit Flash ready / busy signal Flash toggle bit Flash final chip select JTAG enable register Mask AB register outputs Mask BC register outputs Micro Cell AB n output Output Micro Cell AB n clock input Output Micro Cell AB n preset input Output Micro Cell AB n register input Output Micro Cell AB n reset input Output Micro Cell BC n output Output Micro Cell BC n clock input Output Micro Cell BC n preset input Output Micro Cell BC n register input Output Micro Cell BC n reset input Product term control port x7:4 or x3:0 input Micro Output registers for Micro Cell AB Output registers for Micro Cell BC Port x, pin n Port x, Input Micro Cell n Port x, output enable n product term Power down signal Page register outputs Power management mode register n Port n peripheral select PSD internal ready / busy status signal SRAM output enable signal
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Appendix DDesign file for EPM7064S (U2 of Figure 1)
Convention:
CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT
subdesign 8xxtutor ( - The following signals are A / D7.0 : BIDIR -A15.8 : INPUT -RD~ : INPUT -WR~ : INPUT -ALE : INPUT -PSEN~ : INPUT -
generated by the MCU (U1): Multiplexed address (lower byte) / data bus Upper byte of the addr bus Read strobe Write strobe addr latch enable signal Program store enable
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LATCH - Must demux lower byte of addr DFFE - Page register DFFE - Used for memory mapping in combined memory space mode DFFE - Register to store the desired signal level (set by the MCU) DFFE - Register to store the gain level (set by the MCU) DFFE - takes state machine out of idle state (s0) DFFE - MCU I / O mode control register NODE - Demultiplexed addr NODE - FLASH segment enable signals NODE - EEPROM segment enable signals NODE - bit 7 of the page register NODE - bit 6 of the page register NODE - Output from the ADC NODE - Input from the MCU NODE - True when the measured value equals the desired one MACHINE WITH STATES (s0, s1, s2, s3)
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