Application Note Harris Mark Rootz February, 1999 47280
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PSD813F1/ 80C31 Design Tutorial
Application Note
Harris Mark Rootz
February, 1999
47280 Kato Road, Fremont, 94538 Telephone: (510)-656-5400 (800) TEAM-WSI (832-6974) Site: http://waferscale.com E-mail: info@wsipsd.com
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March 1999-REV
PSD813F1/ 80C31 Design Tutorial
Application Note
Harris Mark Rootz
Contents
Introduction Design Example Matching Functions PSD813F1 PSD813F Functional Blocks PSDsoft Development Tools PSDabel Configuration. Fitter Simulator Parallel Programmer JTAG Programmer. code Generation. Design Flow. PSDsoft Program Flow 813F Tutorial Example. Managing Project PSDabel File 5.2.1 Compiling Tutor Design. 5.2.2 Simulating your design using ABEL simulation. PSDsoft Configuration. Fitter Fitting Address Translation 5.4.1 Fitting Design. 5.4.2 Generating code. 5.4.3 Performing Address Translation. PSD813F Chip Simulation. PSDsoft.run File. 5.5.1 5.5.2 Running Logic Simulator 5.5.3 Running Analyzer. 5.5.4 Working With Explorer. Programming PSD813F 5.6.1 PSDpro 5.6.2 JTAG-FlashLink. PSD813F Appendix ABEL Design File Tutor8xx.abl. Appendix Stimulus File Tutor8xx.stl. Appendix List PSD813F Simulation Signals Appendix Design file EPM7064S Figure Appendix Discrete Solution (Figure Compared Integrated Solution (Figure Appendix System Memory UART ISP.
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Introduction
This tutorial takes step-by-step through development cycle PSD813F based design, from design entry, programming device. first part this tutorial shows PSD813F1 used conjunction with handful other implement automatic gain control (AGC) design. tutorial also shows this design would implemented using discrete part solution, Appendix reveals various benefits using PSD813F device versus discrete solution. members PSD813F family programmable system devices Flash-based peripherals with embedded microcontrollers (MCUs), In-System-Programmable (ISP). These PSDs designed easily interface variety 8-bit MCUs provide them with memory, logic, I/O. Embedded designs typically bound cost, size, power consumption. market products using embedded MCUs extremely competitive. Time-to-market quality featuresper-dollar define success. Using PSD813F device will reduce your: Cost Time-to-market Power consumption Board space Design complexity Chip count. read this document, will learn PSD813F enhance your MCU, meet needs for: Flash memory EEPROM SRAM Configurable pins Programmable logic (both sequential combinatorial) Decoded address space Address expansion Backup power Code integrity Code security ISP. these features cost-effective PSD813F1 device allow cost, minimal feature, ROM-less device. addition giving step-by-step design entry information, this document highlights three areas: using concurrent memory JTAG MicroCell technology logic simulation capabilities PSDsilosIII
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typical design with Flash memory consists MCU, main Flash memory, either boot PROM SRAM implement download main Flash memory over UART channel, some other communication link. systems that SRAM ISP, Flash programming algorithm must first downloaded SRAM then executes from SRAM during ISP. power interruption system glitches that occur during download cripple system. Therefore, boot PROM necessity applications that demand high system reliability. However, boot PROM adds cost system difficult update once service. Flash-based PSDs address these concerns combine elements necessary enable easily download main Flash memory boot memory while in-system. method just described requires participation. PSD813F also offers another method that uses JTAG interface, requires participation. This means that completely blank soldered into place, entire chip programmed insystem using WSI's JTAG FlashLink cable PSDsoft development software. This powerful feature PSD813F that allows easy field updates. Typically, adding peripheral memory space involves great amount circuitry decode addresses lines, latch data, handle timing. This "overhead" circuitry required peripheral needed PSD813F device used since address, data, control signals already routed processed inside PSD. MicroCells take advantage this, allowing designer build logic peripherals inside efficient flexible manner. This tutorial compares MicroCell design with equivalent functional design using Altera EPM7064S CPLD device emphasize efficiency PSD. PSD813F Output MicroCells (OMCs) Input MicroCells (IMCs). Each MicroCell occupies memory location address space connected data bus. ability load flip-flops OMCs read them back useful such applications loadable counters, shift registers, other system logic. IMCs latch external inputs read microcontroller. IMCs also useful implementing handshake communication logic with outside source. provides complete chip-level Verilog-HDL models devices with optional PSDsilosIII simulator. These models used conjunction with user-defined stimulus file simulate functionality PSD. PSDsilosIII also comes with Waveform Editor/Viewer Watch window (for stepping through simulation) that used conjunction with stimulus file. Most PSD's status control signals, well user-defined logic CPLD, available with Waveform Editor/Viewer Watch window. Thus, user define MCU-level tasks, such read write that used external chip-level stimuli PSD. results stimuli viewed using Waveform Editor/Viewer Watch window PSDsilosIII. utility featured PSDsoft version 5.X. This utility automatically generates ANSI-C code functions, used with user's choice cross-compilers.
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Note: screen captures this tutorial were taken using PSDsoft version 5.07. have version prior 5.07, should update site-http://waferscale.com. have later version, some screens look different, functionality should same.
Design Example
Implemented this design example closed-loop Automatic Gain Control (AGC) function. analog receiver section Programmable Gain Amplifier (PGA) control signal level that output though envelope detection circuit. gain must adjusted realtime keep constant signal level envelope detection output. This output monitored Analog-to-Digital Converter (ADC). When function works properly, constant signal level output from receiver. This signal used other analog digital circuitry signal processing. block diagram circuit shown below.
80C31 BOOST
STATE
CONTROL
CLOS
CONVERTER
ILTE
LATE
BASE BAND
Block Diagram Automatic Gain Control circuit could perform real-time gain adjustment, leaving little execution time other tasks. Therefore, highly desirable free off-loading these repetitive tasks with hardware. This accomplished moving some this functionality into state machine programmable logic. above configuration, will load state machine with desired signal level start state machine. then perform other tasks interrupted state machine. interrupt occurs signal drifts from desired level. state machine this because reading outputs comparing measured value with desired value. state machine will provide additional signals with each interrupt, `Trim' `Boost'. signal level from receiver high, interrupts will accompanied `Trim', will decrement gain value PGA. Likewise,
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signal level low, interrupts from state machine will accompanied `Boost'. Once this closed-loop process started, perform other tasks need only interrupted when gain correction required. This tutorial shows implement this function different ways: discrete solution (individual devices programmable logic, memory, etc.) integrated solution. addition function, other features implemented, such Real-TimeClock (RTC), In-System Programmability (ISP), miscellaneous signals. Please refer Appendix information related system memory mapping, issues using UART, memory paging considerations. We'll look discrete solution first, which requires four extra devices implement functionality described previously. 80C31 application that 128K Flash memory, battery-backed SRAM, EEPROM, real-time clock (RTC), 8-bit analog-to-digital converter (ADC), JTAG interface, EPM7064S CPLD, analog receiver circuit (including PGA). Following that, show Flash, EEPROM, SRAM, CPLD, battery backup circuit combined into PSD813F1 device. individual discrete solution, shown Figure described below.
80C31 this using external memory since internal program data storage sufficient. result, Port Port sacrificed address data. EPM7064SLC84-5 CPLD needed address decoding, control logic, implementation paging/segmentation scheme Flash EEPROM, interfacing ADC. Refer Appendix complete design listing 29F010 Flash 128K program memory. Notice that address lines A14-A16 driven CPLD support additional address space. A128C256 EEPROM boot memory. Allows concurrent programming Flash. Address lines A13-A14 driven CPLD support additional address space. DP8572A programmable Real-time Clock used time-stamp various data received MCU.
SRAM configured with battery backup protection. Generic 8-bit ADCconverts target signal envelope into digital value.
LH5116 CPLD.
This controlled
Receiver Circuit collection components that make signal receiver circuit, including: PreAmp, mixer, Local Oscillator (LO), PGA, Envelope Detector circuit. circuit takes signal through antenna input outputs signal envelope. 7414 Inverter with hysteresis used provide stable reset signal (U1). part battery backup circuit SRAM.
Generic OPAMP comparator part battery backup circuit SRAM. When sags below battery voltage, circuit switches over battery, which then powers SRAM.
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P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 LE/P EPM7064S H_CS/ H_CS/
RESET INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31
Pushbutton With Debounce Reset
7414 RTC_INTR/ INTR/ RESET/
EEPRO EEPRO
1/01
TRIM
EEPRO M_OE/ EEPRO M_CS
E2/GCLK2
T28C256
128K
RTC_CS
29F010 RESET/ Cloc INT/ Clk1 DC_OUT7 DC_OUT6 DC_OUT5 DC_OUT4 M_CS/ EEPRO EEPRO EEPRO M_OE/ EEPRO M_CS RTC_CS
onnec
Cloc
S232
sc_In sc_O
INTR
RTC_INTR/
DP8572A NTROL0 NTROL1 NTROL2
32.768
TRIM _Din2 _Din1 _Din0
Control0 Control1 Control2
LH5116 1/02 1/O5 1/O6
A_Din2 A_Din1 A_Din0
onvS tart
M_CS/
NTENNA
(Rec
ilter
nvelope etec
PE_O
7414
LITHIUM TERY
Date:
ument Number utor Integr ation Friday heet
Figure
Now, let's compare integrated design Figure discrete design Figure memory (U3, battery backup circuit (U9A U10) Figure incorporated into PSD813F1 (U2) Figure Also, functions handled CPLD Figure taken care PSD's CPLD. pins individually configured match functions implemented original design. Using JTAG, entire PSD813F1 device programmed. Also, JTAG pins multiplexed with other I/O. These JTAG features beyond capabilities EPM7064
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RTC_CS
sc_In sc_O
INTR
RTC_INT/
DP8572A
INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 LE/P
32.768 NTROL0 NTROL1 NTROL2 _DIN0 _DIN1 _DIN2 DC_OUT4 DC_OUT5 DC_OUT6 DC_OUT7
Pushbutton With Debounce Reset
7414 7414
INT/ RTC_INT/
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 CNTL1 CNTL0 CNTL2
Control0 Control1 Control2
TRIM
74HC126 (TMS) (TCK) (TDI) (TDO) C_INT/ RT_CO TRIM TERR/; JEN/ INT/
tem_ Cloc
RTC_CS
D813F1
JEN/
S232
ttery
A_Din0 A_Din1 A_Din2
A_CS
onvS tart
NTENNA
(Rec
onnec ilter nvelope etec
ignal elope
Date:
ument Number utor Integratio Friday heet
pplic ation
Figure
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Matching Functions PSD813F1
Table maps functional areas discrete solution into PSD813F1. 80C31, running MHz, taviv (address valid instruction valid time) PSD813F1-15 (150ns part) selected meet 80C31 access time requirement. Table Discrete solution compared PSD813F1 Design Example with Discrete Components
128KB Flash 32KB EEPROM
Functional Area
Matching PSD813F1 Function
Memory
Same Same Same Automatically taken care internally DPLD, page register, register, prioritized memory access. DPLD (Decoding PLD) Port latched address mode (A7-A0) Output MicroCell each register
Memory Paging/ Segmentation, Control PLD/Control/ Demux
SRAM Extra logic drive address lines, output enables, chip selects Flash EEPROM Decoder (EPM7064S) Address latch logic CPLD Various registers used hold data control information used external devices Latched data inputs outputs CPLD Combinatorial outputs CPLD Automatic switch battery backup
mode feature
same Built-in comparator automatically switches battery power when system voltage drops below battery voltage (Vstby) Utilizes standard JTAG non-standard extensions speed programming); JTAG port multiplexed with other I/O, memory logic within JTAG port.
Supervisory/ JTAG
Limited JTAG interface with multiplexing JTAG port available, JTAG memory available
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PSD813F Functional Blocks
PSD813F provides five system-level functional blocks, allows user define configure these blocks meet design specification. Interface Adapts address, data, control lines particular PSD. Choices include multiplexed non-multiplexed address/data associated control/handshake signals. PLDs (Decode memory registers, General logic) DPLD generates internal chip selects following PSD813F internal blocks: Flash memory EEPROM SRAM Control registers Ports Peripheral mode MicroCells. CPLD implements general logical functions, such state machines, shift registers, counters, combinatorial logic. Both PLDs based Flash memory technology. Ports PSD813F four ports: Ports These ports have several modes operation selected within PSDsoft during design entry firmware runtime. Modes that defined PSDsoft implemented with NonVolatile Memory (NVM) configuration bits that cannot altered unless device reprogrammed. remaining available port operational modes determined writing control registers. Application Note more details. Memory PSD813F1 Kbytes Flash memory, Kbytes EEPROM, Kbytes battery-backed SRAM. these memories operate concurrently. That that, while executing code from type memory, other memories written erased, read. These memory blocks placed system address space using PSDsoft development software. PSD813F also offers some run-time features that used alter system memory on-the-fly, which good memory paging ISP.
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JTAG interface PSD813F family includes JTAG channel In-System Programming (ISP). This function extension typical JTAG boundary-scan function. implementation JTAG-ISC (In-System Configuration) specification that becoming industry standard. entire device configured programmed while soldered product. completely blank before programming because JTAG interface needs assistance from MCU. enhanced standard four-wire IEEE 1149.1 JTAG interface making additional handshake lines available speed-up programming. Refer Application Note JTAG Information PSD8xxF more information. JTAG interface additional handshake lines defined using PSDsoft. Also, some control over JTAG interface runtime.
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PSDsoft Development Tools
PSDsoft WSI's integrated system development software tool, which runs Windows 95/98 Windows environments. PSDsoft supports configuration functional blocks described previous section. Figure section shows PSDsoft design process flow devices. PSDsoft consists following major modules: PSDabel Configuration Fitter Simulator Parallel Programmer JTAG Programmer Code Generator. Section shows each these modules used conjunction with PSD813F during typical design cycle.
PSDabel
PSDabel MINC's ABEL (formerly DATA ABEL) engine core. PSDabel environment provides editor create/edit .abl file that used define chip select logic, general-purpose logic, configuration parameters. Template files provided many combinations. When .abl file compiled, logic synthesized files created passed PSDsoft fitting utility.
Configuration
This utility used specify interface type, special assignments, particular internal functions. output this module .glc configuration file, which also used PSDsoft Fitter.
Fitter
Fitter main functions: Fitter Address Translator. Fitter accepts input from PSDabel Configuration, synthesizes this user logic configuration, fits design silicon. Address Translator process allows user firmware from cross-compiler Intel S-Record format) into memory blocks within PSD. result, firmware merged with logic configuration definition PSD. combined output Fitter Address Translator .obj file that used programmer program device. This .obj file also used program PSD813F using JTAG FlashLink cable. .obj file comprised configuration, fusemap, firmware.
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Simulator
WSI's version SIMUCAD's SILOSIII simulation software provides functional chip-level simulation devices. PSDsoft automatically creates files input simulator. These files convey relevant design information simulator. result, user only create stimulus file since signals node names taken from .abl file.
Parallel Programmer
Interface PSDpro programming device. accepts .obj file input, allows viewing editing .obj file, programs erases device.
JTAG Programmer
Interface FlashLink cable. accepts .obj file input, allows device programmed erased in-system JTAG compatible FlashLink cable.
code Generation
This feature PSDsoft that automatically generates code functions headers controlling Flash devices. These functions headers ANSI-C compatible. generated files edited suit particular application, then compiled linked with rest code. Afterwards, linker output cross-compiler (usually Intel Motorola S-record format) merged with configuration file device Address Translate utility PSDsoft. functions headers provided PSDsoft will cover operations such Flash memory program erase algorithms, EEPROM program algorithms, control definition, memory management, power management.
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Design Flow
This section describes design flow project-from entering design PSDabel- programming device simulation. Figure (right) shows PSDsoft Design Flow utility. This first window appear after invoke PSDsoft. double clicking each box, associated process initiated. While this convenient method navigate through steps, this tutorial shows step through process using menus toolbars since this approach less obvious. Section takes step-by-step through tutorial design.
Figure 3-PSDsoft Design Flow
PSDsoft Program Flow
Here high-level steps complete design. Create open project after entry into PSDsoft. creating project, specify project name, directory path, device family, part number, provide small description design desired. Select design template (project.abl file), modify this template your design. PSDabel edit, compile, optimize project.abl file. Perform ABEL simulation desired. you'll need create necessary test vectors place them PSDabel file. successful PSDabel compile operation will generate optimized file (project.tt2) Fitter. Configure device using Configuration; this generates project.glc file Fitter. design using Fitter. Fitter's input files obtained from PSDabel Configuration. Fitter generates project.fob file that passed Address Translator. Fitter also generates fusemap files, project.afu project.pfu Simulator. After successful fit, possible skip step (simulation) desired since PSDsilosIII used before after firmware merged with configuration.
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Generate code desired. Edit this code suit your particular application. Then, compile link with your other application code. Your cross-compiler will output Intel Motorola S-record file containing firmware. Perform address translation. Address Translator combines firmware file project.fob file into project.obj file. This project.obj file includes firmware, fusemap, configuration bits. Verify design using Simulator. Chip level simulation based user's Verilog stimulus file (project.stl) fusemap files from Fitter. must create project.stl file. However, PSDsoft creates files used with simulator that allow same names that appear your project.abl file, various reserved names. PSDsoft download project.obj file PSD813F PSDpro FlashLink JTAG programmer. compatible third party programmer also used. Contact representative near list compatible programmers.
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813F Tutorial Example
This section uses tutorial design example illustrate steps implement functionality discussed section files required, which were generated tutorial design, found directory. this point, wish start PSDsoft program, that follow along with tutorial example.
Managing Project
Each project have working directory where files generated PSDsoft reside. Once specify project name, PSDsoft passes working directory pertinent information other functional modules. following sections, will guided through full sample design process, windows displayed help follow example.
Start PSDsoft; dialog titled "PSDsoft" pops inquiring want open existing project create one. Select "Open existing project", click
Note, exited PSDsoft without closing whatever project might have been working that project will automatically reopened. don't above dialog box, pull down Project menu select Open Project.
"Open Project" dialog appears. Click Browse. button.
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"Open" window appears. directory, select tutor8xx.ini file, click Open button, which closes "Open" dialog box.
Click button, which closes "Open Project" dialog box.
PSDabel File
detailed information PSDabel relates PSD813F, please read comments file tutor8xx.abl Appendix Also, refer WSI's Application Note (PSD GPLD PrimerPSD6XX/7XX/8XX) PSDsoft PSDabel-HDL Reference Manual. more information system memory this tutorial design, Appendix open tutor8xx.abl design file, click View->Design File, click "Design Entry" button tool bar, click "Design Entry" design flow window.
Your design file should open, shown below.
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5.2.1
Compiling Tutor Design
compile tutor8xx.abl file, take following steps:
Click Options menu select ABEL Compiler Options.
"ABEL Compiler Options" dialog appears. Click each options, read description "Description" feel what each option will Then options shown below, with Standard Listing selected under "Listing options" Retain redundancy checked. better description various options available, refer PSDabel Reference Manual.
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Select "Optimization Options" tab, options shown below. Default should only item selected.
Click button when have finished setting options.
Click Compile->Compile.
click "abl Com" button tool bar.
PSDabel compiler generates error file-tutor8xx.err (even errors present), writes file-tutor8xx.plg. compiler also generates output file, tutor8xx.tt2, which used PSDsoft fitting, optimized based reduction algorithm specified "Optimization Options" under Options menu.
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After compilation, display optimized logic equations that will used Fitter pulling down VIEW menu select Compiled Equations; this opens tutor8xx.eq2 file.
5.2.2
Simulating your design using ABEL simulation
very simplistic functional simulation blocks that make using simulator that included with PSDabel. important note that only functions that generated within .abl file simulated using test vectors file. chiplevel functional simulation, must have version PSDsoft that includes PSDsilosIII simulation software. simulator that comes with PSDabel, take following steps:
Click Options menu select ABEL Compiler Options. Once "ABEL Compiler Options" dialog appears, click "Simulator Options" tab, window shown: under "Format", choose Table format. Ensure that X-value Z-value selected their respective boxes, that Brief trace selected "Trace" box. "Register" box, select Register powerup make sure that "Use .TMV file" checked. Click button save your changes.
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select Simulate Results View menu, PSDabel will automatically start simulation process, display simulation results based logic equations test vectors .abl file. Note: ABEL file four lines that should commented ABEL simulation only. these lines commented out, will message that vectors passed ABEL simulation instead display below. lines that need commented highlighted "CPLD equations" section. decide edit ABEL file, wish PSDSilosIII simulation later, must un-comment lines.
Your simulation results should look like screen capture below. (See above note.)
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PSDsoft Configuration
PSD813F programmable interface able interface directly many microcontrollers. Using Configuration, specify interface have chosen your design. also configure functions specific device using. This tutorial design based Intel 80C31 microcontroller, which 8-bit multiplexed with /RD, /WR, /PSEN control signals, active-high level address latch enable (ALE). perform configuration, take following steps:
Pull down PSDsoft menu main PSDsoft window choose Configuration, click "Configuration" button, click "Device Config" "PSDsoft Design Flow" window.
dialog opens titled "PSD Configuration". Make sure "MCU Configuration" selected. configuration shown: Ensure 8-Bit selected under "Data Width" selected under "Address/Data Mode" High selected under "Address Latch/Strobe Setup" "Enable Chip-Select Input (/CSI)" checked /WR, /RD, /PSEN selected under "Control Setting" Data Space selected under "Flash" Program Space checked under "EEPROM". This arrangement program data space allows boot from EEPROM program space download Flash memory data space needed. Afterwards, override this arrangement example, wanted move Flash memory program space. This done writing register.
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Click "Other Configuration" tab, ensure that Enable Standby Voltage Input (PC2) checked under "Standby Voltage", Edge selected under "Mode Loading MicroCell MCU", other boxes unchecked.
Click "JTAG Configuration" ensure that none boxes checked because checking boxes would enable JTAG port operational 100% time. Since this tutorial multiplexing JTAG pins with other signal functions, desired that JTAG functions only operational when JEN/ signal active (see Figure schematic). Enter value `ABCDEF12' "User Code" below. This value will programmed into your device. User Code value wish (e.g. identify product software revisions, serial numbers, etc.). eight characters entered.
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Click "Sector Protection" tab, ensure that none boxes checked. appropriate sector should only checked desired that selected sector write protected. These bits changed later through JTAG port device programmer.
When finished with configuration settings, click button, which saves configuration. PSD813F configuration completed.
ever wish view configuration file, first ensure Configuration Mode. (See Step this section.) Next, pull down View menu select Configuration Report. configuration report shown below. print configuration report, select File->Print.
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Fitter Fitting Address Translation
Fitter consists Fitter Address Translator. Fitter accepts input from PSDabel Configuration, synthesizes user logic configuration, fits design PSD813F silicon. Address Translator process allows user firmware from cross-compiler Intel S-Record format) into memory blocks within PSD. result, firmware merged with logic configuration definition PSD. combined output Fitter Address Translator tutor8xx.obj file. 5.4.1 Fitting Design
input files Fitter are: tutor8xx.tt2PLA file generated PSDabel. tutor8xx.glcPSD813F configuration file generated Configuration. output files generated Fitter tutor8xx.fobPLD fusemap PSD813F configuration file. tutor8xx.afuGenerated PSDSilosIII. tutor8xx.pfuGenerated PSDSilosIII. tutor8xx.objObject file (PLD Configuration portion only). tutor8xx.frpFitter report file. Design
Click Options Menu, select "Fitter Options."
tutorial, choose Keep Current under "Pin Assignment", ensure that "Enable Product Term Expansion" "Perform Register Synthesis" boxes checked, shown. Click save Fitter options.
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This
Pull down PSDsoft menu choose Fitter. Then, pull down Fitter menu choose Fitting.
This
click "Fitter" then "Fit" button tool bar.
This
click "Logic Synthesis Fitting" design flow Fitter automatically runs.
Fitter appends files: file (PSDsoft.plg) error file (tutor8xx.err). Check file possible errors. there errors present (there shouldn't didn't modify tutor8xx.abl file), skip Step fitting successful, have view tutor8xx.eq2 file PSDabel which logic function caused fitting problem modify tutor8xx.abl file accordingly. view optimized equation file (tutor8xx.eq2), step "Compiling Tutor Design" section (5.2.1). Recompile modified tutor8xx.abl file. Repeat Steps through until successful been found. Then, re-enter Fitter program, proceed Step Examine Fitter Report File pulling down VIEW menu selecting Fitter Report. report file shows results fitting process, assignment PSD813F1. want certain fitting other than generated, return tutor8xx.abl file change desired signal assignments.
also view Memory Report (tutor8xx.map) selecting View>Memory Report. contains information DPLD will interpret addresses from MCU, shows memory internal memory blocks relevant external signals. This information based entirly design (.abl) file summarized your convenience.
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Before cover Address Translator, should aware PSDsoft feature unique Flash devices-automatic code generation. 5.4.2 Generating code
PSDsoft generate ANSI code functions headers controlling PSD813F. This optional step; however, will save time implementing low-level driver function header files. functions headers ANSI-C compatible. files that generated should edited suit your application, then compiled linked with rest your application code using cross-compiler linker. functions headers that generated PSDsoft include following operations: Flash memory program erase algorithms EEPROM program algorithms control definition Memory power management Others coming soon. Although code generation performed anytime after project opened, recommend done after you've successfully your design. Once successful achieved, functions configurations defined, code tailored accordingly. source programming files implement function this tutorial have been provided; however, since this tutorial meant cover aspects PSD813F design, cover would code generation utility your project. Take following steps generate code:
Pull down Tools menu PSDsoft window choose Generate Code., shown. Alternately, click Code Gen" button Design Flow window.
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Code Generation" dialog should appear:
"Functions/Headers" dialog following sections:
Device InfoPSD family part number current project. These values cannot changed unless this project closed different opened. HeaderSpecify folder that would like place header files (.h) generated PSDsoft clicking upper Browse. button. Typically, folder your cross-compiler environment chosen. cannot change name headers file(s) this point since these header files referenced name within other header files functions that also generated PSDsoft. Once headers functions copied their designated folders, edit header file names wish, long change their names respective `#include' statements. FunctionsSpecify folder which would like place function file (.c) clicking upper Browse. button. Typically, folder your cross-compiler environment chosen. This file will contain functions specify next section. Code SelectionSelect categories code functions that would like integrate into your application program. Under "PSD Category" major functional groups that supported with code device that used this project. Under Code Coverage" brief list individual functions that available within each category. select more than category, hold `Ctrl' while making selections with left mouse button. Note: even more than category selected, only file generated because functions appended within same file. Description-Offers description functions that generated selected Code Selection" box. Note: double-click function within Description box, code that will generated shown idea what will appear sample file. After have made your selection, click Apply generate code. this example, three files will written your folder(s), which are: psd813F1.cANSI-C source selected functions psd813F1.hANSI-C header file define particular registers map813F1.hANSI-C header file define locations system memory elements (Flash, EEPROM, registers, etc.).
Note: file psd813F1.h contains define statements each individual function within PSD813F1.c file. Later, edit psd813F1.h, simply remove comment delimiters (//) from define statement function that would like compiled with rest your source code.
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Click "Coded Examples" dialog box.
This sheet contains several examples that basis building your code application. These complete projects (main, functions, headers) targeted toward particular MCU. copy these files some folder browse them ideas, paste sections from examples into your crosscompiler environment. There three sections:
ExampleSpecify folder that would like place example project files generated PSDsoft clicking Browse. button selecting folder. Example SelectionThere several areas which generate code. Each category implements high-level system function, such memory paging UART downloads Flash memory. Description-Describes each coded examples "Example Section"
Once code generated PSDsoft integrated into your application successfully compiled linked your cross-compiler, ready address translation. Choose desired example click Apply each example that want generated. Click when have finished making your selections.
5.4.3
Performing Address Translation
Address Translator combines tutor8xx.fob file with firmware file(s) generated your choice cross-compilers. Address Translator will append tutor8xx.obj file that downloaded programmer compatible with PSD813F. NOTE: addresses within generated tutor8xx.obj file special "direct" addresses that meaningful programming device. They "system" addresses that would use, that DPLD decodes. That what meant `Address Translate'. translation "system" addresses that compiler/linker know about "direct" addresses that device programmer knows about.
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perform address translation, take following steps:
Pull down PSDsoft menu, choose Fitter. Then, pull down Fitter menu choose Address Translate click "Address Translate" button tool bar.
select "MCU Code Mapping" design flow.
will following message upon starting Address Translate:
This warning reminder ensure that take paging into account when entering start/stop addresses file names. Click "Address Translate" dialog appears. Address Translation dialog following sections: Memory Select NameName memory segment that will selected when associated equation true. Memory Select EquationsEach cell shows equation appropriate memory segment. These optimized equations from PSDabel file. They displayed convenience, cannot modified this window. File Address StartStarting system address from compiler/linker that will mapped memory segment. File Address StopEnding system address from compiler/linker that will mapped memory segment. File NameMCU firmware file that generated your Compiler/Linker. Record TypeThe supported formats Intel Motorola S-Record. Mapping ModeTwo modes mapping supported, direct relative. more information, consult PSDsoft User Manual.
Notice that PSDsoft attempted fill File Start File Stop Addresses based your PSDabel equations. However, paging used this tutorial), these file addresses must
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handled carefully since PSDsoft does know your cross-compiler linker handles paging. progress, this process should become clear.
Type file names your linker output appropriate places. this example, five files used. (See Appendix information system memory these files relate.) Four five files programmed into Flash memory different pages. remaining file programmed into boot area EEPROM. four Flash files page_0.hex, page_1.hex, page_2.hex, common.hex. file EEPROM boot.hex. Each these files contain Kbytes code. Enter File Start Addresses, File Stop Addresses, File Names according table below:
Memory Select
EES0 EES1 EES2 EES3
File Start Address
0000 4000 8000 C000 8000 C000 8000 C000 0000 2000
File Stop Address
3FFF 7FFF BFFF FFFF BFFF FFFF BFFF FFFF 1FFF 3FFF
File Name
Common.hex Common.hex Page_0.hex Page_0.hex Page_1.hex Page_1.hex Page_2.hex Page_2.hex boot.hex boot.hex
this design, different file name used each several sections code Flash memory because address space overlap segments. This file scheme used because, even though these sections code physically reside different memory pages, some linkers will place them overlapping absolute address space. method depends your linker. Alternatively, single file name across many memory chip selects your linker automatically appends extra address bits that represent your paging scheme. would then, example, enter 18-bit addresses accompany single file name (which passed Address Translate utility), instead 16-bit addresses accompany several file names. NOTE: Optionally, specify only EEPROM contents programmed device programmer. desired load system code into Flash memory while in-system, device programmer. this case, only information EES0 EES1 should entered Address Translate utility.
Ensure that Direct Mapping selected "Mapping Mode" box. Select Intel Record "Record Type" box. Click perform address translation. errors indicated, then tutor8xx.obj will appended.
your copy PSDsoft includes PSDsilosIII simulator, should simulate verify your design before programming PSD813F. Refer next section simulate tutorial design.
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PSD813F Chip Simulation
PSDsilosIII WSI's version SIMUCAD's SILOSIII simulator software. provides chiplevel simulation design verification using Verilog Hardware Description Language (Verilog-HDL). Appendix lists stimulus file (tutor8xx.stl) this tutorial. Many internal nodes PSD813F available tracing. Descriptions signals that traced simulator listed Appendix PSDsoft generates input files required simulator. file that must created stimulus file (.stl). stimulus file, same names used your PSDabel file, predefined ones Appendix 5.5.1 PSDsoft.run File
files generated PSDsoft simulation process PSDsoft.run, listed Figure below. command batch file used PSDsilosIII. additional information PSDsilosIII commands (commands starting with refer PSDsilosIII's on-line help. Figure PSDsoft.run File
!Reset !file .sav Tutor8xx !control .ext `timescale 1ns/0.1ns !lib d:\psdsoft\psd8.v `include "tutor8xx.top" `include "tutor8xx.stl" endmodule
Let's analyze PSDsoft.run file: !Reset all-tells compiler reset input signals their default state. !file .sav Tutor8xx-tells compiler project name "Tutor8xx." `timescale 1ns/0.1ns-compiler directive defining delay values modul. unit measurement times delays precision which delays rounded off. !lib d:\psdsoft\psd8.v-specifies library file used. There important thing note about included library file: looks other files automatically generated PSDsoft from fusemap file that have .afu .pfu extension. They allow simulation logic defined .abl file stimulus file. `include-compiler directive that allows entire contents Verilog source file included another file (PSDsoft.run this case). Tutor8xx.top generated PSDsoft based PSDabel file, allows signal names within PSDabel file. There also parameter definitions high impedance state signals through Z32) .top file. tutor8xx.stl file user-created stimulus file. (See Appendix "endmodule" statement last statement PSDsoft.run file. there because complements "module WSIdesign" statement .top file.
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5.5.2
Running Logic Simulator
simulator, take following steps:
Review stimulus file (tutor8xx.stl) listed Appendix Pull down PSDsoft menu main PSDsoft window select Simulator click "simulator" button tool bar. This open tutor8xx.stl stimulus file editing within PSDsoft.
tutor8xx.stl file automatically opened PSDsoft, shown.
this point, could edit stimulus file, since have complete stimulus file, click LogicSim invoke PSDsilosIII simulator.
Note: directly PSDsilos simulator, click "Logic Sim" design flow.
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following events happen automatically result clicking LogicSim button: PSDsilosIII simulator automatically starts simulator automatically loads project tutor8xx.spj, PSDsoft.run, window displaying tutor8xx.stl file, shown.
Click "Go" button, which automatically opens "Output" window (shown below) viewing results simulation:
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5.5.3
Running Analyzer
that logic simulation complete, results displayed with PSDsilosIII Data Analyzer performing following steps:
Pull down Window menu select Open Data Analyzer, press click appropriate button tool bar.
SilosIII Data Analyzer window appears with simulation results displayed screen. Note: Your screen will look different. tutorial Data Analyzer Explorer under Help->Contents rearrange group signals.
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5.5.4
Working With Explorer
Explorer SilosIII used conjunction with Data Analyzer trace signals.
open explorer, ensure that have simulated design following steps "Running Logic Simulator" section (5.5.2). Next, click Window->Open Explorer menu selection Explorer button Explorer window will appear. Explorer shows viewable signals.
Signals added Data Analyzer window using Explorer holding `CTRL' button down, clicking signals that want Data Analyzer window. Once have chosen desired signals, right-click signals, select Signals Analyzer. Next, click anywhere Data Analyzer window, signals added will appear bottom window.
more information Explorer Data Analyzer, on-line help PSDsilosIII User Manual. Also, refer this manual information PSDsilosIII Watch Window, which covered because beyond scope this tutorial.
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Programming PSD813F
Programming PSD813F using PSDsoft accomplished ways: using parallel programmer called PSDpro serial programmer called Flashlink. Section 5.6.1 dedicated PSDpro, section 5.6.2 Flashlink. Either interface perform following operations: 5.6.1 Blank Testcheck device blank. Uploadupload contents device. Programprogram device with .obj file. Verifyverify programmed device against .obj file buffer. Erasecompletely erase device. PSDpro
have PSDpro, should read this subsection. only have Flashlink cable, proceed next subsection. First, let's start programming interface software within PSDsoft:
Pull down PSDsoft menu main PSDsoft window choose Programmer, click appropriate button tool bar, click "Device Prog" design flow. these actions will open tutor8xx.obj file, shown below.
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When object file opened, view contents Flash EEPROM, fusemap, configuration bits (ACR). Note: don't have your PSDpro properly connected your parallel port, have your port correctly (either Windows BIOS), this error upon entering program:
correct this problem, refer your computer hardware user manual user manual Windows Windows have your PSDpro properly connected parallel port, should power light come upon entering Parallel Programming software. your green "good" light skip programming portion this section. power light green "good" light not, take following steps PSDpro"
Ensure that your PSDpro connected your PC's parallel ports, select configure going Options menu Programmer environment select Hardware Setup.
Once "PSD Programmer Hardware Setup" dialog appears, under "Hardware Section:", select PSDpro. Next, will that Auto Select option becomes active. This means that PSDsoft will automatically detect which parallel port your PSDpro connected Just click PSDpro will detected configured connections good. should that green "good" self-test failure like shown above, there most likely problem with your parallel port. Getting parallel port working correctly beyond scope this document.
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further, must have your PSDpro working properly, PSD813F device ready programming. Assuming this case, take following steps program device using PSDpro programmer:
Pull down Functions menu select Program click Program button tool that's available when Programmer invoked.
"PSD Programmer Program Confirmation" dialog appears, which enables user program Flash, EEPROM PLD/ACR (PSD Configuration) regions device. Select "All", shown. choose enable Software Data Protect (SDP) EEPROM. doing will have "unlock" EEPROM (just like Flash) before writing erasing. Devices shipped from factory with disabled. PSD813F Family Data sheet details. Place device into programmer using correct orientation, snap down device carrier. Then, click button. programming takes place, PSDpro programmer checks each location after programmed make sure matches .obj file contents. particular location cannot programmed properly, error message will appear. this occurs, must start over program fully erased functional part.
Note: your device blank, will following message similar one) after click blank part proceed desired.
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Once programming operation completed, assuming there were errors, should message similar following. used tutor8xx.obj file, should same checksum numbers.) Congratulations, have successfully programmed part. ready proceed with your design.
5.6.2
JTAG-FlashLink
intend JTAG program your PSD, should read this section. Note: before proceed, ensure that have latest version PSDsoft visiting site- http://waferscale.com. first part deals with setting your FlashLink cable. have already confirmed that your FlashLink cable working properly, skip second part that deals with programming process. Before proceed, should start JTAG Programmer under PSDsoft. pull down PSDsoft menu choose JTAG Programming, click "JTAG" button toolbar, click "JTAG Prog" design flow.
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should following screen. Figure 5-JTAG Chain Setup Dialog
Setting Testing your FlashLink Cable. Ensure that FlashLink cable installed your PC's parallel ports (i.e. LPT1). Note: must also ensure that parallel port that FlashLink connected correctly your BIOS Windows (95/98 NT). Consult user manuals that came with your machine your operating system ensure that your parallel port setup correctly. setup FlashLink cable, take following steps:
Click Setup button bottom "JTAG Chain Setup" dialog box. This brings "Hardware Setting" dialog box, shown. Since FlashLink currently only device, this will shown "Hardware Selection:" box. "Parallel Port" box, "Auto Select" first. Auto Select doesn't work, selecting port that have Flashlink connected
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will perform Loopback Test. click Loop Test button. "FlashLink Loop Test" information screen will Follow instructions Test, click
this message, your parallel port working properly. Click next section.
this message, FlashLink receiving information from parallel port. changing your selection "Hardware Setting" dialog under "Parallel Port:" whichever parallel port number have your FlashLink cable connected, rerun test above. still experiencing problems, will need your parallel port working properly before continue, which beyond scope this document.
this message, ensure that Ground wires connected correct pins that pins correct voltage potential. should have between low-power parts (parts with suffix) between low-power parts with suffix. have correct voltage, should this message.
Once have determined that your Parallel port working properly (because your FlashLink Loop Test passed), ready attempt program your part. next part covers program part using your FlashLink cable.
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Programming PSD813F JTAG using FlashLink Cable This part section covers program your PSD813F JTAG using FlashLink cable. This part assumes have tested your FlashLink Cable passed Loopback Test previous part. Note: encounter problems during programming have passed Loopback Test described above, your problem several conditions, including: don't have PSDsoft version 5.07 later. this case, site-http://waferscale.com-and download latest version. Your PSD813F part been damaged. easily check this have another part program. same error, chances have problem with your JTAG connection (covered last). have previously programmed PSD813F with .obj file that disables JTAG pins. must either erase using PSDpro, must enalbe pins run-time using JTAG register. Refer PSD813F family data sheet details. having problem with your JTAG connection. This problem beyond scope this document. Refer Application Note more information JTAG. can't solve your problems with this Application Note Technical Support section site email Applications Engineer from there. should back "JTAG Chain Setup" dialog (Figure JTAG Programming software should have automatically loaded tutor8xx.jcf file. create your JTAG chain file, subsection "Creating JTAG Chain File." program your PSD813F using FlashLink cable, take following steps:
Right-click line "Chain Information" select Properties shown.
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should "JTAG Chain Setup Properties." Ensure that "Set Pins/Flow Control" selected, window with following selections based Figure this tutorial (proper selections shown right): Under "Flow Control", select Option "Set Pins" box, ports follows: Port pins "OUTPUT (CMOS)" Port pins "INPUT (HI-Z)", pins "OUTPUT CMOS)" Port change "TSTAT (CMOS)", "TERR (CMOS)". Leave rest pins Port pins "INPUT (HI-Z)", "OUTPUT HIGH (CMOS)" Click Apply button made changes. This saves changes have made far.
Click "JTAG Attributes" tab. will screen shown. using tutor8xx.jcf file, there nothing here. using your JTAG Chain File, read following note appropriate section below.
Note: "Device Name", "Instruction Register Length:", "JTAG Device ID:" grayed because this information automatically entered whenever select PSD813F device. wanted enter information about non-PSD device that would included your chain, here place another device, would need enter valid information "JTAG Attributes" section. Also, note that select "JTAG Device ID:" box, PSDsoft will verify JTAG before programming erasing device.
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Click "User Code" tab. enter value "User Code" box, value will compared with User Code already programmed into device before JTAG operation occurs (e.g. Erase, Program, etc.). leave this area blank, comparison will done. Enter ABCDEF12 "User Code" box. Then press Apply (which grays "Apply" button out), finally press
Now, should back "JTAG Chain Setup" window (Figure Rightclick same line step only this time, choose Program.
should "Operation: Program" dialog box. Ensure that checked "Regions:" section.
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Your "JTAG Chain Setup" should have following look. Select will programmed with information tutor8xx.obj file.
Note: during program operation, PSDsoft holds reset (Rst) line FlashLink cable low. Your should connected this Reset line that does execute code during JTAG programming operation. signal output from FlashLink cable opencollector pulled cable. Once finished with Program operation, PSDsoft releases Reset line FlashLink cable. Congratulations, have programmed PSD813F part JTAG using FlashLink cable! ready proceed with your design. sure read next subsection unsure JTAG chain file.
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5.6.2.1
Setting JTAG Chain
following rules apply setting JTAG chain:
JTAG chain more devices must defined. JTAG compatible devices that connected JTAG bus, including PSD813F
non-PSD devices from other vendors compose JTAG chain.
Non-PSD devices that part JTAG chain will placed bypass mode
automatically.
length instruction register, along with name device must entered
each non-PSD device. future versions PSDsoft, will able automatically load this information with BSDL file.)
Before programming device(s), user must have valid .obj file each
device chain. Please refer document titled JTAG Information PSD8xxF (Application Note information these areas: JTAG Spec Compliance Programming Support Program/Erase Flow Control SVF/BSDL file information Enhanced functions Multiplexed JTAG functions Dedicated JTAG functions JTAG connector JTAG Chaining Electrical Considerations.
Now, let's step through sample JTAG chain setup, create JTAG chain file (.jcf). following steps would take:
currently using JTAG Programming software, exit clicking button upper right-hand corner "JTAG Chain Setup" dialog box.
Erase tutor8xx.jcf file from directory. Start JTAG Programming program PSDsoft. (See beginning Section 5.7.2.)
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should "JTAG Chain Setup" dialog that "blank," shown below. "Chain Information" click Browse. button.
"Open" window pops tutor8xx.obj file click Open.
Select
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Your "JTAG Chain Setup" window should look like this:
Note: device name (PSD813F1 this case) does automatically appear "Device Name" window, click down arrow next "Device Name", select PSD813F1.
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Click button. Your "JTAG Chain Setup" window should look like this:
Save your work JTAG Chain File future use. click Save button. This action brings "Save dialog box. Type tutor8xx "File name:" box, click Save. file tutor8xx.jcf will created. This identical file were working with before.
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Now, "JTAG Chain Setup" window should look like this:
Note: need load this .jcf file future, will have click Browse. button, which would bring "Open" dialog box. Choose tutor8xx.jcf file, click Open.
wanted more devices JTAG chain file, would repeat Steps through
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PSD813F
PSD813F programmed in-system, with without participation from MCU. with MCU, Appendix UART download information considerations. without participation, section 5.6.2 Application Note JTAG Information PSD8XXF FlashLink JTAG programming within PSDsoft environment.
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Appendix AABEL Design FileTutor8xx.abl
module Tutor8xx title '8xx Tutorial Design File'; Designed Harris Mark Rootz Design date: 6-16-98 Description: This shows logic implementation sample design Tutorial. design highlights following functionality PSD8xx: Effective efficient Input Output Micro<->Cells pins while underlying Micro<->Cell being used other functionality. WSIPSD PROPERTY statement output demultiplexed address bits, define Input Micro<->Cells/Output Micro<->Cells. Multiplexing JTAG pins with other I/O. logically interface 80C31 MCU, RTC, circuit. Revision: Date: 9-21-98 Convention: used throughout file indicate active signals. Note that used with reserved signal names below.
"************************** Interface signal declarations ************************** reserved signal names automatically assigned appropriate following inputs from pin; "CNTL0 Input:(pin 47)- write strobe pin; "CNTL1 Input:(pin 50)- read strobe psen pin; "CNTL2 Input:(pin 49)- program store enable pin; "PD0 Input:(pin 10)- address latch enable reset pin; "Input:(pin 48)- system reset a15.a0 pin; "Input:(pins 46.39,37.30)- demuxed address
"**************************
Port declaration
**************************
Port Control outputs mode outputs Control0.Control2 "Some generic control signals Assign latched/demultiplexed address Port pins pa0. WSIPSD PROPERTY 'Address_Out Aout[4:0]:Addr_Out[4:0]';
Port PGA_Din2.PGA_Din0
"Data bits used program "Implemented with mode Measured_Level3.Measured_Level0 istype 'reg'; "Upper bits converter (ADC) WSIPSD PROPERTY 'DataBus_IMC D[7:4]:Measured_Level[3:0] PortB'; Port Note that pins pc0, pc1, pc5-6 multiplexed output/JTAG signals. pc3, pc4, JTAG signals that multiplexed. Ensure that under "Global Configuration" with "JTAG Configuration" selected that none boxes enabling various JTAG signals certain pins checked because device will expect only valid JTAG signals these pins, multiplexing done under these circumstances. (pin used VSTBY (set global configuration) Intrn "Interrupt when gain needs changed/JTAG Start_Conv "Start Conversion signal ADC/JTAG Trim "The gain high needs decremented/JTAG TSTAT Boost "There enough gain-increment it/JTAG TERRn JCEn "JTAG chip enable signal used demultiplex Port output JTAG
Port (pin assigned above signal from microcontroller. external chip selects that generated decoding address should placed Port when possible save many resources possible. RTCcsn "Real Time Clock (RTC) chip select/JTAG clkin pin; "Port (pin System clock
Output Micro<->Cell assignments WSIPSD PROPERTY 'DataBus_OMC D[7:4]:Desired_Level[3:0] MCELLAB'; WSIPSD PROPERTY 'DataBus_OMC D7:begin_cycle MCELLBC'; "************************** mxord3 meqd node; node; Internal node declarations **************************
"This signal needed save product terms "True when measured signal equals desired signal level
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begin_cycle node istype 'reg'; "This signal takes state machine idle STATE1.STATE0 node istype 'reg'; "State machine bits Desired_Level3.Desired_Level0 node istype 'reg'; "The desired gain level fs7.fs0 node; "Main Flash memory segments ees3.ees0 node; "EEPROM memory segments Reserved node names node; "Select SRAM memory space csiop node; "Control register jtagsel node 102; "This JTAG enable product term. "the JTAG port signals. pgr1.pgr0 node; "Internal Page Register bits
used enable
following page register definitions example manipulate memory facilitate ISP. This scheme explained Appendix Application note
swap
node 117;
This page register (pgr7) will used swapping memory segments after firmware download from 8031 UART port completed. When swap secondary occupies boot area ISP, swap primary occupies boot area.
enable_data_half node 116;
This page register (pgr6) will used manipulate EEPROM. this divide EEPROM into equal sections, boot general data. When this bit=0, boot section active. When this data section active.
"**************************
DEFINITIONS
**************************
DLEVEL "Desired gain level MLEVEL "Measured gain level latched IMCs STATE_MACHINE [STATE1.STATE0]; .x.; "Don't care symbol .c.; "Clock symbol page [pgr1,pgr0]; address [a15.a0]; "De-muxed microcontroller address signals
EQUATIONS "************************** Generate active high chip PSD813FX devices. ((address ^h8000) ((address ^h0000) (address ^h4000) (address ^h8000) (address ^hC000) (address ^h8000) (address ^hC000) (address ^h8000) (address ^hC000) DPLD equations selects main Flash segments. (address (address (address (address (address (address (address (address (address ^hBFFF) ^h3FFF) ^h7FFF) ^hBFFF) ^hFFFF) ^hBFFF) ^hFFFF) ^hBFFF) ^hFFFF) (page (page (page (page (page (page (page (page (page ************************** Each segment bytes
!swap) swap);
Generate active high chip selects EEPROM PSD813F1 devices. ees0 ((address ^h0000) (address ^h1FFF) ((address ^h8000) (address ^h9FFF) ees1 ((address ^h2000) (address ^h3FFF) ((address ^hA000) (address ^hBFFF) ees2 (address ^hC000) (address ^hDFFF) ees3 (address ^hE000) (address ^hFFFF)
segments. (page (page (page (page (page (page
Each segment bytes !swap) swap !enable_data_half); !swap) swap !enable_data_half); swap enable_data_half; swap enable_data_half;
//Generate active high chip select SRAM bytes). (address ^h0100) (address ^h08FF) (page
Generate active high chip select control registers. contiguous bytes must decoded PSD8xx devices. csiop (address ^h0900) (address ^h09FF) (page
Enable JTAG port when JTAG Chip Enable (JCEn) Signal active jtagsel !JCEn;
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"**************************
CPLD equations
**************************
IMPORTANT NOTE: Comment these next four equations ABEL simulation only. PSDsilosIII Simulator requires equations (and they functionally correct). problem that presets (loads) clears these registers, value registered through input. However, ABEL simulator does reconize "dot" extentions these would normally through equations). basic functionality still properly tested, actually implemented hardware slightly different. intend ABEL Simulator, comment following four lines that test vectors file will work properly. DLEVEL.ck DLEVEL begin_cycle.ck begin_cycle mxord3 Measured_Level3 !Desired_Level3; Trim gain when Measured signal level greater than desired signal level. Trim MLEVEL DLEVEL Trim (Measured_Level3 !Desired_Level3) ((Measured_Level2 !Desired_Level2) mxord3) ((Measured_Level1 !Desired_Level1) mxord3 (Measured_Level2 !Desired_Level2)) ((Measured_Level0 !Desired_Level0) mxord3 (Measured_Level2 !Desired_Level2) (Measured_Level1 !Desired_Level1)); Boost gain when Measured signal level less than desired one. meqd (MLEVEL DLEVEL); Boost !meqd !Trim; Generate chip select !RTCcsn ((address ^h0a00) (address ^h0aff)); Loading various registers MLEVEL.ld !clkin; State machine which controls conversion start ADC, interrupt MCU, strobing IMCs STATE_MACHINE.ck clkin; STATE_MACHINE.re !reset; state_diagram STATE_MACHINE; state Start_Conv Intrn (begin_cycle then else state Start_Conv goto state Start_Conv goto state !Intrn Trim Boost; goto "Interrupt when Measured equal Desired
Test_Vectors Test state machine, trim, ([clkin, reset, begin_cycle, MLEVEL, [Start_Conv, Intrn, STATE1, STATE0, ^h3, ^h4, ^h5, ^h5, ^h5, ^h4, ^h4,
boost signals DLEVEL] Trim, Boost]) "system reset "system reset
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Appendix BStimulus FileTutor8xx.stl
tutor8xx.stl file consists four sections: Parameter Definitions: each PSD813F control registers address (offset from CSIOP base address). parameters make stimulus file easier read. User-defined tasks: used define implement microcontroller cycles. each task, timing control signals address/data should follow that microcontroller, don't have exact, just scale. Simulator will simulate cycle every time read, write, psen task called. Signal Initialization: must specify initial logic level input signals before simulation. Note: output signals that want simulate should initialized high impedance state. stimulus inputs: here stimulus inputs needed perform read/write cycles access Flash, EEPROM, SRAM ports. Inputs also generated exercise CPLD functions.
//Title: //Function: //Designed //Design Date: //Description: tutor8xx.stl Simulation file PSD8xx Tutorial Harris 6-23-98 This file intended used PSDsilosIII environment stimulus file PSD8xx Tutorial. idea this file show Verilog-HDL language works, rather format .stl file, applies this tutorial example. main parts this file are: Parameter declarations which make file more readable Read, write "PSEN/" cycle tasks 80C31 area where user wish file order test more functions actual stimulus design
Parameters declarations address offsets CSIOP address space //Port parameter parameter parameter parameter //Port parameter parameter parameter parameter
Port_A_Dir_Reg='h0906, Port_A_Cntl_Reg ='h0902; Port_A_Dout_Reg='h0904, Port_A_Din_Reg ='h0900; Port_A_IMC='h090A, Port_A_Drive_Sel 'h0908; Port_A_En_Out='h090C;
Port_B_Dir_Reg='h0907, Port_B_Cntl_Reg ='h0903; Port_B_Dout_Reg='h0905, Port_B_Din_Reg ='h0901; Port_B_IMC='h090B, Port_B_Drive_Sel 'h0909; Port_B_En_Out='h090D;
//Port parameter Port_C_Dir_Reg='h0914, Port_C_En_Out ='h091A; parameter Port_C_Dout_Reg='h0912, Port_C_Din_Reg ='h0910; parameter Port_C_IMC='h0918, Port_C_Drive_Sel 'h0916; //Port parameter Port_D_Dir_Reg='h0915, Port_D_Drive_Sel ='h0917; parameter Port_D_Dout_Reg='h0913, Port_D_Din_Reg ='h0911; parameter Port_D_En_Out='h091B; //Port OMCs
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parameter Port_AB_OMC='h0920, //Port OMCs parameter Port_BC_OMC='h0921, //Other control registers parameter FLASH_Protect='h09C0, parameter PMMR0_Reg='h09B0, parameter PMMR2_Reg='h09B4, parameter Page_Reg='h09E0,
Port_AB_OMC_Mask 'h0922;
Port_BC_OMC_Mask 'h0923;
EEPROM_Protect 'h09C2; PMMR1_Reg ='h09B2; JTAG_En 'h09C4; VM_Reg ='h09E2;
Defining tasks simulate 80C31 cycles (read, write psen cycles). Note that cycles shortened simulation purposes, functionality remains same. //The "write task" implements 80C31 write cycle task write; input [15:0] addr_bus; input [7:0] data_in; begin adio addr_bus; adio[7:0] data_in; #100 adio[7:0] endtask
//Latch address lines //Read valid address (adio defined .top file) //Ale inactive //Write operation //Write pulse //Write ends //Z16 defined .top file
//The "read task" implements task read; input [15:0] addr_bus; begin adio addr_bus; adio[7:0] #100 endtask
80C31 read cycle timing
//Latch address lines //Read valid address //Ale inactive //Float address defined .top) //Read pulse //Read ends
//The "psen task" implements task psen; input [15:0] addr_bus; begin adio addr_bus; adio[7:0] psen #100 psen endtask
80C31 psen program fetch cycle
//Latch address lines //Set-up right address //Ale inactive //Float address //Read pulse //Read ends
Define some busses here make program easier read. //adrout latched address output Port [4:0] adrout; Addr_Out4, Addr_Out3,Addr_Out2, Addr_Out1, Addr_Out0; assign {Addr_Out4, Addr_Out3, Addr_Out2, Addr_Out1, Addr_Out0} adrout;
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[3:0] measured_value; Measured_Level3, Measured_Level2, Measured_Level1, Measured_Level0; assign {Measured_Level3, Measured_Level2, Measured_Level1, Measured_Level0} measured_value; [3:0] desired_value; Desired_Level3, Desired_Level2, Desired_Level1, Desired_Level0; assign {Desired_Level3, Desired_Level2, Desired_Level1, Desired_Level0} desired_value; [3:0] PGA_data; PGA_Din3, PGA_Din2, PGA_Din1, PGA_Din0; assign {PGA_Din3, PGA_Din2, PGA_Din1, PGA_Din0} PGA_data; [2:0] cntrl; Control2, Control1, Control0; assign {Control2, Control1, Control0} cntrl;
Stimulus starting point Initialize first. Then proceed with rest simulation. initial begin //Initialize signals first reset adio 'h0000; psen adrout measured_value 'h0; desired_value 'h0; PGA_data=Z4; cntrl Intrn Start_Conv Trim Boost JCEn #100 reset Take reset after 100ns
//We ready some configuration //Port configuration //Configure Port pins output latched address, rest //of port will output control information mode. //Writing "1F" Port control register enables latched address output //pins pa0, rest port output I/O. write(Port_A_Cntl_Reg, 'h1f); //Writing "FF" Port direction register sets Port pins outputs. write(Port_A_Dir_Reg,'hff); //Port configuration //Since there latched address output Port control register //defaults mode output, only direction register needs setup. //Only pins will outputting data, rest will receiving //input write(Port_B_Dir_Reg,'h0f); //All Port output (with exception Vstby input write(Port_C_Dir_Reg,'hfb); //There only output Port (RTCcs/), direction register //setup follows: write(Port_D_Dir_Reg,'h04); //Set mask registers that only desired portion OMCs //written. Only desired value (MCELLAB[7:4]), begin (MCELLBC7) //written write(Port_AB_OMC_Mask, 'h0f); write(Port_BC_OMC_Mask, 'h7f);
//Write EEPROM segment ees0, Flash segment //then read SRAM write('h0020,'h5a); write('h5A00,'ha5); read ('h07FE); //write ees0 //write //read internal SRAM
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Wait, then initialize gain output data pins pb0. write(Port_B_Dout_Reg,'h01);
Assume small value output since gain measured_value='h3;
Load into desired value register write(Port_AB_OMC, 'h50);
Take state machine idle state generate chip select. write(Port_BC_OMC, 'h80);
Since measured value less than desired one, gain would boosted after interrupt generated cycles after start state machine). should increment gain that time. #400 write(Port_B_Dout_Reg, 'h02); $finish; initial begin Generate system clock used state machine, etc. Note time scale psdsoft.run file. clkin=0; forever #100 clkin=~clkin; //stimulus ends here
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Appendix CList PSD813F Simulation Signals
This list signals from Explorer that viewed using PSDsilosIII Data Analyzer. This list based tutor8xx.abl file, predefined signals. list will vary depending names your .abl file, most signals will same. Note: some internal PSD813F signals, will have click plus sign expand list. circle below.
above signals dragged Data Analyzer window viewing. Once there, signals made into busses. more information Explorer Data Analyzer, PSDsilosIII's on-line help, PSDsilosIII User Manual. Below table that contains viewable predefined signal names, along with brief description each. conventions used table are: represents number represents letter list above determine which letters and/or numbers apply respective signal.
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Table C1Predefined Signal Names their Descriptions Signal/Bus Name
adioh[15:8] adiol[7:0] ctrl_x data[7:0] din_x dirff_x dout_x drive_x ecsdn ee_boot_oe ee_power_down ee_protection[3:0] ee_ready_busy_N ee_sdp_disable ee_sdp_enable ee_toggle eesel_f enable_x f_protection[7:0] flash_oe flash_polling flash_ready_busy flash_toggle flsel_f jtag mask_mcab mask_mcbc mcellabn mcellabn_clk mcellabn_pr mcellabn_reg mcellabn_re mcellbcn mcellbcn_clk mcellbcn_pr mcellbcn_reg mcellbcn_re nib_xn out_mcab[7:0] out_mcbc[7:0] pxn_imc pxn_oe pgr7_0 pmmrn pseln rd_bsy sram_oe
Description
register Address/Data high byte Address/Data byte Port control register Non-multiplexed 8-bit data Port data register Port direction register Port data register Port drive register External chip select output EEPROM output enable EEPROM power down signal security EEPROM sector protection EEPROM ready/busy signal EEPROM software data protection disable EEPROM software data protection enable EEPROM toggle signal EEPROM final chip select Enable port driver Flash sector protection register (read only) Flash output enable Flash data polling Flash ready/busy signal Flash toggle Flash final chip select JTAG enable register Mask register outputs Mask register outputs Micro Cell output Output Micro Cell clock input Output Micro Cell preset input Output Micro Cell register input Output Micro Cell reset input Output Micro Cell output Output Micro Cell clock input Output Micro Cell preset input Output Micro Cell register input Output Micro Cell reset input Product term control port x[7:4] x[3:0] input Micro Output registers Micro Cell Output registers Micro Cell Port Port Input Micro Cell Port output enable product term Power down signal Page register outputs Power management mode register Port peripheral select internal ready/busy status signal SRAM output enable signal
Cell
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Appendix DDesign file EPM7064S Figure
-Title: Function: Designed Design date: Description: Tutorial-Discrete Solution Replacement programmable logic portions PSD8xx Harris 6/15/98 This design shows what chip logic would required replace programmable logic portions PSD813F1. This chip will responsible following tasks: Latching address generated 80C31 MCU. Decoding address generating internal/external chip selects. Storing control/status information internal registers. Address translation memory pageng. Interfacing controlling Receiver circuit, RTC, SRAM, EEPROM, FLASH, MCU. Interfacing JTAG-compatible port ISP. tilde used throughout this design indicate active signals. H"09E0"; H"09E2"; H"0902"; H"0920"; H"0901"; H"0921";
Convention:
CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT
PAGE_REG_ADDR VM_REG_ADDR MCU_IO_OUT_ADDR DESIRED_REG_ADDR GAIN_REG_ADDR START_SIG_ADDR
subdesign 8xxtutor following signals A/D[7.0] BIDIR; -A[15.8] INPUT; -RD~ INPUT; -WR~ INPUT; -ALE INPUT; -PSEN~ INPUT;
generated (U1): Multiplexed address (lower byte)/data Upper byte addr Read strobe Write strobe addr latch enable signal Program store enable
System-level inputs: Reset~ INPUT; System reset Clock INPUT; System clock following AGC_Interrupt~ Trim Boost signals generated (U1): OUTPUT;- Interrupt when desired measured signal levels don't match OUTPUT; True when measured level greater than desired OUTPUT; Opposite Trim
chip select output (U5): RTC_CS~ OUTPUT; This signals to/from (U7): Start_Conversn OUTPUT; Indicates when should start analog-to-digital conversion ADC_Out[3.0] INPUT; measured signal strength used gain (part PGA_Din[2.0] OUTPUT; following outputs external memories: Chip selects FLASH_CS~ OUTPUT; EEPROM_CS~ OUTPUT; SRAM_CS~ OUTPUT; Output enables FLASH_OE~ OUTPUT; EEPROM_OE~ OUTPUT; SRAM_OE~ OUTPUT; Upper address bits FLASH_A[16.14] OUTPUT; addr bits 128K FLASH segmentation EEPROM_A[14.13] OUTPUT; addr bits EEPROM segmentation Latched/demultiplexed address output Addr_Out[7.0] OUTPUT; outputs external memories Control Output mode Control[2.0] OUTPUT; VARIABLE A/D[7.0] TRI; Needed drive data output onto data
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la[7.0] page_reg[7.0] vm_reg[7.0] desired_reg[3.0] gain_reg[2.0] begin_comparrison cntrl_port_reg[2.0] addr[15.0] fs[7.0] ees[3.0] swap enable_data_half measured[3.0] desired[3.0] meqd BEGIN
LATCH;- Must demux lower byte addr DFFE; Page register DFFE; Used memory mapping combined memory space mode DFFE; Register store desired signal level (set MCU) DFFE; Register store gain level (set MCU) DFFE; takes state machine idle state (s0) DFFE; mode control register NODE; Demultiplexed addr NODE; FLASH segment enable signals NODE; EEPROM segment enable signals NODE; page register NODE; page register NODE; Output from NODE; Input from NODE; True when measured value equals desired MACHINE WITH STATES (s0, s3);
Right now, there nothing output lines A/D[] GND; Latch addr[] la[] A/D[]; la[].ena ALE; addr[7.0] la[]; addr[15.8] A[]; Addr_Out[] la[]; begin_comparrison A/D7; begin_comparrison.clk Clock; begin_comparrison.clrn Reset~; begin_comparrison.ena !WR~ (addr[] START_SIG_ADDR); desired_reg[] A/D[7.4]; desired_reg[].clk Clock; desired_reg[].clrn Reset~; desired_reg[].ena !WR~ (addr[] DESIRED_REG_ADDR); gain_reg[] A/D[2.0]; gain_reg[].clk Clock; gain_reg[].clrn Reset~; gain_reg[].ena !WR~ (addr[] GAIN_REG_ADDR); cntrl_port_reg[] A/D[2.0]; cntrl_port_reg[].clk Clock; cntrl_port_reg[].clrn Reset~; cntrl_port_reg[].ena !WR~ (addr[] MCU_IO_OUT_ADDR); page_reg[] A/D[]; page_reg[].clk Clock; page_reg[].clrn Reset~; page_reg[].ena !WR~ (addr[] PAGE_REG_ADDR); vm_reg[] A/D[]; vm_reg[].clk Clock; vm_reg[].clrn Reset~; vm_reg[].ena !WR~ (addr[] VM_REG_ADDR); measured[] ADC_Out[]; desired[] desired_reg[]; PGA_Din[] gain_reg[]; Control[] cntrl_port_reg[]; Memory Section swap page_reg7; enable_data_half page_reg6; ((addr[] H"8000") (addr[] H"BFFF") (page_reg[] !swap) ((addr[] H"0000") (addr[] H"3FFF") swap); (addr[] H"4000") (addr[] H"7FFF"); (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[] (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[] (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[] ees0 ((addr[] H"0000") (addr[] H"1FFF") !swap) ((addr[] H"8000") (addr[] H"9FFF") swap !enable_data_half); ees1 ((addr[] H"2000") (addr[] H"3FFF") !swap)
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((addr[] H"A000") (addr[] H"BFFF") ees2 (addr[] H"C000") (addr[] H"DFFF") ees3 (addr[] H"E000") (addr[] H"FFFF")
swap !enable_data_half); swap enable_data_half; swap enable_data_half;
FLASH upper EEPROM upper address encoding FLASH_A16 FLASH_A15 FLASH_A14 EEPROM_A14 ees3 EEPROM_A13 ees3 fs4; fs2; fs1; ees2; ees1;
Chip Selects Output Enables SRAM highest priority, followed EEPROM, then FLASH !FLASH_CS~ (fs0 fs7) (EEPROM_CS~ SRAM_CS~); !EEPROM_CS~ (ees0 ees1 ees2 ees3) SRAM_CS~; !SRAM_CS~ ((addr[] H"0100") (addr[] H"08FF")); !RTC_CS~ ((addr[] H"0A00") (addr[] H"0A1F")); !SRAM_OE~ !(!RD~ (!PSEN~ vm_reg0)); !EEPROM_OE~ !((!PSEN~ vm_reg1) (vm_reg3 !RD~)); !FLASH_OE~ !((!PSEN~ vm_reg2) (vm_reg4 !RD~)); Comparator Trim (measured[] desired[]); meqd (measured[] desired[]); Boost !Trim !meqd;
State Machine sm.clk Clock; sm.reset !Reset~; CASE WHEN Start_Conversn GND; AGC_Interrupt~ VCC; (begin_comparrison) THEN ELSE WHEN Start_Conversn VCC; WHEN Start_Conversn GND; WHEN !AGC_Interrupt~ Trim Boost; Interrupt when Measured equal Desired CASE; END;
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Appendix EDiscrete Solution (Figure Compared Integrated Solution (Figure
This appendix compares circuits Figures following categories: (Only major were compared.) Cost Average Current Usage Board Space Usage Time market.
Cost
PSD813F1 PLCC package purchased significantly lower price than total cost individual EEPROM, Flash, SRAM, CPLD devices.
Average Current Usage
PSD813F would typically 4.88 according calculation based "Example PSD813F Typical Power Calculation "AC/DC Parameters" section PSD813F Family Data Sheet. Now, take total average current devices discrete solution, 32.4 (with EPM7064S turbo mode). This shows that discrete solution uses 664% more current than PSD!
Board Space Usage
PSD813F1 PLCC package takes mm2. chips that make discrete solution take combined 1493 mm2. That equates 373% more board space! (All calculations based PLCC packages.) This calculation does reflect extra board space, complexity, noise associated with routing signals discrete solution.
Time Market
While specific quantities used calculation, should obvious that time market will reduced significantly many reasons. easiest visualize fact that discrete solution involves complex deal with instead just one. Also, there templates predefined routines that, when used conjunction with user-friendly PSDsoft, will help with every step your design process. Issues related concurrent memory, memory mapping, assisted simplified. Even code generated you. JTAG interface greatest benefits time savers; allows program, configure, test entire PSD, leave soldered board whole time! Last, least, there just fewer places wrong, fewer things debug when have this level integration.
Calculation based crystal input 80C31 MCU, composite input frequency PLD, product terms (based output from fitter report). rest parameters used calculation identical ones used "Example PSD813F Typical Power Calculation section PSD813F Family Data Sheet.
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Appendix FSystem Memory UART
Introduction system memory developed this tutorial take full advantage memory available PSD813F1 expand beyond Kbyte address space limitation 8031 MCU. This memory facilitates downloading firmware from host computer Flash memory using 8031 UART. 8031 boots from EEPROM, concurrently downloads Flash memory, then 8031 execution jumps from EEPROM Flash memory. After this jump, EEPROM boot area address space replaced with Flash memory special register within (the Register). After that, entire Flash memory available 8031. This system memory also allows concurrent downloading boot code into EEPROM while executing code Flash memory. This possible non-PSD systems that PROM boot code. total memory available 8031 defined this system Kbytes Flash Kbytes EEPROM boot code Kbytes EEPROM data storage Kbytes battery-backed SRAM addition bytes SRAM resident 8031) System Memory system memory shown Figures labels EESx names internal memory segments within PSD813F1 device. represents Kbyte Flash segments, EESx represents Kbyte EEPROM segments. this design, paging used because system contains more memory than 8031 address linearly. PSD813F1 facilitates paging using page register, which 8031 access. Because paging used, common memory area needed firmware routines that must accessible regardless what page executing from. This common area resides lower half each memory page program space (shown Figures through F4); should contain routines that handle initialization, interrupts, implement page switching, drive physical devices. also used keep critical data space items available times. example, this design, control registers, I/O, system SRAM stack global variables available memory page (see Figures through F4). There fundamental modes operation: boot/download mode, other normal operation. Figures through show memory during transition from boot/download mode normal operation mode.
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Figure represents memory power-on (boot). system will boot from EEPROM, then facilitate download main Flash memory needed) using 8031 UART. this point, Flash memory 8031 "data space" EEPROM 8031 "program space". This "MCU Configuration" that done step section (PSD Configuration), shown again, below. This step configuration automatically sets register 12h. Refer PSD813F Family Data Sheet information register settings.
very important note that Configuration utility sets register (located CSIOP space offset E2h) initially, that only changed after booted.
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After Flash been programmed and/or validated, Flash memory moved from 8031 data space 8031 program space writing register (while still executing EEPROM). Figure represents memory after Flash been moved program space. This intermediate step that result writing register. Next, 8031 execution jumps from EEPROM Flash. While executing from Flash, 8031 will page register that call "SWAP". Note: "SWAP" while executing from EEPROM, indeterminite results would occur. (It's like pulling from under yourself.) Now, EEPROM that booted from during power-up replaced with Flash memory that contains application vectors code, shown Figure transition between maps Figures under control 8031 setting "SWAP" inside (defined PSDabel (tutor8xx.abl) file). Again, state memory shown Figure intermediate step. NOTE: Individual bits within 8-bit page register used functions other than memory page definition. example, this tutorial, eight page register bits define four memory pages, page register bits used "SWAP" bit, described above. Finally, while executing from Flash memory, 8031 must write register move EEPROM from 8031 program space 8031 data space. this point, jump reset vector that resides location 0000h Flash segment FS0. This will finalize memory map, shown Figure Now, Kbytes Flash memory program space, with Kbytes common area Kbytes spread across three memory pages. Also, EEPROM data space accessible from memory page. Notice that EEPROM segments (EES2 EES3) appear Figure These segments general data while other EEPROM segments (EES0 EES1) comprise 8031 power-on boot code. that system memory looks like that Figure another feature becomes available. Besides mechanisms mentioned, there more memory mapping control used this tutorial design. This bit, "ENABLE_DATA_HALF", another page register used protect boot code EES0 EES1 from inadvertent writes. same time, enables other half EEPROM (EES2 EES3) accessed general data. example, update boot code EES0 EES1 with code downloaded over UART, 8031 would leave ENABLE_DATA_HALF logic zero, perform update writing EES0 EES1, then ENABLE_DATA_HALF logic one. boot code inaccessible (protected while booting), data half EEPROM accessible.
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OGRAM SPACE (PSEN\)
PAGE FFFF PAGE PAGE
DATA SPACE
PAGE PAGE FFFF
C000
C000
Execute from here
EES1
ACROSS DATA
EES0
Figure System Memory 8031-PSD813F1, boot/download POWER-UP Register 12h)
SPAC
FFFF
SPAC
FFFF
COMM
Execute
EES1
EES1
EES1
EES1
SYSTEM
EES0
EES0
EES0
EES0
Figure System 8031-PSD813F1, move Flash program space WRITE REGISTER
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Figure System Memory 8031-PSD813F1, swap boot EEPROM with Flash segment
SPAC
FFFF
SPAC
FFFF
EES1 Execute
EES1
EES1
EES1
EES0
EES0
EES0
EES0
COMM
SYSTEM
SWAP
SPAC
FFFF
SPAC
FFFF
EES3
EES2
EES1
EES0
COMM
Figure Final 8031-PSD813F1, move EEPROM data space WRITE REGISTER Code partitioning
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Now, let's look partitioning code Flash memory pages. Ultimately, will executing from Flash memory since EEPROM used boot-up this design. Let's assume that will have Kbytes program space Flash memory, shown Figure Kbytes code will reside four areas: Kbytes common area (FS0 FS1, accessible from page), Kbytes page zero (FS2 FS3), Kbytes page (FS4 FS5), Kbytes page (FS6 FS7). Keep mind that 8031 never leaves page zero while executing, access Kbytes Flash memory through well SRAM I/O. 8031 execution jumps Flash memory pages from call upper half page zero (FS2 FS3), care must taken leave path return page zero again. However, call page from routine lower half page zero (common area, FS1), there problem returning from call. When placing code Flash memory upper half pages zero, one, two, software designer must break tasks into logical groups. These groups should need access code other pages frequently. (Most software split this manner result good modular design.) Since system SRAM available page, firmware routines that reside different pages pass data using global variables stack. designer create pageswitching algorithms jump between tasks different pages. There many ways implement paging scheme: method involves table that contains addresses page numbers program tasks, which called from page page. table algorithms must reside portion Flash memory that's located common area. This provides very clean paging solution, which implemented using high-level compiler. (The compiler from Keil supports this directly, creates tables you.) only penalty when using this method overhead experienced when switching from page another. this tutorial design, five different files from cross-compiler linker will used program memory sections PSD813F1. These dummy files with code them, present illustrate merging firmware with configuration during Address Translate operation. this were real design, file common.hex would contain common functions interrupt vectors, would programmed into FS0/FS1. Three more files from linker, page_0.hex, page_1.hex, page_2.hex would contain partitioned code described above. such, these three files would programmed into segments FS2/FS3, FS4/FS5, FS6/FS7, respectively. Finally, file boot.hex, containing power-up boot code programming algorithms Flash memory, would programmed into EES0/EES1.
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Start-up sequences, UART downloads Let's assume that desired laptop host download firmware this embedded system over RS-232 UART channel (instead JTAG). These download actions program main Flash memory very first time; update main Flash after been programmed once; update boot code after being programmed first time device programmer JTAG link. There valid boot-up scenarios through that must handled system powerup (reset). default setting register power-up places main Flash memory data space EEPROM program space. Refer memory maps Figures through boot-up scenarios follows:
RS-232 cable attached, main Flash valid. 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory ENABLE_DATA_HALF boot download request exists Normal application code executed from main Flash memory. RS-232 cable attached, main Flash valid, download demands from host. Action: same step "a.", above. RS-232 cable attached, main Flash valid, download main Flash demanded host. 8031 action: Boots from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure Program main Flash memory with data from UART checksum. register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory ENABLE_DATA_HALF boot download request exists Normal application code executed from main Flash memory.
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RS-232 cable attached, main Flash blank invalid. 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure Wait until UART traffic present (Figure RS-232 cable attached, main Flash blank invalid. 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure Program main Flash memory with data from UART checksum register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory ENABLE_DATA_HALF boot download request exists Normal application code executed from main Flash memory.
RS-232 cable attached, main Flash valid, system requests download boot memory 8031 action: Boot from EES0/EES1 checksum Flash memory Check UART pending host download request main Flash (Figure register main Flash into program space (Figure SWAP PSD, which swaps EES0/EES1 with (Figure register EEPROM into data space (Figure Now, system normal operating mode. More 8031 action: Check UART host download request boot memory Program EEPROM boot memory EES0 EES1 with data from UART checksum EES0 EES1 ENABLE_DATA_HALF protect boot code EES0 EES1 from inadvertent writes Enable data access EES2 EES3 Normal application code executed from main Flash memory.
Note: these host UART download options, assumed that normal boot (EES0/EES1) area programmed very first time device programmer before installed circuit card JTAG interface while in-system.
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