Available 5-V, 4.85-V, 3.3-V Fixed-Output Adjustable Versions Very Low

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Available 5-V, 4.85-V, 3.3-V Fixed-Output Adjustable Versions Very Low

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TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS
Available 5-V, 4.85-V, 3.3-V Fixed-Output Adjustable Versions Very Low-Dropout Voltage Maximum (TPS7150) Very Quiescent Current Independent Load Extremely Sleep-State Current Tolerance Over Specified Conditions Fixed-Output Versions
PACKAGE (TOP VIEW)
Output Current Range TSSOP Package Option Offers Reduced Component Height Space-Critical Applications Thermally Enhanced Surface-Mount Package Power-Good (PG) Status Output
PACKAGE (TOP VIEW)
SENSE/FB
PACKAGE (TOP VIEW)
SENSE
GND/HEATSINK GND/HEATSINK GND/HEATSINK GND/HEATSINK
GND/HEATSINK GND/HEATSINK SENSE/FB GND/HEATSINK GND/HEATSINK
PACKAGE (BOTTOM VIEW)
Thermal
internal connection SENSE Fixed voltage options only (TPS7133, TPS7148, TPS7150) Adjustable version only (TPS7101)
description
TPS71xx integrated circuits family micropower low-dropout (LDO) voltage regulators. order magnitude reduction dropout voltage quiescent current over conventional performance achieved replacing typical pass transistor with PMOS device.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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description (continued)
Because PMOS device behaves low-value resistor, dropout voltage very (maximum output current TPS7150) directly proportional output current (see Figure Additionally, since PMOS pass element voltage-driven device, quiescent current very remains independent output loading (typically over full range output current, mA). These specifications yield significant improvement operating life battery-powered systems. family also features sleep mode; applying high signal (enable) shuts down regulator, reducing quiescent current maximum 25°C.
0.25 25°C Dropout Voltage
0.15
TPS7133 TPS7148
TPS7150 0.05
0.05 0.15 0.25 0.35 0.45 Output Current
Figure Dropout Voltage Versus Output Current Power good (PG) reports output voltage used implement power-on reset low-battery indicator. TPS71xx offered 3.3-V, 4.85-V, fixed-voltage versions adjustable version (programmable over range 9.75 Output voltage tolerance specified maximum over line, load, temperature ranges adjustable version). TPS71xx family available PDIP pin), pin), TSSOP (20-pin) standard thermally enhanced packages. TSSOP maximum height thermally enhanced surface-mount power package innovative thermal that, when soldered printed-wiring board (PWB), enables device dissipate several watts power (see Thermal Information section).
AVAILABLE OPTIONS OUTPUT VOLTAGE 55°C 150°C 4.75 3.23 4.85 4.95 3.37 SMALL OUTLINE TPS7150QD TPS7148QD TPS7133QD TPS7101QD PACKAGED DEVICES PLASTIC TPS7150QP TPS7148QP TPS7133QP TPS7101QP TSSOP (PW) TPS7150QPWLE TPS7148QPWLE TPS7133QPWLE TPS7101QPWLE TSSOP (PWP) TPS7150QPWP TPS7148QPWP TPS7133QPWP TPS7101QPWP CHIP FORM
TPS7150Y TPS7148Y TPS7133Y TPS7101Y
Adjustable 9.75
package available taped reeled. suffix device type (e.g., TPS7150QDR). packages only available left-end taped reeled indicated suffix device type (i.e., TPS7150QPWLE). TPS7101Q programmable using external resistor divider (see application information). chip form tested 25°C.
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TPS71xx SENSE
TPS7133, TPS7148, TPS7150 (fixed-voltage options) Capacitor selection nontrivial. application information section details.
Figure Typical Application Configuration
TPS71xx chip information
These chips, when properly assembled, display characteristics similar TPS71xxQ. Thermal compression ultrasonic bonding used doped aluminum bonding pads. chips mounted with conductive epoxy gold-silicon preform.
BONDING ASSIGNMENTS TPS71xx CHIP THICKNESS: MILS TYPICAL BONDING PADS: MILS MINIMUM TJmax 150°C TOLERANCES 10%. DIMENSIONS MILS. SENSE Fixed voltage options only (TPS7133, TPS7148, TPS7150) Adjustable version only (TPS7101) NOTE most applications, SENSE should tied together close possible device; other implementations, refer SENSE-pin connection discussion Applications Information section this data sheet.
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functional block diagram
1.12 Vref 1.178 SENSE RESISTOR DIVIDER OPTIONS DEVICE TPS7101 TPS7133 TPS7148 TPS7150 UNIT
NOTE Resistors nominal values only.
Switch positions shown with (active). most applications, SENSE should externally connected close possible device. other implementations, refer SENSE-pin connection discussion Applications Information section.
absolute maximum ratings over operating free-air temperature range (unless otherwise
Input voltage SENSE, Output current, Continuous total power dissipation Dissipation Rating Tables Operating virtual junction temperature range, 55°C 150°C Storage temperature range, Tstg 65°C 150°C Lead temperature (1/16 inch) from case seconds 260°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. voltage values with respect network terminal ground. DISSIPATION RATING TABLE FREE-AIR TEMPERATURE (see Figure PACKAGE PW|| PWP|| 25°C POWER RATING 1175 DERATING FACTOR ABOVE 25°C mW/°C mW/°C W/°C mW/°C mW/°C 70°C POWER RATING 125°C POWER RATING
DISSIPATION RATING TABLE CASE TEMPERATURE (see Figure PACKAGE PW|| PWP|| 25°C POWER RATING 2188 2738 4025 DERATING FACTOR ABOVE 25°C 17.5 mW/°C mW/°C 21.9 W/°C 32.2 mW/°C 285.7 mW/°C 70°C POWER RATING 1400 1752 2576 22.9 125°C POWER RATING
Dissipation rating tables figures provided maintenance junction temperature below absolute maximum temperature 150°C. guidelines maintaining junction temperature within recommended operating range, Thermal Information section. Refer Thermal Information section detailed power dissipation considerations when using TSSOP packages.
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DISSIPATION DERATING CURVE FREE-AIR TEMPERATURE
1400 Maximum Continuous Dissipation Maximum Continuous Dissipation 1200 Package 106°C/W 4800 4400 4000 3600 3200 2800 2400 2000 1600 1200
DISSIPATION DERATING CURVE CASE TEMPERATURE
Package 31°C/W Package 46°C/W
1000
Package 172°C/W
Package 178°C/W
Package 57°C/W Case Temperature
Free-Air Temperature
Figure
Figure
MAXIMUM CONTINUOUS DISSIPATION CASE TEMPERATURE
Maximum Continuous Dissipation
Package
Measured with exposed thermal coupled infinite heat sink with thermally conductive compound (the thermal conductivity compound 0.815 °C). 3.5°C/W.
Case Temperature
Figure
Dissipation rating tables figures provided maintenance junction temperature below absolute maximum temperature 150°C. guidelines maintaining junction temperature within recommended operating range, Thermal Information section.
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recommended operating conditions
TPS7101Q Input voltage, voltage TPS7133Q TPS7148Q TPS7150Q High-level input voltage Low-level input voltage Output current range, 3.77 5.33 UNIT
Operating virtual junction temperature range, Minimum input voltage defined recommended operating conditions maximum specified output voltage plus dropout voltage maximum specified load range. Since dropout voltage function output current, usable range extended lighter loads. calculate minimum input voltage your maximum output current, following equation: VI(min) VO(max) VDO(max load) Because TPS7101 programmable, rDS(on) should used calculate before applying above equation. equation calculating from rDS(on) given Note electrical characteristics table. minimum value absolute lower limit recommended input voltage range TPS7101.
electrical characteristics µF/CSR SENSE/FB shorted (unless otherwise noted)
PARAMETER TEST 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 40°C 125°C 2.05 1.06 40°C 125°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 0.02 TPS7101Q, TPS7133Q TPS7148Q, TPS7150Q Ground current (active mode) Input current (standby mode) Output current limit Pass-element leakage current Pass element standby mode leakage current Output voltage temperature coefficient Thermal shutdown junction temperature logic high (standby mode) logic (active mode) hysteresis voltage input current Minimum active pass element Minimum valid ppm/°C UNIT
Normal operation operation,
(compensation series resistance) refers total series resistance, including equivalent series resistance (ESR) capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7101 electrical characteristics µF/CSR shorted device leads (unless otherwise noted)
PARAMETER Reference voltage (measured with connected Reference voltage temperature coefficient Input regulation Note TEST CONDITIONS Note 25°C 40°C 125°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 2.13 25°C 40°C 125°C 25°C 40°C 125°C 1.101 1.145 µVrms µV/Hz 0.32 0.23 0.52 0.83 1.143 TPS7101Q 1.178 1.213 0.85 0.85 UNIT ppm/°C
Pass-element series resistance (see Pass element Note
Note Output regulation Note Ripple rejection Note Output noise-spectral density Output noise voltage trip-threshold hysteresis output input current kHz,
voltage decreasing from above Measured
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately. Output voltage programmed with closed-loop configuration (see application information). NOTES: When simultaneously, pass element rDS(on) increases (see Figure point such that resulting dropout voltage prevents regulator from maintaining specified tolerance range. calculate dropout voltage, equation: rDS(on) rDS(on) function both output current input voltage. parametric table lists rDS(on) which corresponds dropout conditions programmed output voltages respectively. other programmed values, refer Figure
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TPS7133 electrical characteristics µF/CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS Dropout voltage Pass-element series resistance Input regulation (3.23 VO)/IO, 3.23 3.23 3.23 3.23 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 25°C 40°C 125°C 2.868 0.22 µVrms µV/Hz 0.47 3.23 TPS7133Q 3.37 UNIT
Output regulation Ripple rejection Output noise-spectral density kHz,
Output noise voltage
trip-threshold voltage hysteresis voltage output voltage
voltage decreasing from above
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7148 electrical characteristics 5.85 µF/CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS 5.85 5.85 Dropout voltage Pass-element series resistance Input regulation (4.75 VO)/IO, 5.85 4.75 4.75 4.75 4.75 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 4.12 25°C 40°C 125°C µVrms µV/Hz 0.32 4.75 TPS7148Q 4.85 4.95 0.35 0.52 UNIT
5.85 Output regulation 5.85 Ripple rejection Output noise-spectral density kHz,
Output noise voltage
trip-threshold voltage hysteresis voltage output voltage
voltage decreasing from above
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TPS7150 electrical characteristics µF/CSR SENSE shorted (unless otherwise noted)
PARAMETER Output voltage TEST CONDITIONS Dropout voltage Pass-element series resistance Input regulation (4.88 VO)/IO, 4.88 4.88 4.88 4.88 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 40°C 125°C 25°C 25°C 25°C 25°C 40°C 125°C 25°C 4.25 25°C 40°C 125°C 4.55 4.75 µVrms µV/Hz 0.29 TPS7150Q 0.32 0.47 UNIT
Output regulation Ripple rejection Output noise-spectral density kHz,
Output noise voltage
trip-threshold voltage hysteresis voltage output voltage
voltage decreasing from above
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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electrical characteristics µF/CSR 25°C, SENSE/FB shorted (unless otherwise noted)
PARAMETER TEST CONDITIONS Normal operation, TPS7101Y, TPS7133Y TPS7148Y, TPS7150Y Ground current (active mode) Output current limit leakage current Thermal shutdown junction temperature hysteresis voltage Minimum active pass element Minimum valid 0.02 2.05 1.06 UNIT
PARAMETER Reference voltage (measured with connected Pass-element series resistance (see Note
TEST CONDITIONS Measured
TPS7101Y 1.178 0.83 0.52 0.32 0.23
UNIT
Input regulation
Note Note Note kHz, 2.13
µV/Hz µVrms
Output regulation
Ripple rejection Output noise-spectral density Output noise voltage hysteresis output input current
refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately. Output voltage programmed with closed-loop configuration (see application information). NOTES: When simultaneously, pass element rDS(on) increases (see Figure point such that resulting dropout voltage prevents regulator from maintaining specified tolerance range. calculate dropout voltage, equation: rDS(on) rDS(on) function both output current input voltage. parametric table lists rDS(on) which corresponds dropout conditions programmed output voltages respectively. other programmed values, refer Figure
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electrical characteristics µF/CSR 25°C, SENSE shorted (unless otherwise noted) (continued)
PARAMETER Output voltage 3.23 3.23 3.23 (3.23 VO)/IO, kHz, TEST CONDITIONS 3.23 TPS7133Y 0.02 0.47 0.22 µVrms µV/Hz UNIT
Dropout voltage
Pass-element series resistance Output regulation Ripple rejection Output noise-spectral density
Output noise voltage
hysteresis voltage output voltage
PARAMETER Output voltage 5.85 4.75 4.75 4.75
TEST CONDITIONS 4.75
TPS7148Y 4.85 0.08 0.32
UNIT
Dropout voltage
Pass-element series resistance Output regulation Ripple rejection Output noise-spectral density
(4.75 VO)/IO, 5.85 5.85 5.85 5.85 5.85 kHz, 5.85
µV/Hz µVrms
Output noise voltage
hysteresis voltage
4.12 output voltage refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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electrical characteristics µF/CSR 25°C, SENSE shorted (unless otherwise noted) (continued)
PARAMETER Output voltage 4.88 4.88 4.88 (4.88 VO)/IO, kHz, TEST CONDITIONS 4.88 TPS7150Y 0.13 0.29 µVrms µV/Hz UNIT
Dropout voltage
Pass-element series resistance Output regulation Ripple rejection Output noise-spectral density
Output noise voltage
hysteresis voltage
4.25 output voltage refers total series resistance, including capacitor, series resistance added externally, trace resistance Pulse-testing techniques used maintain virtual junction temperature close possible ambient temperature; thermal effects must taken into account separately.
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TYPICAL CHARACTERISTICS Table Graphs
FIGURE Output current Quiescent current Typical Dropout voltage Change dropout voltage Change output voltage Output voltage Change output voltage Input voltage Free-air temperature Output current Free-air temperature Free-air temperature Input voltage Input voltage Output voltage Output current Ripple rejection Frequency Output spectral noise density Frequency rDS(on) II(SENSE) Pass-element resistance Divider resistance SENSE current leakage current II(EN) Minimum input voltage active-pass element Minimum input voltage valid Input current (EN) Output voltage response from Enable (EN) Power-good (PG) voltage Compensation Series Resistance Compensation Series Resistance Compensation Series Resistance Compensation Series Resistance Output voltage Output current Ceramic capacitance Output current Ceramic capacitance Input voltage Free-air temperature Free-air temperature Free-air temperature Free-air temperature Free-air temperature Free-air temperature
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TYPICAL CHARACTERISTICS
QUIESCENT CURRENT OUTPUT CURRENT
Quiescent Current TPS7148, 5.85 Output Current TPS7133, TPS7150, 25°C Quiescent Current TPS71xx,
QUIESCENT CURRENT INPUT VOLTAGE
25°C TPS7133 TPS7148 TPS7150
TPS7101 With Programmed
Input Voltage
Figure
TPS7148Q
Figure
DROPOUT VOLTAGE OUTPUT CURRENT
25°C 0.25 TPS7133 Dropout Voltage
QUIESCENT CURRENT FREE-AIR TEMPERATURE
VO(nom) Quiesent Current
0.15
TPS7148
TPS7150
0.05
Free-Air Temperature Output Current
Figure
Figure
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TYPICAL CHARACTERISTICS
CHANGE DROPOUT VOLTAGE FREE-AIR TEMPERATURE
Change Dropout Voltage Change Output Voltage VO(nom)
CHANGE OUTPUT VOLTAGE FREE-AIR TEMPERATURE
Free-Air Temperature
Free-Air Temperature
Figure
OUTPUT VOLTAGE INPUT VOLTAGE
Change Output Voltage 25°C Output Voltage TPS7148 TPS7150 Input Voltage
Figure
CHANGE OUTPUT VOLTAGE INPUT VOLTAGE
25°C
TPS7150 TPS7148
TPS7133 TPS7101 With Programmed
TPS7133
Input Voltage
Figure
Figure
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TYPICAL CHARACTERISTICS
TPS7101Q TPS7133Q
OUTPUT VOLTAGE OUTPUT CURRENT
2.52 2.515 2.51 2.505 2.495 2.49 2.485 2.48 Output Current 25°C Programmed 3.34 25°C 3.33 3.32 3.31 3.29 3.28 3.27 3.26
OUTPUT VOLTAGE OUTPUT CURRENT
Output Voltage
Output Voltage
Output Current
Figure
TPS7148Q
Figure
TPS7150Q
OUTPUT VOLTAGE OUTPUT CURRENT
4.92 4.91 Output Voltage Output Voltage 4.89 4.88 4.87 4.86 4.85 4.84 4.83 4.82 4.81 5.85 25°C 5.06 5.05 5.04 5.03 5.02 5.01 4.99 4.98 4.97 4.96 4.95 4.94 Output Current 25°C
OUTPUT VOLTAGE OUTPUT CURRENT
Output Current
Figure
Figure
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TYPICAL CHARACTERISTICS
TPS7101Q TPS7133Q
RIPPLE REJECTION FREQUENCY
Ripple Rejection
RIPPLE REJECTION FREQUENCY
Ripple Rejection
25°C (CSR Input Capacitance Programmed 100K
25°C (CSR Input Capacitance
Frequency
Frequency
Figure
TPS7148Q
Figure
TPS7150Q
RIPPLE REJECTION FREQUENCY
Ripple Rejection Ripple Rejection
RIPPLE REJECTION FREQUENCY
25°C (CSR Input Capacitance
25°C (CSR Input Capacitance
Frequency
Frequency
Figure
Figure
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TYPICAL CHARACTERISTICS
TPS7101Q TPS7133Q
OUTPUT SPECTRAL NOISE DENSITY FREQUENCY
Output Spectral Noise Density 25°C Input Capacitance Programmed (CSR (CSR Output Spectral Noise Density
OUTPUT SPECTRAL NOISE DENSITY FREQUENCY
25°C Input Capacitance (CSR (CSR (CSR
(CSR 0.01 Frequency
0.01
Frequency
Figure
TPS7148Q
Figure
TPS7150Q
OUTPUT SPECTRAL NOISE DENSITY FREQUENCY
Output Spectral Noise Density Output Spectral Noise Density 25°C Input Capacitance 5.85 (CSR (CSR
OUTPUT SPECTRAL NOISE DENSITY FREQUENCY
(CSR (CSR 25°C Input Capacitance
(CSR
(CSR 0.01 Frequency 0.01 Frequency
Figure
Figure
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TYPICAL CHARACTERISTICS
PASS-ELEMENT RESISTANCE INPUT VOLTAGE
rDS(on) Pass-Element Resistance Input Voltage 25°C VI(FB) 1.12 Divider Resistance TPS7148 TPS7133
DIVIDER RESISTANCE FREE-AIR TEMPERATURE
VO(nom) VI(sense) VO(nom) TPS7150
Free-Air Temperature
Figure
FIXED-OUTPUT VERSIONS SENSE CURRENT FREE-AIR TEMPERATURE
I(sense) Sense Current VO(nom) VI(sense) VO(nom) Leakage Current
Figure
ADJUSTABLE VERSION LEAKAGE CURRENT FREE-AIR TEMPERATURE
Free-Air Temperature
Free-Air Temperature
Figure
Figure
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TYPICAL CHARACTERISTICS
MINIMUM INPUT VOLTAGE ACTIVE PASS ELEMENT FREE-AIR TEMPERATURE
2.09 Minimum Input Voltage 2.08 2.07 2.06 2.05 2.04 2.03 2.02 2.01 Free-Air Temperature Minimum Input Voltage 1.09
MINIMUM INPUT VOLTAGE VALID POWER GOOD (PG) FREE-AIR TEMPERATURE
1.08
1.07
Figure
INPUT CURRENT FREE-AIR TEMPERATURE
I(EN) Input Current VI(EN)
Free-Air Temperature
Figure
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1.05
Free-Air Temperature
Figure
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TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN)
Output Voltage VO(nom)
Time
Figure
POWER-GOOD (PG) VOLTAGE OUTPUT VOLTAGE
25°C Pulled With Power-Good (PG) Voltage
Output Voltage percent VO(nom))
Figure
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Voltage
25°C (ESR Input Capacitance
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS
TYPICAL CHARACTERISTICS
TYPICAL REGIONS STABILITY TYPICAL REGIONS STABILITY
COMPENSATION SERIES RESISTANCE OUTPUT CURRENT
Compensation Series Resistance Compensation Series Resistance VO(nom) Input Capacitance Added Ceramic Capacitance 25°C Region Instability
COMPENSATION SERIES RESISTANCE OUTPUT CURRENT
VO(nom) Input Capacitance Ceramic Capacitance 25°C Region Instability
Region Instability Output Current
Region Instability Output Current
Figure
TYPICAL REGIONS STABILITY
Figure
TYPICAL REGIONS STABILITY
COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE
Compensation Series Resistance Compensation Series Resistance VO(nom) Input Capacitance 25°C Region Instability
COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE
VO(nom) Input Capacitance 25°C Region Instability
Region Instability Ceramic Capacitance
Region Instability Ceramic Capacitance
Figure
Figure
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TYPICAL CHARACTERISTICS
TYPICAL REGIONS STABILITY TYPICAL REGIONS STABILITY
COMPENSATION SERIES RESISTANCE OUTPUT CURRENT
Compensation Series Resistance Region Instability Compensation Series Resistance VO(nom) Input Capacitance Ceramic Capacitance 25°C
COMPENSATION SERIES RESISTANCE OUTPUT CURRENT
VO(nom) Input Capacitance Added Ceramic Capacitance 25°C
Region Instability
Output Current
Output Current
Figure
TYPICAL REGIONS STABILITY
Figure
TYPICAL REGIONS STABILITY
COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE
Compensation Series Resistance Compensation Series Resistance VO(nom) Input Capacitance 25°C
COMPENSATION SERIES RESISTANCE ADDED CERAMIC CAPACITANCE
VO(nom) Input Capacitance 25°C
Region Instability
Region Instability
Ceramic Capacitance
Ceramic Capacitance
Figure
values below recommended.
Figure
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TYPICAL CHARACTERISTICS
SENSE Ccer Load
Ceramic capacitor
Figure Test Circuit Typical Regions Stability (Figures through
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THERMAL INFORMATION standard TSSOP-20
response system-miniaturization trends, integrated circuits being offered low-profile fine-pitch surface-mount packages. Implementation many today's high-performance devices these packages requires special attention power dissipation. Many system-dependent issues such thermal coupling, airflow, added heat sinks convection surfaces, presence other heat-generating components affect power-dissipation limits given component. Three basic approaches enhancing thermal performance illustrated this discussion: Improving power-dissipation capability design Improving thermal coupling component Introducing airflow system Figure example thermally enhanced layout 20-lead TSSOP package. This layout involves adding copper conduct heat away from device. this component board system illustrated Figure family curves illustrates effect increasing size copper-heat-sink surface area. standard board inch inch 0.062 inch); board traces heat sink area 1-oz (per square foot) copper. Figure shows thermal resistance same system with addition thermally conductive compound between body TSSOP package copper routed directly beneath device. thermal conductivity compound used this analysis 0.815 Using these figures determine system allows maximum power-dissipation limit calculated with equation: Where TJ(max) maximum allowable junction temperature (i.e., 150°C absolute maximum 125°C maximum recommended operating temperature specified operation). This limit should then applied internal power dissipated TPS71xx regulator. equation calculating total internal power dissipation TPS71xx D(total)
RJ(max) D(max)
qJA(system)
Because quiescent current TPS71xx family very low, second term negligible, further simplifying equation D(total)
20-lead TSSOP board system with thermally conductive compound between board device body, where 55°C, airflow /min, copper heat sink area cm2, maximum power-dissipation limit calculated. indicated Figure system 94°C/W; therefore, maximum power-dissipation limit
RJ(max) D(max)
qJA(system)
12594C
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THERMAL INFORMATION standard TSSOP-20 (continued)
system implements TPS7148 regulator where internal power dissipation D(total)
4.85) 0.385
Comparing PD(total) with PD(max) reveals that power dissipation this example does exceed maximum limit. When does, corrective actions taken. power-dissipation limit raised increasing airflow heat-sink area. Alternatively, internal power dissipation regulator lowered reducing input voltage load current. either case, above calculations should repeated with system parameters.
Copper Heat Sink Copper
Figure Thermally Enhanced Layout (not scale) 20-Pin TSSOP
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THERMAL INFORMATION
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT FLOW
Flow /min Component /Board System 20-Lead TSSOP
Thermal Resistance, Junction-to-Ambient °C/W
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT FLOW
Thermal Resistance, Junction-to-Ambient °C/W Flow /min Component /Board System 20-Lead TSSOP Includes Thermally Conductive Compound Between Body Board
Figure
Figure
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THERMAL INFORMATION thermally enhanced TSSOP-20
thermally enhanced package based 20-pin TSSOP, includes thermal [see Figure 47(c)] provide effective thermal contact between PWB. Traditionally, surface mount power have been mutually exclusive terms. variety scaled-down TO220-type packages have leads formed gull wings make them applicable surface-mount applications. These packages, however, suffer from several shortcomings: they address very profile requirements many today's advanced systems, they offer pin-count high enough accommodate increasing integration. other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits usable range many high-performance analog circuits. package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal performance comparable much larger power packages. package designed optimize heat transfer PWB. Because very small size limited mass TSSOP package, thermal enhancement achieved improving thermal conduction paths that remove heat from component. thermal formed using lead-frame design (patent pending) manufacturing technique provide user with direct connection heat-generating When this soldered otherwise coupled external heat dissipator, high power dissipation ultrathin, fine-pitch, surface-mount package reliably achieved.
Side View
Thermal
View
Bottom View
Figure Views Thermally Enhanced Package
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THERMAL INFORMATION thermally enhanced TSSOP-20 (continued)
Because conduction path been enhanced, power-dissipation capability determined thermal considerations design. example, simply adding localized copper plane (heat-sink surface), which coupled thermal pad, enables package dissipate free (reference Figure 49(a), copper heat sink natural convection). Increasing heat-sink size increases power dissipation range component. power dissipation limit further improved adding airflow PWB/IC assembly (see Figures 49). line drawn Figures indicates performance minimum recommended heat-sink size, illustrated Figure thermal directly connected substrate which TPS71xxQPWP series secondary electrical connection device ground. heat-sink surface that added ground plane left electrically isolated. other TO220-type surface-mount packages, thermal connection also primary electrical connection given terminal which always ground. package provides independent leads that used inputs outputs (Note: leads internally connected thermal substrate).
THERMAL RESISTANCE COPPER HEAT-SINK AREA
Thermal Resistance
Natural Convection ft/min ft/min
ft/min ft/min
ft/min ft/min
Copper Heat-Sink Area
Figure
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THERMAL INFORMATION thermally enhanced TSSOP-20 (continued)
25°C Power Dissipation Limit ft/min ft/min Power Dissipation Limit ft/min 55°C
Natural Convection
ft/min
Natural Convection
Copper Heat-Sink Size 105°C Power Dissipation Limit
Copper Heat-Sink Size
ft/min ft/min Natural Convection
Copper Heat-Sink Size
Figure Power Ratings Package Ambient Temperatures 25°C, 55°C, 105°C
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THERMAL INFORMATION thermally enhanced TSSOP-20 (continued)
Figure example thermally enhanced layout with package. This board configuration used thermal experiments that generated power ratings shown Figures discussed earlier, copper been added conduct heat away from device. this assembly illustrated Figure function heat-sink area. family curves included illustrate effect airflow introduced into system.
Heat-Sink Area Copper
Board thickness Board size Board material Copper trace/heat sink Exposed mounting
mils 63/67 tin/lead solder
Figure Layout (Including Copper Heatsink Area) Thermally Enhanced Package From Figure assembly determined used calculate maximum power-dissipation limit component/PWB assembly, with equation: Where TJmax maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended operating limit) ambient temperature. PD(max) should then applied internal power dissipated TPS7133QPWP regulator. equation calculating total internal power dissipation TPS7133QPWP D(total) Jmax D(max)
qJA(system)
Since quiescent current TPS7133QPWP very low, second term negligible, further simplifying equation D(total)
case where 55°C, airflow /min, copper heat-sink area cm2, maximum power-dissipation limit calculated. First, from Figure find system 50°C/W; therefore, maximum power-dissipation limit Jmax 12550C°C D(max)
qJA(system)
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THERMAL INFORMATION thermally enhanced TSSOP-20 (continued)
system implements TPS7133QPWP regulator, where internal power dissipation D(total)
3.3) 1.35
Comparing PD(total) with PD(max) reveals that power dissipation this example does exceed calculated limit. When does, corrective actions should made: raising power-dissipation limit increasing airflow heat-sink area, lowering internal power dissipation regulator reducing input voltage load current. either case, above calculations should repeated with system parameters.
mounting information
Since thermal primary connection electrical signal, importance electrical connection significant. primary requirement complete thermal contact between thermal metal. thermal solderable surface fully intended soldered time component mounted. Although voiding thermal-pad solder-connection desirable, voiding acceptable. data included Figures soldered connections with voiding between 50%. thermal analysis shows significant difference resulting from variation voiding percentage. Figure shows solder-mask land pattern package. minimum recommended heat-sink area also illustrated. This simply copper plane under body extent package, including metal routed under terminals
Minimum Recommended Heat-Sink Area Location Exposed Thermal Package
0.27
reliability information
This section includes demonstrated reliability test results obtained from qualification program. Accelerated tests performed high-stress conditions that product reliability established during relatively short test duration. Specific stress conditions chosen represent accelerated versions various deviceapplication environments allow meaningful extrapolation normal operating conditions. component level reliability test results
0.65
5.72
Figure Package Land Pattern
preconditioning
Preconditioning components prior reliability testing employed simulate actual board assembly process used customer. This ensures that reliability test results more representative those that would seen final application. general form preconditioning sequence includes moisture soak followed multiple vapor-phase-reflow infrared-reflow solder exposures. components used following reliability tests were preconditioned accordance with JEDEC Test Method A113 Level (not moisture-sensitive) products.
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THERMAL INFORMATION
high-temperature life test
High-temperature life testing used demonstrate long-term reliability product under bias. potential failure mechanisms evaluated with this stress those associated with dielectric integrity design process sensitivity mobile-ion phenomena. Components tested elevated ambient temperature 155°C extended period. Results derated using Arrhenius equation equivalent number unit hours representative application temperature. corresponding predicted failure rate expressed FITs, failures billion device-hours. failure rate shown this case data-limited since actual failures were experienced during qualification testing.
PREDICTED LONG-TERM FAILURE RATE Number Units Equivalent Unit Hours 55°C 24,468,090 FITs 36.2
biased humidity test
Biased humidity testing used evaluate effects moisture penetration plastic-encapsulated devices under bias. This stress verifies integrity package construction passivation system. primary potential failure mechanism electrolytic corrosion. Components biased power state reduce heat dissipation subjected 120°C, 85%-relative-humidity environment hours.
BIASED HUMIDITY TEST RESULTS Equivalent Unit Hours 85°C 357,000 Failures
autoclave test
autoclave stress used assess capabilities package construction materials with respect moisture ingress extended exposure. Predominant failure mechanisms include leakage currents that result from internal moisture accumulation galvanic corrosion resulting from reactions with present ionic contaminants. Components subjected 121°C, PSIG, 100%-relative-humidity environment hours.
AUTOCLAVE TEST RESULTS Total Unit Hours 54,720 Failures
thermal shock test
Thermal shock testing used evaluate capability component withstand mechanical stress resulting from differences thermal coefficients expansion among package construction materials. Failure mechanisms typically related physical damage interface locations between different materials. Components cycled between -65°C 150°C liquid mediums total duration 1000 cycles.
THERMAL SHOCK TEST RESULTS Total Unit Cycles 345,000 Failures
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THERMAL INFORMATION
assembly level reliability results
temperature cycle test
Temperature cycle testing assembly used evaluate capability assembly withstand mechanical stress resulting from differences thermal coefficients expansion among die, package, board materials. This testing also used sufficiently soldered thermal connection between thermal trace board evaluate degradation thermal resistance board-mounted test unit. assemblies were cycled between temperature extremes 40°C 125°C total duration cycles.
TEMPERATURE CYCLE TEST RESULTS Total Unit Cycles 36,500 Failures Average Change RJA(system) 0.41%
solderability test
Solderability testing used simulate actual board-mount performance reflow process. Solderability testing conducted follows: test devices first steam-aged hours. stencil used apply solder-paste terminal pattern ceramic substrate (nominal stencil thickness 0.005 inch). test units manually placed solder-paste footprint with proper implements avoid contamination. ceramic substrate components subjected reflow process follows:
REFLOW PROCESS PREHEAT SOAK Temperature Time 150°C 170°C REFLOW 215°C 230°C
After cooling room temperature, component removed from ceramic substrate component terminals subjected visual inspection magnification. Test results acceptable terminations exhibit continuous solder coating free defects minimum critical surface area individual termination. Causes rejection include: dewetting, nonwetting, holes. component leads exposed thermal were evaluated against this criteria.
SOLDERABILITY TEST RESULTS Number Test Units Failures
X-ray test
X-ray testing used examine quantify voiding soldered attachment between thermal copper trace. Voiding between observed 49-piece sample.
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APPLICATION INFORMATION
X-ray test (continued)
TPS71xx series low-dropout (LDO) regulators designed overcome many shortcomings earlier-generation LDOs, while adding features such power-saving shutdown mode power-good indicator. TPS71xx family includes three fixed-output voltage regulators: TPS7133 (3.3 TPS7148 (4.85 TPS7150 family also offers adjustable device, TPS7101 (adjustable from 9.75
device operation
TPS71xx, unlike many other LDOs, features very quiescent currents that remain virtually constant even with varying loads. Conventional regulators pnp-pass element, base current which directly proportional load current through regulator IC/). Close examination data sheets reveals that those devices typically specified under near no-load conditions; actual operating currents much higher evidenced typical quiescent current versus load current curves. TPS71xx uses PMOS transistor pass current; because gate PMOS element voltage driven, operating currents invariable over full load range. TPS71xx specifications reflect actual performance under load. Another pitfall associated with pnp-pass element tendency saturate when device goes into dropout. resulting drop forces increase maintain load. During power this translates large start-up currents. Systems with limited supply current fail start battery-powered systems, means rapid battery discharge when voltage decays below minimum required regulation. TPS71xx quiescent current remains even when regulator drops out, eliminating both problems. Included TPS71xx family 4.85-V regulator, TPS7148. Designed specifically cellular systems, 4.85-V output, regulated within allows operation within low-end limit systems specified tolerance; therefore, maximum regulated operating lifetime obtained from battery pack before device drops out, adding crucial talk minutes between charges. TPS71xx family also features shutdown mode that places output high-impedance state (essentially equal feedback-divider resistance) reduces quiescent current under shutdown feature used, should tied ground. Response enable transition quick; regulated output voltage reestablished typically
minimum load requirements
TPS71xx family stable even zero load; minimum load required operation.
SENSE-pin connection
SENSE fixed-output devices must connected regulator output proper functioning regulator. Normally, this connection should short possible; however, connection made near critical circuit (remote sense) improve performance that point. Internally, SENSE connects high-impedance wide-bandwidth amplifier through resistor-divider network noise pickup feeds through regulator output. Routing SENSE connection minimize/avoid noise pickup essential. Adding network between SENSE filter noise recommended because cause regulator oscillate.
external capacitor requirements
input capacitor required; however, ceramic bypass capacitor (0.047 improves load transient response noise rejection TPS71xx located more than inches from power supply. higher-capacitance electrolytic capacitor necessary large (hundreds milliamps) load transients with fast rise times anticipated.
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APPLICATION INFORMATION external capacitor requirements (continued)
with most regulators, TPS71xx family requires output capacitor stability. low-ESR 10-µF solid-tantalum capacitor connected from regulator output ground sufficient ensure stability over full load range (see Figure 52). Adding high-frequency ceramic film capacitors (such power-supply bypass capacitors digital analog ICs) cause regulator become unstable unless tantalum capacitor less than over temperature. Capacitors with published specifications such TPSD106K035R0300 Sprague 593D106X0035D2W work well because maximum 25°C (typically, solid-tantalum capacitors increases factor less when temperature drops from 25°C 40°C). Where component height and/or mounting area problem, physically smaller, 10-µF devices screened ESR. Figures through show stable regions operation using different values output capacitance with various values ceramic load capacitance. applications with little high-frequency bypass capacitance µF), output capacitance reduced provided maintained between Because minimum capacitor seldom ever specified, necessary 0.5- resistor series with capacitor limit maximum. show graphs (Figures through 42), minimum problem when using 10-µF larger output capacitors. Below partial listing surface-mount capacitors usable with TPS71xx family. This information (along with graphs, Figures through included assist selection suitable capacitance user's application. When necessary achieve height requirements along with high output current and/or high ceramic load capacitance, several higher capacitors used parallel meet guidelines above. load temperature conditions with added ceramic load capacitance: PART T421C226M010AS 593D156X0025D2W 593D106X0035D2W TPSD106M035R0300 MFR. Kemet Sprague Sprague VALUE SIZE SIZE SIZE
Load ceramic load capacitance full temperature range: PART 592D156X0020R2T 595D156X0025C2T 595D106X0025C2T 293D226X0016D2W MFR. Sprague Sprague Sprague Sprague VALUE
Load ceramic load capacitance full temperature range: PART 195D106X06R3V2T 195D106X0016X2T 595D156X0016B2T 695D226X0015F2T 695D156X0020F2T 695D106X0035G2T MFR. Sprague Sprague Sprague Sprague Sprague Sprague VALUE
Size maximum resistance 25°C. Listings sorted height.
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APPLICATION INFORMATION external capacitor requirements (continued)
TPS71xx SENSE
TPS7133, TPS7148, TPS7150 (fixed-voltage options)
Figure Typical Application Circuit
programming TPS7101 adjustable regulator
Programming adjustable regulators accomplished using external resistor divider shown Figure equation governing output voltage where Vref reference voltage, 1.178
Vref
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APPLICATION INFORMATION programming TPS7101 adjustable regulator (continued)
Resistors should chosen approximately 7-µA divider current. recommended value with adjusted desired output voltage. Smaller resistors used, offer inherent advantage consume more power. Larger values should avoided leakage currents will introduce error. Solving equation yields more useful equation choosing appropriate resistance:
TPS7101 OUTPUT VOLTAGE PROGRAMMING GUIDE Power-Good Indicator OUTPUT VOLTAGE UNIT
>2.7
<0.5V
Figure TPS7101 Adjustable Regulator Programming
power-good indicator
TPS71xx features power-good (PG) output that used monitor status regulator. internal comparator monitors output voltage: when output drops between nominal regulated value, output transistor turns taking signal low. open-drain output requires pullup resistor. used, left floating. used drive power-on reset circuitry low-battery indicator. does assert itself when regulated output voltage falls outside specified tolerance, instead reports output voltage low, relative nominal regulated value.
regulator protection
TPS71xx PMOS-pass transistor built-in back diode that safely conducts reverse currents when input voltage drops below output voltage (e.g., during power down). Current conducted from output input internally limited. When extended reverse voltage anticipated, external limiting appropriate. TPS71xx also features internal current limiting thermal protection. During normal operation, TPS71xx limits output current approximately When current limiting engages, output voltage scales back linearly until overcurrent condition ends. While current limiting designed prevent gross device failure, care should taken exceed power dissipation ratings package. temperature device exceeds 165°C, thermal-protection circuitry shuts down. Once device cooled, regulator operation resumes.
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MECHANICAL DATA
(R-PDSO-G**)
SHOWN PINS 0.020 (0,51) 0.014 (0,35) 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27)
0.197 (5,00)
0.344 (8,75)
0.394 (10,00)
Gage Plane
0.010 (0,25) 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 10/94 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0.006 (0,15). Four center pins connected mount Falls within JEDEC MS-012
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MECHANICAL DATA
(R-PDIP-T8)
0.400 (10,60) 0.355 (9,02)
PLASTIC DUAL-IN-LINE PACKAGE
0.260 (6,60) 0.240 (6,10)
0.070 (1,78) 0.020 (0,51) 0.310 (7,87) 0.290 (7,37)
0.200 (5,08) Seating Plane 0.125 (3,18)
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25)
4040082 10/94 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Falls within JEDEC MS-001
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MECHANICAL DATA
(R-PDSO-G**)
SHOWN 0,32 0,17
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,13
0,15 4,50 4,30 6,70 6,10 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,10 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60 4040064 10/95
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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MECHANICAL DATA
(R-PDSO-G20) PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,32 0,17
0,13 Thermal
0,15 4,70 4,30 6,70 6,10 Gage Plane
6,80 6,40
0,25
0,75 0,50
Seating Plane 1,15 0,08 0,00 0,10
4073225 10/94 NOTES: linear dimensions millimeters. This drawing subject change without notice. package thermal performance enhanced bonding thermal external thermal plane. solderable electrically thermally connected backside leads
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IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

Available 5-V, 4.85-V, 3.3-V Fixed-Output Adjustable Versions Very Low

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