Clock Distribution Buffer Three Banks Mobile SDRAM output buffer

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Clock Distribution Buffer Three Banks Mobile SDRAM output buffer

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CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
output buffer high clock fanout applications. Output individually disabled with volts Output frequency range <250ps skew between output clocks. 16-pin SSOP TSSOP package.
Product Description
device high fanout system clock buffer. primary application distribute clocks needed support wide range applications such SDRAM clocks. This device provides skew distribution clock heavily loaded. important application this component where long traces used transport clocks from their generating devices their loads. creation degradation waveform rise fall times greatly reduces running single reference clock trace this device then using these devices therefore minimized board real estate saved.
Block Diagram
Configuration
Control
SDATA SCLK
SDR(0:1)
SDR0 SDR1 CLKIN SDR2 SDATA
SDR2 SDR(3:4) SDR(5:6)
REFIN
SDR6 SDR5 SDR4 SDR3 SCLK
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Description
2,3,6,11,12,15,16 4,10,14 1,7,13
Name
CLKIN SDR(0:6) SDATA SCLK
Type
BUF1
Description
This connected input reference clock. This clock range 10.0 100.0 Skew output clock. Serial data C-wire control interface. internal pull-up resistor. Serial data C-wire control interface. internal pull-up resistor COMMON Ground Power output clock buffers core logic
Maximum Ratings
Maximum Input Voltage Relative VSS: 0.3V Maximum Input Voltage Relative VDD: 0.3V Storage Temperature: Operating Temperature: Maximum Power Supply: +125
This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Approved Product 2-Wire Control Interface
2-wire control interface implements write only slave interface. device control read back. Subaddressing supported, thus, preceding bytes must sent order change control bytes. 2-wire control interface allows each clock output individually enabled disabled. During normal data transfer, SDATA signal only changes when SDCLK signal low, stable when SDCLK high. There exceptions this. high transition SDATA while SDCLK high used indicate start data transfer cycle. high transition SDATA while SDCLK high indicates data transfer cycle. Data always sent complete 8-bit bytes, after which acknowledge generated. first byte transfer cycle 7-bit address with read /write LSB. Data being transferred first. device respond writes bytes (max) data address generating acknowledge (low) signal SDATA wire following reception each byte. device will respond other control interface conditions.
Control Signal Registers
Note: pin# column lists affected number where applicable. @Pup column gives state true power Bytes values shown only true power when PWR_DWN# activated. Following acknowledge Address Byte (D2) additional bytes must sent: "Command Code" byte "Byte Count" byte Although data (bits) these bytes considered don't care", they must sent will acknowledge. After Command Code Count bytes have been acknowledge, below described sequence (Byte0, Byte1, Byte2.) will valid acknowledged.
Byte Enable, stopped)
@Pup Description SDR2(Enable =1,stopped=0) Reserved Reserved Reserved SDR1(Enable =1,stopped=0) SDR0(Enable =1,stopped=0) Reserved Reserved
Byte Enable, stopped)
@Pup Description SDR6 (enable=1,s topped=0) SDR5 (enable=1, stopped=0 Reserved Reserved SDR4 (enable=1, stopped=0) SDR3 (enable=1, stopped=0) Reserved Reserved
application note AN664-01 further reducing power consumption with
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Approved Product Electrical Characteristics
Characteristics Input Voltage Input High Voltage Input Current Input High Current Tri-State leakage current Dynamic Supply Current (all outputs loaded with Static Supply Current Short Circuit Current Input Rise Time Symbol Idd66 Idd100 Isdd Units Conditions
Input Frequency Input Frequency =100 outputs disabled input clock input time seconds Volts =VDD1 thru VDD6 3.3V±5%, 70°C
Switching Characteristics
Characteristics Output Duty Cycle Buffer Out/Out Skew Buffer Outputs Buffer Input Output Skew Jitter Cycle Cycle* Jitter Absolute (Peak Peak)* Symbol TSKEW Units Conditions Measured 1.5V (50/50 Load Measured 1.5V
TSKEW TJCC loading TJabs loading =VDD1 thru VDD6 3.3V±5%, 70°C *this jitter additive input clock's jitter
Buffer Characteristics Clock Outputs)
Characteristics Pull-Up Current ull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between 0.4V 2.4V Rise/Fall Time between 0.4V 2.4V Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax 1.33 1.33 Units Conditions Vout Vout Vout Vout Load Load
VDDI thru VDD6 3.3V±5%, +70°C
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Layout Suggestion
Plane Plane
Void (Cut) power plane
22µF
This only layout recommendation best performance lower EMI. designer choose different approach (all o.1µF) should always used placed close their pins physically possible. ferrite Bead resistor needed reduce conducted from device into systems power circuitry.
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Approved Product Package Drawing Dimensions TSSOP Outline Dimensions
SYMBOL
INCHES 0.002 0.031 0.007 0.004 0.193 0.169 0.039 0.197 0.173 0.026 0.244 0.018 0.252 0.024 0.260 0.030 0.047 0.006 0.041 0.012 0.008 0.201 0.177
MILLIMETERS 1.00 5.00 4.40 0.65 6.20 0.45 6.40 0.60 6.60 0.75 1.20 0.15 1.05 0.30 0.20 5.10 4.50
0.05 0.80 0.19 0.09 4.90 4.30
SSOP Outline Dimensions
INCHES SYMBOL 0.301 0.022 0.068 0.002 0.066 0.010 0.005 0.239 0.205 0.073 0.005 0.068 0.012 0.006 0.244 0.209 0.0256BSC 0.307 0.030 0.311 0.037 7.65 0.55 0.078 0.008 0.070 0.015 0.009 0.249 0.212 1.73 0.05 1.68 0.25 0.13 6.07 5.20 MILLIMETERS 1.86 0.13 1.73 0.30 0.15 6.20 5.30 0.65 7.80 0.75 7.90 0.95 1.99 0.21 1.78 0.38 0.22 6.33 5.38
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Approved Product Ordering Information
Part Number CB664ET CB664EY Note: Package Type TSSOP SSOP Production Flow Commercial, Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below. IMI, YYWWW CB664ET
Marking: Example:
CB664ET
Package TSSOP Revision Device Number
DISCLAIMER Cypress Semiconductor Corporation reserves right change modify information contained this datasheet products described therein, without prior notice. Cypress Semiconductor Corporation does convey license under patent rights rights others. Charts, drawings schedules contained this datasheet provided illustration purposes only they vary depending upon specific applications. Cypress Semiconductor Corporation makes warranty guarantee regarding suitability these products particular purpose, does Cypress Semiconductor Corporation assume liability arising application product circuit described herein. Cypress Semiconductor Corporation does authorize products critical components application which failure Cypress Semiconductor Corporation product expected result significant injury death, including life support systems critical medical instruments.
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page
CB664
Clock Distribution Buffer Three Banks Mobile SDRAM
Approved Product Document Title: CB664 Clock Distribution Buffer Three Banks Mobile SDRAM Document Number: 38-07024 REV. Issue Date Orig. Change Description Change 109163 08/29/01 Convert from Cypress
Cypress Semiconductor Corporation Coches Milpitas, 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com
Document#: 38-07024 Rev.
5/6/99 Page

Clock Distribution Buffer Three Banks Mobile SDRAM output buffer

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