Fast-mode Plus parallel I2C-bus controller Rev. August 2006 Objec
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Rev. August 2006 Objective data sheet
PCA9665 serves interface between most standard parallel-bus serial I2C-bus allows parallel system communicate bidirectionally with I2C-bus. PCA9665 operate master slave transmitter receiver. Communication with I2C-bus carried Byte Buffered mode using interrupt polled handshake. PCA9665 controls I2C-bus specific sequences, protocol, arbitration timing with external timing element required. PCA9665 same footprint PCA9564 with additional features:
transmission speeds drive capability SCL/SDA 68-byte buffer I2C-bus General Call Software reset parallel
Features
Parallel-bus I2C-bus protocol converter interface Both master slave functions Multi-master capability Internal oscillator trimmed accuracy reduces external components Mbit/s SCL/SDA (Fast-mode Plus) capability I2C-bus General Call capability Software reset parallel 68-byte data buffer Operating supply voltage: tolerant I/Os Standard-mode Fast-mode I2C-bus capable compatible with SMBus protection exceeds 2000 JESD22-A114, JESD22-A115, 1000 JESD22-C101 Latch-up testing done JEDEC Standard JESD78 which exceeds Packages offered: DIP20, SO20, TSSOP20, HVQFN20
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Applications
I2C-bus port controllers/processors that have additional I2C-bus ports controllers/processors that need multiple I2C-bus ports Converts bits parallel data serial data stream prevent having large number traces across entire printed-circuit board
Ordering information
Table Ordering information Tamb Type number PCA9665BS PCA9665D PCA9665N PCA9665PW Topside mark 9665 PCA9665D PCA9665N PCA9665 Package Name HVQFN20 SO20 DIP20 TSSOP20 Description plastic thermal enhanced very thin quad flat package; leads; terminals; body 0.85 plastic small outline package; leads; body width plastic dual in-line package; leads; (300 mil) plastic thin shrink small outline package; leads; body width Version SOT662-1 SOT163-1 SOT146-1 SOT360-1
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Objective data sheet
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Block diagram
data
PCA9665
FILTER BUFFER direct registers CONTROL 68-BYTE BUFFER ENSIO FILTER I2CSTA status register read only ENSIO MODE
I2CDAT data register read/write
INDPTR indirect address pointer write only
CONTROL
I2CCON control register read/write BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 INDIRECT indirect register access read/write
ENSIO
indirect registers INDPTR I2CCOUNT byte count read/write
I2CADR address read/write
I2CSCLL period read/write
BIT0
I2CSCLH HIGH period read/write BIT6 BIT5 BIT4 BIT3 BIT2 BIT1
I2CTO TIMEOUT register read/write
I2CPRESET software reset register write only
I2CMODE I2C-bus mode register read/write CONTROL BLOCK
CLOCK SELECTOR OSCILLATOR
INTERRUPT CONTROL
POWER-ON RESET
002aab023
control signals
RESET
Block diagram PCA9665
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Pinning information
Pinning
i.c.
RESET
002aab020
i.c.
RESET
002aab021
PCA9665D
PCA9665PW
configuration SO20
configuration TSSOP20
i.c.
terminal index area RESET RESET
PCA9665N
002aab019
PCA9665BS
i.c.
002aab022
Transparent view
configuration DIP20
configuration HVQFN20
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PCA9665
Fast-mode Plus parallel I2C-bus controller
description
Table Symbol description DIP, TSSOP HVQFN 7[1] Data bus: Bidirectional 3-state data used transfer commands, data status between controller CPU. least significant bit. internally connected: must left floating (pulled internally) Supply ground Write strobe: When also LOW, content data loaded into addressed register. Data latched rising edge either Read strobe: When also LOW, causes contents addressed register presented data bus. read cycle begins falling edge Chip Enable: Active input signal. When LOW, data transfers between controller enabled controlled inputs. When HIGH, places lines 3-state condition. Data written into addressed register rising edge either Address inputs: Selects controller's internal registers ports read/write operations. Interrupt request: Active LOW, open-drain, output. This requires pull-up device. Reset: Active input. level clears internal registers resets I2C-bus state machine. I2C-bus serial clock input/output (open-drain). This requires pull-up device. I2C-bus serial data input/output (open-drain). This requires pull-up device. Power supply: Type Description
i.c.
power
RESET
power
HVQFN package supply ground connected both exposed center pad. must connected supply ground proper device operation. enhanced thermal, electrical, board-level performance, exposed needs soldered board using corresponding thermal board, proper heat conduction through board thermal vias need incorporated thermal region.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Functional description
General
PCA9665 acts interface device between standard high-speed parallel buses serial I2C-bus. I2C-bus, either master slave. Bidirectional data transfer between I2C-bus parallel-bus microcontroller carried byte buffered basis, using either interrupt polled handshake.
Internal oscillator
PCA9665 contains internal 28.5 oscillator which used I2C-bus timing. oscillator requires start-up after ENSIO `1'.
Registers
PCA9665 contains eleven registers which used configure operation device well send receive serial data. There four registers that accessed directly seven registers that accessed indirectly setting register pointer. four direct registers selected setting pins appropriate logic levels before read write operation executed parallel bus. seven indirect registers require that INDPTR (indirect register pointer, four direct registers described above) initially loaded with address register indirect address space before read write performed INDIRECT data field. example, order write indirectly addressed I2CSCLL register, INDPTR register should loaded with performing write direct INDPTR register Then I2CSCLL register programmed writing INDIRECT data field direct address space. Register mapping described Table Table Figure Remark: write I2C-bus registers while I2C-bus busy PCA9665 master addressed slave mode.
Table I2CSTA INDPTR I2CDAT I2CCON INDIRECT
Direct register selection setting Register function status indirect register pointer data control indirect data field access Read/Write Default 00h[1]
Register name
Section 8.10 "Power-on reset" more detail.
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Objective data sheet
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Indirect register selection setting Register function byte count address period HIGH period time-out parallel software reset I2C-bus mode INDPTR Read/Write Default
Table I2CCOUNT I2CADR I2CSCLL I2CSCLH I2CTO
Register name
I2CPRESET I2CMODE
read? write? read/write?
I2CSTA REGISTER
INDPTR REGISTER
INDPTR
I2CCOUNT REGISTER
INDPTR read/write? I2CDAT REGISTER
I2CADR REGISTER
INDPTR I2CCON REGISTER
I2CSCLL REGISTER
read/write?
INDPTR
I2CSCLH REGISTER
INDPTR
I2CTO REGISTER
INDPTR
I2CPRESET REGISTER (write only)
INDPTR RESERVED
I2CMODE REGISTER
002aab459
Register mapping flowchart
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PCA9665
Fast-mode Plus parallel I2C-bus controller
7.3.1 Direct registers
7.3.1.1 Status register, I2CSTA I2CSTA 8-bit read-only register. least significant bits always zero. most significant bits contain status code. There possible status codes. When I2CSTA contains F8h, indicates idle state therefore serial interrupt requested. other I2CSTA values correspond defined states. When each these states entered, serial interrupt requested asserted LOW). Remark: Data I2CSTA valid only when serial interrupt occurs asserted LOW). Reading register when HIGH cause wrong values read.
Table Table I2CSTA Status register allocation
I2CSTA Status register description Symbol ST[5:0] Description status code corresponding different I2C-bus states always zero
7.3.1.2
Indirect Pointer register, INDPTR
Table Table INDPTR Indirect Register Pointer allocation
INDPTR Indirect Pointer register description Symbol Description reserved; must written with zeroes address indirect register
INDPTR 8-bit write-only register. contains pointer register indirect address space (IP[2:0]). value register will determine what indirect register will accessed when INDIRECT register read written, defined Table 7.3.1.3 I2C-bus Data register, I2CDAT I2CDAT 8-bit read/write register. contains byte serial data transmitted byte which just been received. master mode, this includes slave address that master wants send I2C-bus, with most significant slave address position Read/Write position. read from write this 8-bit register while PCA9665 process shifting byte. This occurs when PCA9665 defined state serial interrupt flag set. Data I2CDAT remains stable long set. Whenever PCA9665 generates interrupt, I2CDAT register contains data byte that just transferred I2C-bus.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Byte mode, read write single byte time. Buffered mode, read write bytes time. Section "Configuration modes" more detail. Remark: I2CDAT register will capture serial address data when addressed serial bus. Remark: Byte mode only, data register will capture data from serial during (arbitration lost slave address data bytes causing this data I2CDAT changed), I2CDAT register will need reloaded when becomes free. Buffered mode, data written data register when arbitration lost, which keeps buffer intact.
Table Table I2CDAT Data register allocation
I2CDAT Data register description Description Eight bits transmitted just received. logic I2CDAT corresponds HIGH level I2C-bus. logic corresponds level bus.
Symbol SD[7:0]
7.3.1.4
Control register, I2CCON I2CCON 8-bit read/write register. bits affected controller hardware: when serial interrupt requested, cleared when STOP condition present I2C-bus. Write I2CCON register parallel interface automatically clears bit, which causes Serial Interrupt line de-asserted next clock pulse line generated. Remark: Since none registers should written parallel interface once Serial Interrupt line been de-asserted, other registers that need modified should written before content I2CCON register modified.
Table I2CCON Control register allocation ENSIO MODE
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PCA9665
Fast-mode Plus parallel I2C-bus controller
I2CCON Control register description Assert Acknowledge flag. flag set, acknowledge (LOW level SDA) will returned during acknowledge clock pulse line when:
Table
Symbol Description
`Own slave address' been received defined I2CADR register). data byte been received while controller Master Receiver mode. data byte been received while controller addressed Slave Receiver mode.
flag reset, acknowledge (HIGH level SDA) will returned during acknowledge clock pulse when:
`Own slave address' been received defined I2CADR register). data byte been received while PCA9665 Master Receiver mode. data byte been received while PCA9665 addressed Slave Receiver mode.
When controller addressed Slave Transmitter mode, state will entered after last data byte transmitted received from Master Receiver (see Figure Figure 14). When cleared, PCA9665 enters addressed Slave Receiver mode, line remains HIGH level. state C8h, flag again future address recognition. When PCA9665 addressed slave mode, slave address ignored. Consequently, acknowledge returned, serial interrupt requested. Thus, controller temporarily released from I2C-bus while status monitored. While controller released from bus, START STOP conditions detected, serial data shifted Address recognition resumed time setting flag. ENSIO controller enable bit. ENSIO When ENSIO `0', outputs high-impedance state. input signals ignored, PCA9665 `not addressed' slave state. Internal oscillator off. ENSIO When ENSIO `1', PCA9665 enabled. After ENSIO `1', takes internal oscillator start therefore, PCA9665 will enter either master slave mode after this time. ENSIO should used temporarily release PCA9665 from I2C-bus since, when ENSIO reset, I2C-bus status lost. flag should used instead (see description flag above). following text, assumed that ENSIO Normal mode operation. power-up behavior, please refer Section 8.10 "Power-on reset".
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PCA9665
Fast-mode Plus parallel I2C-bus controller
I2CCON Control register description .continued START flag. When enter master mode, controller hardware checks status I2C-bus generates START condition free. free, then controller waits STOP condition (which will free bus) generates START condition after minimum buffer time (tBUF) elapsed. while controller already master mode more bytes transmitted received, controller transmits repeated START condition. time. also when controller addressed slave. START condition will then generated after STOP condition minimum buffer time (tBUF) elapsed. When reset, START condition repeated START condition will generated.
Table
Symbol Description
STOP flag. When while controller master mode, STOP condition transmitted I2C-bus. When STOP condition detected bus, hardware clears flag. bits both set, then STOP condition transmitted I2C-bus, PCA9665 master mode. controller then transmits START condition after minimum buffer time (tBUF) elapsed. When reset, STOP condition will generated.
Serial Interrupt flag. When flag set, and, ENSIO also set, serial interrupt requested. hardware when possible states controller states entered. only state that does cause state F8h, which indicates that relevant state information available. While set, period serial clock line stretched, serial transfer suspended. HIGH level line unaffected serial interrupt flag. automatically cleared when I2CCON register written. cannot user. When flag reset, serial interrupt requested, there stretching serial clock line.
MODE
Reserved. When I2CCON read, zeroes read. Must written with zeroes. Mode flag. MODE Byte mode. Section 8.1.1 "Byte mode" more detail. MODE buffered mode. Section 8.1.2 "Buffered mode" more detail.
Remark: ENSIO value must changed only when I2C-bus idle. 7.3.1.5 indirect data field access register, INDIRECT registers indirect address space accessed using INDIRECT data field. Before writing reading such register, INDPTR register should written with address indirect register that needs accessed. Once INDPTR register contains appropriate value, reads writes INDIRECT data field will actually read write selected indirect register.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
7.3.2 Indirect registers
7.3.2.1 Byte Count register, I2CCOUNT (indirect address 00h) I2CCOUNT register 8-bit read/write register. contains number bytes that have been stored Master/Slave Buffered Receiver mode, number bytes sent Master/Slave Buffered Transmitter mode. last byte control applies Master/Slave Buffered Receiver mode only. data I2CCOUNT register relevant only Buffered mode (MODE should used (read written) Byte mode (MODE
Table Table I2CCOUNT Byte Count register (indirect address 00h) allocation
I2CCOUNT Byte Count register (indirect address 00h) description Description Last Byte control bit. Master/Slave Buffered Receiver mode only. PCA9665 does acknowledge last received byte. PCA9665 acknowledges last received byte. future transaction must complete read sequence acknowledging last byte.
Symbol
BC[6:0]
Number bytes read written bytes). BC[6:0] equal greater than (44h), bytes will read written interrupt immediately generated after writing I2CCON register Buffered mode only).
7.3.2.2
Address register, I2CADR (indirect address 01h) I2CADR 8-bit read/write register. affected controller hardware. content this register irrelevant when controller master mode. slave modes, seven most significant bits must loaded with microcontroller's slave address least significant determines General Call address will recognized not. Remark: AD[7:1] must different from General Call address (000 0000) proper device operation.
Table Table I2CADR Address register (indirect address 01h) allocation
I2CADR Address register (indirect address 01h) description Description slave address. most significant corresponds first received from I2C-bus after START condition. logic I2CADR corresponds HIGH level I2C-bus, logic corresponds level bus. General Call. General Call address (00h) recognized. General Call address (00h) ignored.
Symbol AD[7:1]
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PCA9665
Fast-mode Plus parallel I2C-bus controller
7.3.2.3
Clock Rate registers, I2CSCLL I2CSCLH (indirect addresses 03h) I2CSCLL I2CSCLH 8-bit read/write registers. They define data rate PCA9665 when used master. actual frequency determined tHIGH (time where HIGH), tLOW (time where LOW), (rise time), (fall time) values. tHIGH tLOW calculated based values that programmed into I2CSCLH I2CSCLL registers internal oscillator frequency. system/application dependent. 2CSCLL 2CSCLH with Tosc internal oscillator period Remark: I2CMODE register needs programmed before programming I2CSCLL I2CSCLH registers order know which I2C-bus mode selected. Section 7.3.2.6 "The I2C-bus mode register, I2CMODE (indirect address 06h)" more detail. Standard mode default selected mode power-up after reset.
Table Table Table Table I2CSCLL Clock Rate register (indirect address 02h) allocation
I2CSCLL Clock Rate register (indirect address 02h) description Symbol L[7:0] Description Eight bits defining state SCL.
I2CSCLH Clock Rate High register (indirect address 03h) allocation
I2CSCLH Clock Rate High register (indirect address 03h) description Symbol H[7:0] Description Eight bits defining HIGH state SCL.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
7.3.2.4
Time-out register, I2CTO (indirect address 04h) I2CTO 8-bit read/write register. used determine maximum time that allowed logic state before I2C-bus state machine reset PCA9665 initiates forced action I2C-bus. When I2C-bus interface operating, I2CTO loaded time-out counter every transition.
Table Table I2CTO Time-out register (indirect register 04h) allocation
I2CTO Time-out register (indirect register 04h) description Symbol Description Time-out enable/disable Time-out function enabled Time-out function disabled
TO[6:0]
Time-out value. time-out period (I2CTO[6:0] 143.36 time-out value vary some, approximate value.
Time-out register used following cases:
When controller, master mode, wants send START condition
line held some other device. Then controller waits time period equivalent time-out value released. case released, controller concludes that there error, loads I2CSTA register, generates interrupt signal releases lines. After microcontroller reads status register, needs send reset order reset controller.
master mode, time-out feature starts every time goes LOW.
stays time period equal greater than time-out value, controller concludes there error behaves manner described above. When I2C-bus interface operating, I2CTO loaded time-out counter every transition. Section 8.11 "Reset" more information.
case forced access I2C-bus. (See more details Section 8.9.3 "Forced
access I2C-bus".) 7.3.2.5 Parallel Software Reset register, I2CPRESET (indirect address 05h) I2CPRESET 8-bit write-only register. Programming I2CPRESET register allows user reset PCA9665 under software control. software reset achieved writing consecutive bytes this register. first byte must while second byte must 5Ah. writes must consecutive values must match 5Ah. this sequence followed described, reset aborted.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
7.3.2.6
I2C-bus mode register, I2CMODE (indirect address 06h) I2CMODE 8-bit read/write register. contains control bits that select correct timing parameters when device used master mode (AC[1:0]). Timing parameters involved with AC[1:0] tBUF, tHD;STA, tSU;STA, tSU;STO, tHIGH, tLOW.
Table Table I2CMODE I2C-bus Mode register (indirect address 06h) allocation
I2CMODE I2C-bus Mode register (indirect address 06h) description Symbol AC[1:0] Description Reserved. When I2CMODE read, zeroes read. Must written with zeroes. I2C-bus mode selection ensure proper timing parameters (see Table 25). AC[1:0] Standard-mode parameters selected. AC[1:0] Fast-mode parameters selected. AC[1:0] Fast-mode Plus parameters selected. AC[1:0] Turbo mode. this mode, user limited maximum frequency MHz.
Remark: Change from I2C-bus mode slower (Fast mode Standard mode, example) will cause HIGH timings violated. then required program I2CSCLL I2CSCLH registers with values accordance with selected mode.
Table I2C-bus mode selection example[1] I2CSCLH (hexadecimal) I2C-bus frequency (kHz)[2] 99.9 396.8 952.3 AC[1:0] Mode Standard Fast Fast-mode Plus Turbo mode
I2CSCLL (hexadecimal)
I2CSCLL I2CSCLH values table also represents minimum values that used corresponding I2C-bus mode. lower values will cause minimum values loaded. Using formula 2CSCLL 2CSCLH
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PCA9665
Fast-mode Plus parallel I2C-bus controller
PCA9665 modes
Configuration modes
Byte mode Buffered mode selected using MODE I2CCON register: MODE Byte mode MODE Buffered mode
8.1.1 Byte mode
Byte mode allows communication single command basis. Only specific command executed time Status Register updated once this single command been performed. command START, STOP, Byte Write, Byte Read,
8.1.2 Buffered mode
Buffered mode allows several instructions executed before Interrupt generated before I2CSTA register updated. This allows microcontroller request sequence, bytes single transmission lets PCA9665 perform without having access Status Register Control Register each time single command performed. microcontroller then perform other tasks while PCA9665 performs requested sequence. number bytes that needs sent from internal buffer (Transmitter mode) received into internal buffer (Receiver mode) defined indirectly addressed I2CCOUNT Register (BC[6:0]). bytes sent received.
Operating modes
four operating modes are:
Master Transmitter Master Receiver Slave Receiver Slave Transmitter
Each mode used byte basis (Byte mode) 68-byte buffer basis (Buffered mode). Data transfers each mode operation shown Figure through Figure These figures contain following abbreviations: START condition 7-bit slave address Read (HIGH level SDA) Write (LOW level SDA) Acknowledge (LOW level SDA) acknowledge (HIGH level SDA) Data 8-bit data byte
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PCA9665
Fast-mode Plus parallel I2C-bus controller
STOP condition Figure Figure Figure Figure Figure Figure Figure Figure circles used indicate when serial interrupt flag set. serial interrupt generated when I2CSTA F8h. This happens STOP condition when external reset generated power-up, when RESET going during software reset parallel bus). numbers circles show status code held I2CSTA register. these points, service routine must executed continue complete serial transfer. These service routines critical since serial transfer suspended until serial interrupt flag cleared software. When serial interrupt routine entered, status code I2CSTA used branch appropriate service routine. each status code, required software action details following serial transfer given Table Table Table Table Table Table Table Table
Byte mode
8.3.1 Master Transmitter Byte mode
Master Transmitter Byte mode, number data bytes transmitted slave receiver (see Figure Before Master Transmitter Byte mode entered, I2CCON must initialized shown Table
Table Symbol Value I2CCON initialization (Byte mode) ENSIO MODE reserved reserved
ENSIO must logic enable PCA9665. reset, PCA9665 will acknowledge slave address event another device becoming master bus. other words, reset, PCA9665 cannot enter slave mode.) STA, STO, must reset. Once ENSIO been takes about oscillator start Master Transmitter Byte mode entered setting bit. I2C-bus state machine will first test I2C-bus generate START condition soon becomes free. When START condition transmitted, serial interrupt flag (SI) set, Interrupt line (INT) goes status code status register (I2CSTA) will 08h. This status code must used vector interrupt service routine that loads I2CDAT with slave address data direction (SLA+W). write I2CCON resets bit, clears Interrupt (INT goes HIGH) allows serial transfer continue. When slave address with direction have been transmitted, Serial Interrupt flag (SI) again, Interrupt line (INT) goes again I2CSTA loaded with following possible codes:
acknowledgment (ACK) been received acknowledgment (NACK) been received PCA9665 lost arbitration
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PCA9665
Fast-mode Plus parallel I2C-bus controller
PCA9665 lost arbitration addressed slave transmitter (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver during
General Call sequence (slave mode enabled with General Call address enabled with I2CADR register) appropriate action taken each these status codes detailed Table ENSIO affected serial transfer referred Table After repeated START condition (state 10h), PCA9665 switch Master Receiver mode loading I2CDAT with SLA+R. Remark: master should transmit slave address.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
successful transmission Slave Receiver
DATA
next transfer started with repeated START condition
Acknowledge received after slave address
Acknowledge received after data byte
Master Receiver mode entry MR(4)
arbitration lost slave address data byte
other continues
other continues
arbitration lost addressed slave
other continues
from master slave from slave master
corresponding states Slave Transmitter mode corresponding states Slave Receiver mode corresponding states Slave Receiver mode (General Call)
DATA
number data bytes their associated Acknowledge bits This number (contained I2CSTA) corresponds defined state I2C-bus.(1)
002aab024
Table Defined state when single byte sent received. Defined state when single byte sent NACK received. Master Receiver Byte mode entered when MODE Master Receiver Buffered mode entered when MODE
Format states Master Transmitter Byte mode (MODE
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Fast-mode Plus parallel I2C-bus controller
Table
Master Transmitter Byte mode (MODE Application software response To/from I2CDAT Load SLA+W Load SLA+W Load SLA+R I2CCON MODE SLA+W will transmitted; ACK/NACK will received SLA+W will transmitted; ACK/NACK will received SLA+R will transmitted; PCA9665 will switched Master Receiver Byte mode Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 START condition been transmitted repeated START condition been transmitted
SLA+W been Load data byte transmitted; been received I2CDAT action I2CDAT action I2CDAT action
Data byte will transmitted; ACK/NACK will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset Data byte will transmitted; ACK/NACK will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset Data byte will transmitted; ACK/NACK will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset
SLA+W been transmitted; NACK been received
Load data byte I2CDAT action I2CDAT action I2CDAT action
Data byte I2CDAT Load data byte been transmitted; been I2CDAT action received I2CDAT action I2CDAT action
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Fast-mode Plus parallel I2C-bus controller
Table
Master Transmitter Byte mode (MODE .continued Application software response To/from I2CDAT I2CCON MODE Data byte will transmitted; ACK/NACK will received Repeated START will transmitted; STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset I2C-bus will released; PCA9665 will enter Slave mode. I2C-bus will released; PCA9665 will enter Slave mode. START condition will transmitted when becomes free Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665
Data byte I2CDAT Load data byte been transmitted; NACK been I2CDAT action received I2CDAT action I2CDAT action
Arbitration lost I2CDAT SLA+W Data bytes action I2CDAT action I2CDAT action
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Fast-mode Plus parallel I2C-bus controller
8.3.2 Master Receiver Byte mode
Master Receiver Byte mode, number data bytes received from slave transmitter byte time (see Figure transfer initialized Master Transmitter Byte mode. Master Receiver Byte mode entered setting bit. I2C-bus state machine will first test I2C-bus generate START condition soon becomes free. When START condition transmitted, Serial Interrupt flag (SI) set, Interrupt line (INT) goes status code status register (I2CSTA) will 08h. This status code must used vector interrupt service routine that loads I2CDAT with slave address data direction (SLA+R). write I2CCON resets bit, clears Interrupt (INT goes HIGH) allows serial transfer continue. When slave address data direction have been transmitted, serial interrupt flag (SI) again, Interrupt line (INT) goes again I2CSTA loaded with following possible codes:
acknowledgment (ACK) been received slave address with
direction
acknowledgment (NACK) been received slave address with
direction
PCA9665 lost arbitration PCA9665 lost arbitration addressed slave transmitter (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver during
General Call sequence (slave mode enabled with General Call address enabled with I2CADR register). appropriate action taken each these status codes detailed Table ENSIO affected serial transfer referred Table After repeated START condition (state 10h), PCA9665 switch Master Transmitter mode loading I2CDAT with SLA+W. Remark: master should transmit slave address.
PCA9665_1
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Objective data sheet
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
successful reception from Slave Transmitter
DATA
DATA
next transfer started with repeated START condition
Acknowledge received after slave address
Master Transmitter mode entry MT(4)
arbitration lost slave address Acknowledge
other continues
other continues
arbitration lost addressed slave
other continues
from master slave from slave master number data bytes their associated Acknowledge bits
corresponding states Slave Transmitter mode corresponding states Slave Receiver mode corresponding states Slave Receiver mode (General Call)
DATA
This number (contained I2CSTA) corresponds defined state I2C-bus.(1)
002aab025
Table Defined state when single byte received sent Defined state when single byte received NACK sent Master Transmitter Byte mode entered when MODE Master Transmitter Buffered mode entered when MODE
Format states Master Receiver Byte mode (MODE
PCA9665_1
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Objective data sheet
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Table
Master Receiver Byte mode (MODE Application software response To/from I2CDAT Load SLA+R I2CCON MODE SLA+R will transmitted; ACK/NACK will received Load SLA+R Load SLA+W SLA+R will transmitted; ACK/NACK will received SLA+W will transmitted; PCA9665 will switched Master Transmitter Byte mode Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 START condition been transmitted repeated START condition been transmitted
Arbitration lost NACK
I2CDAT action I2CDAT action
I2C-bus will released; PCA9665 will enter slave mode START condition will transmitted when becomes free Data byte will received; NACK will returned Data byte will received; will returned Repeated START condition will transmitted STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset Data byte will received; NACK will returned Data byte will received; will returned Repeated START condition will transmitted STOP condition will transmitted; flag will reset STOP condition followed START condition will transmitted; flag will reset
SLA+R been transmitted; been received
I2CDAT action I2CDAT action I2CDAT action I2CDAT action I2CDAT action
SLA+R been transmitted; NACK been received
Data byte been received; been returned
Read data byte read data byte
Data byte been Read data byte received; NACK been returned read data byte read data byte
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Objective data sheet
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
8.3.3 Slave Receiver Byte mode
Slave Receiver Byte mode, number data bytes received from master transmitter byte time (see Figure initiate Slave Receiver mode, I2CADR I2CCON must loaded shown Table Table
Table Symbol Value I2CADR initialization slave address
upper bits I2C-bus address which PCA9665 will respond when addressed master. control that allows PCA9665 respond General Call address (00h). When programmed logic PCA9665 will acknowledge General Call address. When programmed logic PCA9665 will acknowledge General Call address.
Table Symbol Value I2CCON initialization ENSIO MODE
ENSIO must logic enable I2C-bus interface. must enable PCA9665 acknowledge slave address, STA, STO, must reset. When I2CADR I2CCON have been initialized, PCA9665 waits until addressed slave address followed data direction which must operate Slave Receiver mode. After slave address have been received, Serial Interrupt flag (SI) set, Interrupt line (INT) goes LOW, I2CSTA loaded with 60h. This status code used vector interrupt service routine, appropriate action taken detailed Table Slave Receiver Buffered mode also entered when:
arbitration lost while PCA9665 master mode. status
D8h.
General Call Address (00h) been received (General Call address enabled
with status D0h. reset during transfer, PCA9665 will return acknowledge (logic after next received data byte. While reset, I2C-bus state machine does respond slave address. However, I2C-bus still monitored address recognition resumed time setting This means that used temporarily isolate PCA9665 from I2C-bus.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
reception slave address more data bytes; Acknowledged. last data byte received Acknowledged
DATA
DATA
STOP
arbitration lost addressed slave
STOP
reception General Call address more data bytes
GENERAL CALL
DATA
DATA
STOP
last data byte received Acknowledged arbitration lost addressed slave General Call from master slave from slave master number data bytes their associated Acknowledge bits This number (contained I2CSTA) corresponds defined state I2C-bus.(1) STOP
DATA
002aab026
Table Defined state when single byte received sent Defined state when single byte received NACK sent
Format states Slave Receiver Byte mode (MODE
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Objective data sheet
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Table
Slave Receiver Byte mode (MODE Application software response To/from I2CDAT I2CCON I2CDAT action I2CDAT action MODE Data byte will received NACK will returned Data byte will received will returned Data byte will received NACK will returned Data byte will received will returned Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 SLA+W been received; been returned Arbitration lost SLA+R/W master; SLA+W been received, been returned General Call address (00h) been received; been returned.
I2CDAT action I2CDAT action
I2CDAT action I2CDAT action
Data byte will received NACK will returned. Data byte will received will returned. Data byte will received NACK will returned. Data byte will received will returned.
I2CDAT action Arbitration lost master; General Call I2CDAT action address been received; been returned. Read data byte Previously addressed with slave address; DATA read data byte been received; been returned Read data byte Previously addressed with slave address; DATA byte been read data byte received; NACK been returned read data byte
Data byte will received NACK will returned Data byte will received will returned
Switched addressed slave mode; recognition General Call address Switched addressed slave mode; slave address will recognized; General Call address will recognized Switched addressed slave mode; recognition slave address General Call address. START condition will transmitted when becomes free Switched addressed slave mode; slave address will recognized; General Call will recognized START condition will transmitted when becomes free.
read data byte
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Table
Slave Receiver Byte mode (MODE .continued Application software response To/from I2CDAT I2CCON Read data byte read data byte MODE Data byte will received NACK will returned. Data byte will received will returned. Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 Previously addressed with General Call; Data been received; been returned Previously addressed with General Call; Data been received; NACK been returned
Read data byte
Switched addressed slave mode; recognition slave address General Call address. Switched addressed slave mode; slave address will recognized; General Call address will recognized Switched addressed slave mode; recognition slave address General Call address. START condition will transmitted when becomes free. Switched addressed slave mode; slave address will recognized; General Call address will recognized START condition will transmitted when becomes free. Switched addressed slave mode; recognition slave address General Call address. Switched addressed slave mode; slave address will recognized; General Call will recognized Switched addressed slave mode; recognition slave address General Call. START condition will transmitted when becomes free Switched addressed slave mode; slave address will recognized; General Call will recognized START condition will transmitted when becomes free.
read data byte
read data byte
read data byte
STOP condition repeated START condition been received while still addressed Slave Receiver
I2CDAT action I2CDAT action
I2CDAT action
I2CDAT action
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PCA9665
Fast-mode Plus parallel I2C-bus controller
8.3.4 Slave Transmitter Byte mode
Slave Transmitter Byte mode, number data bytes transmitted master receiver byte time (see Figure 10). Data transfer initialized Slave Receiver Byte mode. When I2CADR I2CCON have been initialized, PCA9665 waits until addressed slave address followed data direction which must PCA9665 operate Slave Transmitter mode. After slave address have been received, Serial Interrupt flag (SI) set, Interrupt line (INT) goes I2CSTA loaded with A8h. This status code used vector interrupt service routine, appropriate action taken detailed Table Slave Transmitter Byte mode also entered arbitration lost while PCA9665 master mode. state appropriate actions Table reset during transfer, PCA9665 will transmit last byte transfer enter state C8h. PCA9665 switched addressed slave mode will ignore master receiver continues transfer. Thus master receiver receives `1's serial data. While reset, PCA9665 does respond slave address. However, I2C-bus still monitored, address recognition resumed time setting This means that used temporarily isolate from I2C-bus.
reception slave address transmission more data bytes
DATA
DATA
STOP
arbitration lost addressed slave
from master slave last data byte transmitted; switched Addressed slave I2CCON
'1's
from slave master DATA number data bytes their associated Acknowledge bits This number (contained I2CSTA) corresponds defined state I2C-bus.(1)
STOP
002aab027
Table Defined state when single byte transmitted received. Defined state when single byte transmitted NACK received. Defined state when single byte transmitted PCA9665 goes non-addressed mode received.
Format states Slave Transmitter Byte mode (MODE
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Objective data sheet
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Table
Slave Transmitter Byte mode (MODE Application software response To/from I2CDAT I2CCON Load data byte load data byte MODE Last data byte will transmitted ACK/NACK will received Data byte will transmitted; ACK/NACK will received Last data byte will transmitted ACK/NACK will received Data byte will transmitted; will received Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 SLA+R been received; been returned
Load data byte Arbitration lost SLA+R/W master; SLA+R load data byte been received, been returned Data byte I2CDAT Load data byte been transmitted; load data byte been received Data byte I2CDAT I2CDAT action been transmitted; NACK been received I2CDAT action I2CDAT action
Last data byte will transmitted ACK/NACK will received Data byte will transmitted; ACK/NACK will received Switched addressed slave mode; recognition slave address. General Call address recognized Switched slave mode; slave address will recognized. General Call address recognized Switched addressed slave mode; recognition slave address. General Call address recognized START condition will transmitted when becomes free Switched slave mode; slave address will recognized. General Call address recognized START condition will transmitted when becomes free. Switched addressed slave mode; recognition slave address. General Call address recognized Switched slave mode; slave address will recognized. General Call address recognized Switched addressed slave mode; recognition slave address. General Call address recognized START condition will transmitted when becomes free Switched slave mode; slave address will recognized. General Call address recognized START condition will transmitted when becomes free.
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I2CDAT action
I2CDAT Last data byte action I2CDAT been transmitted been received I2CDAT action I2CDAT action
I2CDAT action
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Buffered mode
8.4.1 Master Transmitter Buffered mode
Master Transmitter Buffered mode, number data bytes transmitted slave receiver several bytes time (see Figure 11). Before Master Transmitter Buffered mode entered, I2CCON must initialized shown Table
Table Symbol Value Table Symbol Value I2CCON initialization (Buffered mode) ENSIO MODE reserved reserved
I2CCOUNT programming
number bytes received single sequence byte bytes)
ENSIO must logic enable PCA9665. reset, PCA9665 will acknowledge slave address event another device becoming master other words, reset, PCA9665 cannot enter slave mode). STA, STO, must reset. Once ENSIO been logic takes about oscillator start Master Transmitter Buffered mode entered setting bit. I2C-bus state machine will first test I2C-bus generate START condition soon becomes free. When START condition transmitted, Serial Interrupt flag (SI) set, Interrupt line (INT) goes status code status register (I2CSTA) will 08h. This status code must used vector interrupt service routine that loads I2CDAT with slave address data direction (SLA+W) followed number data bytes sent. byte count register (I2CCOUNT) been previously programmed with number bytes that need sent single sequence (BC[6:0]) shown Table only used Receiver Buffered modes programmed either logic logic total number bytes loaded I2CDAT (slave address with direction plus data bytes) must equal value programmed I2CCOUNT. write I2CCON resets bit, clears Interrupt (INT goes HIGH) allows serial transfer continue. When slave address with direction part following bytes have been transmitted, Serial Interrupt flag (SI) again, Interrupt line (INT) goes again I2CSTA loaded with following possible codes:
acknowledgment (ACK) been received slave address with
direction (happens only I2CCOUNT data bytes have been sent).
acknowledgment (NACK) been received slave address with
direction data bytes have been sent).
slave address with direction data bytes have been transmitted
acknowledgement been received each them (number bytes sent equal value I2CCOUNT).
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
slave address with direction been successfully sent
acknowledgement (NACK) been received while transmitting data bytes (number total bytes sent lower than equal value I2CCOUNT).
PCA9665 lost arbitration when sending slave address with
direction when sending data bytes.
PCA9665 lost arbitration addressed slave transmitter (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver during
General Call sequence (slave mode enabled with General Call address enabled with I2CADR register). appropriate action taken each these status codes detailed Table ENSIO affected serial transfer referred Table After repeated START condition (state 10h), PCA9665 switch Master Receiver mode loading I2CDAT with SLA+R). Remark: master should transmit slave address.
PCA9665_1
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Objective data sheet
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
successful transmission Slave Receiver
DATA
next transfer started with repeated START condition
Acknowledge received after slave address
Acknowledge received after data byte
MST/REC mode entry MR(5)
arbitration lost slave address data byte
other continues
other continues
arbitration lost addressed slave
other continues
from master slave from slave master
corresponding states Slave Transmitter mode corresponding states Slave Receiver mode corresponding states Slave Receiver mode (General Call)
DATA
number data bytes their associated Acknowledge bits This number (contained I2CSTA) corresponds defined state I2C-bus.(1)
002aab659
Table Serial interrupt that occurs when BC[6:0] serial interrupt BC[6:0] Defined state when number bytes sent equal value I2CCOUNT register been received bytes sent. Defined state when NACK received while number bytes sent lower than equal value I2CCOUNT register. Master Receiver Byte mode entered when MODE Master Receiver Buffered mode entered when MODE Remark: master should never transmit slave address.
Format states Master Transmitter Buffered mode (MODE
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Philips Semiconductors
Table
Master Transmitter Buffered mode (MODE Application software response To/from I2CDAT I2CCOUNT BC[6:0] Load SLA+W data bytes I2CCON MODE SLA+W will transmitted. received, data bytes will transmitted until them have been sent been received each them until NACK received. SLA+W will transmitted. received, data bytes will transmitted until them have been sent been received each them until NACK received. SLA+R will transmitted. PCA9665 will switched Master Receiver Buffered mode. BC[6:0] data bytes will transmitted (until them have been sent been received each them until NACK received). Repeated START will transmitted. Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 START condition been transmitted repeated START condition been transmitted
Total number bytes transmitted SLA+W number data bytes) Total number bytes transmitted SLA+W number data bytes) Total number bytes received Total number data bytes transmitted
Load SLA+W data bytes
Load SLA+R
SLA+W been transmitted; been received
Load data bytes
I2CDAT action I2CDAT action I2CDAT action
Fast-mode Plus parallel I2C-bus controller
STOP condition will transmitted. flag will reset. STOP condition followed START condition will transmitted. flag will reset. BC[6:0] data bytes will transmitted (until them have been sent been received each them until NACK received). Repeated START will transmitted. STOP condition will transmitted;. flag will reset. STOP condition followed START condition will transmitted. flag will reset.
SLA+W been transmitted; NACK been received
Load data bytes
Total number data bytes transmitted
I2CDAT action I2CDAT action I2CDAT action
PCA9665
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Table Master Transmitter Buffered mode (MODE .continued Application software response To/from I2CDAT Load data bytes I2CCOUNT BC[6:0] Total number data bytes transmitted I2CCON MODE BC[6:0] data bytes will transmitted (until them have been sent been received each them until NACK received). Repeated START will transmitted. STOP condition will transmitted. flag will reset. condition followed START condition will transmitted. flag will reset.
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Philips Semiconductors
Status Status code I2C-bus (I2CSTA) PCA9665 BC[6:0] bytes I2CDAT have been transmitted; been received them
Next action taken PCA9665
I2CDAT action I2CDAT action I2CDAT action
BC[6:0] bytes Load data I2CDAT have bytes been transmitted;
Total number data bytes transmitted
NACK been received last I2CDAT action byte I2CDAT action I2CDAT action
BC[6:0] data bytes will transmitted (until them have been sent been received each them until NACK received). Repeated START will transmitted.
Fast-mode Plus parallel I2C-bus controller
STOP condition will transmitted. flag will reset. STOP condition followed START condition will transmitted. flag will reset. I2C-bus will released; PCA9665 will enter addressed slave mode. I2C-bus will released; PCA9665 will enter slave mode. START condition will transmitted when becomes free.
Arbitration lost SLA+W Data bytes
I2CDAT action I2CDAT action I2CDAT action
PCA9665
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
8.4.2 Master Receiver Buffered mode
Master Receiver Buffered mode, number data bytes received from slave transmitter several bytes time (see Figure 12). transfer initialized Master Transmitter Byte mode. Master Receiver Buffered mode entered setting bit. I2C-bus state machine will first test I2C-bus generate START condition soon becomes free. When START condition transmitted, Serial Interrupt flag (SI) set, Interrupt line (INT) goes status code status register (I2CSTA) will 08h. This status code must used vector interrupt service routine that loads I2CDAT with slave address data direction (SLA+R). byte count register (I2CCOUNT) needs programmed with number bytes that need received single sequence (BC[6:0]). programmed with logic last received byte needs acknowledged (read operation still ongoing) with logic last received byte needs acknowledged (read operation ends PCA9665 issue STOP Re-START condition). write I2CCON resets bit, clears Interrupt (INT goes HIGH) allows serial transfer continue. When slave address data direction have been transmitted data bytes have been received, Serial Interrupt flag (SI) again, Interrupt line (INT) goes again I2CSTA loaded with following possible codes:
acknowledgment (NACK) been received slave address with
direction
when bytes have been received acknowledgement (ACK)
been returned bytes
when bytes have been received acknowledgement (ACK)
been returned bytes except last
PCA9665 lost arbitration PCA9665 lost arbitration addressed slave transmitter (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver (slave
mode enabled with
PCA9665 lost arbitration addressed slave receiver during
General Call sequence (slave mode enabled with General Call address enabled with I2CADR register). appropriate action taken each these status codes detailed Table ENSIO affected serial transfer referred Table After repeated START condition (state 10h), PCA9665 switch Master Transmitter mode loading I2CDAT with SLA+W. Remark: master should transmit slave address.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
successful reception from Slave Transmitter
DATA
DATA
DATA
next transfer started with repeated START condition
Acknowledge received after slave address
Master Transmitter mode entry MT(5)
arbitration lost slave address Acknowledge
other continues
other continues
arbitration lost addressed slave
other continues corresponding states Slave Transmitter mode corresponding states Slave Receiver mode corresponding states Slave Receiver mode (General Call)
from master slave from slave master
DATA
number data bytes their associated Acknowledge bits This number (contained I2CSTA) corresponds defined state I2C-bus.(1)
002aab660
Table serial interrupt. Defined state when number bytes received equal value I2CCOUNT register. Defined state when number bytes received equal value I2CCOUNT register. Master Transmitter Byte mode entered with MODE Master Transmitter Buffered mode entered when MODE
Format states Master Receiver Buffered mode (MODE
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Table
Master Receiver Buffered mode (MODE Application software response To/from I2CDAT Load SLA+R To/from I2CCOUNT BC[6:0] I2CCON MODE SLA+R will transmitted. received, BC[6:0] data bytes will received, will returned them. SLA+R will transmitted. received, BC[6:0] data bytes will received, will returned them, except last where NACK will returned. SLA+R will transmitted. received, BC[6:0] data bytes will received, will returned them. SLA+R will transmitted. received, BC[6:0] data bytes will received, will returned them, except last where NACK will returned. SLA+W will transmitted; PCA9665 will switched Master Transmitter Buffered mode. I2C-bus will released; PCA9665 will enter slave mode. START condition will transmitted when becomes free. Repeated START condition will transmitted. STOP condition will transmitted; flag will reset. STOP condition followed START condition will transmitted; flag will reset. Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 START condition been transmitted
Total number bytes received
Total number bytes received
repeated START condition been transmitted
Load SLA+R
Total number bytes received
Total number bytes received
Fast-mode Plus parallel I2C-bus controller
Load SLA+W data bytes
Total number bytes transmitted SLA+W number data bytes)
Arbitration lost NACK
I2CDAT action I2CDAT action
SLA+R been transmitted; NACK been received
I2CDAT action I2CDAT action I2CDAT action
PCA9665
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Table Master Receiver Buffered mode (MODE .continued Application software response To/from I2CDAT Read data bytes Read data bytes Read data bytes Read data bytes Read data bytes To/from I2CCOUNT BC[6:0] I2CCON MODE BC[6:0] data bytes will received, will returned them BC[6:0] data bytes will received, will returned them, except last where NACK will returned Repeated START condition will transmitted STOP condition will transmitted; flag will reset. STOP condition followed START condition will transmitted; flag will reset. Next action taken PCA9665
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Philips Semiconductors
Status Status code I2C-bus (I2CSTA) PCA9665 BC[6:0] data bytes have been received; been returned bytes BC[6:0] data bytes have been received; been returned bytes, except last where NACK been returned
Total number bytes received Total number bytes received
Fast-mode Plus parallel I2C-bus controller
PCA9665
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
8.4.3 Slave Receiver Buffered mode
Slave Receiver Buffered mode, number data bytes received from master transmitter several bytes time (see Figure 13). initiate Slave Receiver Byte mode, I2CADR I2CCON must loaded shown Table Table
Table Symbol Value I2CADR initialization slave address
upper bits I2C-bus address which PCA9665 will respond when addressed master. control that allows PCA9665 respond General Call address (00h). When programmed logic PCA9665 will acknowledge General Call address. When programmed logic PCA9665 will acknowledge General Call address.
Table Symbol Value Table Symbol Value I2CCON initialization ENSIO MODE
I2CCOUNT programming
number bytes received single sequence byte bytes)
ENSIO must logic enable I2C-bus interface. must enable PCA9665 acknowledge slave address; STA, STO, must reset. When I2CADR I2CCON have been initialized, PCA9665 waits until addressed slave address followed data direction which must operate Slave Receiver mode. After slave address have been received, Serial Interrupt flag (SI) set, Interrupt line (INT) goes I2CSTA loaded with 60h. This status code used vector interrupt service routine, appropriate action taken detailed Table Slave Receiver Buffered mode also entered when:
arbitration lost while PCA9665 master mode. status
D8h.
General Call Address (00h) been received (General Call address enabled
with status D0h. Appropriate actions taken from these status codes also detailed Table byte count register (I2CCOUNT) programmed with number bytes that need sent single sequence (BC[6:0]) shown Table
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PCA9665
Fast-mode Plus parallel I2C-bus controller
reset (logic PCA9665 will return acknowledge bytes that will received. maximum number bytes that received single sequence defined BC[6:0] I2CCOUNT register shown Table (logic during transfer, PCA9665 will return acknowledge (logic after receiving last byte. reset, I2C-bus state machine does respond slave address. However, I2C-bus still monitored address recognition resumed time setting This means that used temporarily isolate PCA9665 from I2C-bus.
reception slave address more data bytes; Acknowledged last data byte received Acknowledged
DATA
DATA
DATA
STOP
STOP
arbitration lost addressed slave
reception General Call address more data bytes last data byte received Acknowledged
GENERAL CALL
DATA
DATA
DATA
STOP
arbitration lost addressed slave General Call from master slave
from slave master number data bytes their associated Acknowledge bits This number (contained I2CSTA) corresponds defined state I2C-bus.(1) STOP
DATA
002aab661
Table Defined state when number bytes received equal value I2CCOUNT register Defined state when number bytes received equal value I2CCOUNT register Number bytes received lower than I2CCOUNT.
Format states Slave Receiver Buffered mode (MODE
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Table
Slave Receiver Buffered mode (MODE Application software response To/from I2CDAT To/from I2CCOUNT BC[6:0] I2CDAT action I2CDAT action Total number bytes received Total number bytes received I2CCON MODE BC[6:0] data bytes will received, will returned them. BC[6:0] data bytes will received, will returned them, except last where NACK will returned (unless master transmitter sends STOP Repeated START condition before). BC[6:0] data bytes will received, will returned them. BC[6:0] data bytes will received, will returned them, except last where NACK will returned (unless master transmitter sends STOP Repeated START condition before). BC[6:0] data bytes will received, will returned them. BC[6:0] data bytes will received, will returned them, except last where NACK will returned (unless master transmitter sends STOP Repeated START condition before). BC[6:0] data bytes will received, will returned them. BC[6:0] data bytes will received, will returned them, except last where NACK will returned (unless master transmitter sends STOP Repeated START condition before). Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 SLA+W been received; been returned
I2CDAT action Arbitration lost SLA+R/W master; SLA+W been received; been returned I2CDAT action
Total number bytes received Total number bytes received
General Call address I2CDAT action (00h) been received; been returned. I2CDAT action
Total number bytes received Total number bytes received
Fast-mode Plus parallel I2C-bus controller
Arbitration lost master;
I2CDAT action
Total number bytes received Total number bytes received
General Call address I2CDAT action been received; been returned.
PCA9665
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Table Slave Receiver Buffered mode (MODE .continued Application software response To/from I2CDAT To/from I2CCOUNT BC[6:0] Total number bytes received Total number bytes received I2CCON MODE BC[6:0] data bytes will received, will returned them. BC[6:0] data bytes will received, will returned them, except last where NACK will returned (unless master transmitter sends STOP Repeated START condition before). Switched addressed slave mode; recognition slave address; General Call address will recognized Switched addressed slave mode; slave address will recognized; General Call address will recognized Switched addressed slave mode; recognition slave address; General Call address will recognized START condition will transmitted when becomes free. Switched addressed slave mode; slave address will recognized; General Call address will recognized START condition will transmitted when becomes free. BC[6:0] data bytes will received, will returned them. BC[6:0] data bytes will received, will returned them, except last where NACK will returned (unless master transmitter sends STOP Repeated START condition before). Next action taken PCA9665
Objective data sheet Rev. August 2006
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Philips Semiconductors
Status Status code I2C-bus (I2CSTA) PCA9665
Previously addressed Read data bytes with slave address; BC[6:0] data bytes have been received; been returned bytes Read data bytes
Previously addressed Read data bytes with slave address; BC[6:0] data bytes have been received; been returned bytes, except last where NACK been returned Read data bytes Read data bytes
Fast-mode Plus parallel I2C-bus controller
Read data bytes
Previously addressed Read data bytes with General Call; BC[6:0] data bytes have been received; Read data bytes been returned bytes
Total number bytes received Total number bytes received
PCA9665
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Table Slave Receiver Buffered mode (MODE .continued Application software response To/from I2CDAT Read data bytes Read data bytes Read data bytes To/from I2CCOUNT BC[6:0] I2CCON MODE Switched addressed slave mode; recognition slave address; General Call address will recognized Switched addressed slave mode; slave address will recognized; General Call address will recognized Switched addressed slave mode; recognition slave address; General Call address will recognized START condition will transmitted when becomes free. Switched addressed slave mode; slave address will recognized; General Call address will recognized START condition will transmitted when becomes free. Switched addressed slave mode; recognition slave address; General Call address will recognized Switched addressed slave mode; slave address will recognized; General Call address will recognized Switched addressed slave mode; recognition slave address; General Call address will recognized START condition will transmitted when becomes free. Switched addressed slave mode; slave address will recognized; General Call address will recognized START condition will transmitted when becomes free. Next action taken PCA9665
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Philips Semiconductors
Status Status code I2C-bus (I2CSTA) PCA9665 Previously addressed with General Call; BC[6:0] data bytes have been received; been returned bytes, except last where NACK been returned
Read data bytes
STOP condition repeated START condition been received while still addressed slave receiver
I2CDAT action I2CDAT action I2CDAT action
Fast-mode Plus parallel I2C-bus controller
I2CDAT action
PCA9665
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
8.4.4 Slave Transmitter Buffered mode
Slave Transmitter Buffered mode, number data bytes transmitted master receiver several bytes time (see Figure 14). Data transfer initialized Slave Receiver Buffered mode. When I2CADR I2CCON have been initialized, PCA9665 waits until addressed slave address followed data direction which must PCA9665 operate Slave Transmitter mode. After slave address have been received, Serial Interrupt flag (SI) set, Interrupt line (INT) goes I2CSTA loaded with A8h. This status code used vector interrupt service routine, appropriate action taken detailed Table Slave Transmitter Buffered mode also entered arbitration lost while PCA9665 master mode. state appropriate actions Table byte count register (I2CCOUNT) programmed with number bytes that need sent single sequence (BC[6:0]) shown Table only used Receiver Buffered modes programmed either logic logic reset during transfer, PCA9665 will transmit bytes transfer (values defined BC[6:0]) enter state C8h. PCA9665 switched addressed slave mode will ignore master receiver continues transfer. Thus master receiver receives `1's serial data. While reset, PCA9665 does respond slave address. However, I2C-bus still monitored, address recognition resumed time setting This means that used temporarily isolate PCA9665 from I2C-bus.
reception slave address transmission more data bytes
DATA
DATA
STOP
arbitration lost addressed slave
from master slave last data byte transmitted; switched Addressed slave I2CCON '1's
from slave master number data bytes their associated Acknowledge bits
DATA
STOP
002aab662
This number (contained I2CSTA) corresponds defined state I2C-bus.(1)
Table Defined state when number bytes sent equal value I2CCOUNT register. Defined state when NACK received. number bytes transmitted lower than equal value I2CCOUNT register. Defined state after last byte been transmitted PCA9665 goes non-addressed mode received. number bytes that transmitted equal value I2CCOUNT register.
Format states Slave Transmitter Buffered mode (MODE
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Objective data sheet Rev. August 2006
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Philips Semiconductors
Table
Slave Transmitter Buffered mode (MODE Application software response To/from I2CDAT Load data bytes To/from I2CCOUNT BC[6:0] I2CCON MODE BC[6:0] bytes will transmitted. PCA9665 switches addressed mode after BC[6:0] bytes have been transmitted. BC[6:0] bytes will transmitted. BC[6:0] bytes will transmitted. PCA9665 switches addressed mode after BC[6:0] bytes have been transmitted BC[6:0] bytes will transmitted. BC[6:0] bytes will transmitted. PCA9665 switches addressed mode after BC[6:0] bytes have been transmitted BC[6:0] bytes will transmitted. Switched addressed slave mode; recognition slave address; General Call address recognized Switched slave mode; slave address will recognized; General Call address recognized Switched addressed slave mode; recognition slave address; General Call address will recognized START condition will transmitted when becomes free Switched slave mode; slave address will recognized; General Call address will recognized START condition will transmitted when becomes free Next action taken PCA9665
Status Status code I2C-bus (I2CSTA) PCA9665 SLA+R been received; been returned
Total number data bytes transmitted
Load data bytes Arbitration lost SLA+R/W master; SLA+R been received, been returned BC[6:0] bytes I2CDAT have been transmitted; been received BC[6:0] bytes I2CDAT have been transmitted; NACK been received Load data bytes
Total number data bytes transmitted Total number data bytes transmitted
Load data bytes Load data bytes
Total number data bytes transmitted Total number data bytes transmitted
Load data bytes
Total number data bytes transmitted
Fast-mode Plus parallel I2C-bus controller
I2CDAT action I2CDAT action I2CDAT action
PCA9665
I2CDAT action
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Table Slave Transmitter Buffered mode (MODE .continued Application software response To/from I2CDAT To/from I2CCOUNT BC[6:0] I2CDAT action I2CDAT action I2CDAT action I2CCON MODE Switched addressed slave mode; recognition slave address; General Call address recognized Switched slave mode; slave address will recognized; General Call address recognized Switched addressed slave mode; recognition slave address; General Call address will recognized START condition will transmitted when becomes free. Switched slave mode; slave address will recognized; General Call address will recognized START condition will transmitted when becomes free. Next action taken PCA9665
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Philips Semiconductors
Status Status code I2C-bus (I2CSTA) PCA9665 BC[6:0] bytes I2CDAT have been transmitted been received
I2CDAT action
Fast-mode Plus parallel I2C-bus controller
PCA9665
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Buffered mode examples
8.5.1 Buffered Master Transmitter mode operation
Program I2CCOUNT register with number bytes that need sent I2C-bus (BC[6:0] value from 44h). used Receiver mode only Load data bytes I2CDAT buffer. different bytes sent will stored PCA9665 buffer. There protection against writing over buffer's boundary. more than bytes written buffer, data address will overwritten. number bytes that needs loaded I2CDAT equal BC[6:0] I2CCOUNT register. number data bytes sent equal BC[6:0], therefore, number data bytes loaded greater than BC[6:0], additional data will sent. number data bytes written buffer less than BC[6:0], PCA9665 will still send BC[6:0] data bytes. Program I2CCON register initiate Master Transmitter Buffered sequence. Master mode, START command sent. interrupt will asserted I2CCON register after START been sent. I2CSTA register contains status transmission. MODE must each time write I2CCON register performed. After reading I2CSTA status register, I2CCON programmed with That clears previous Interrupt. START command been previously sent, first byte loaded into buffer sent I2C-bus interpreted I2C-bus address operation. transmitter mode, following bytes that sent I2C-bus interpreted data bytes. When sequence been executed, Interrupt asserted I2CCON register. I2CSTA register contains status transmission I2CCOUNT register contains number bytes that have been sent I2C-bus described Table More sequence (program I2CCOUNT register, load data bytes I2CDAT buffer, write I2CCON register send data I2C-bus, read I2CSTA register when sequence been executed) performed long STOP Repeated START command been sent. Master Transmitter Buffered mode ends when I2CCOUNT register programmed with
8.5.2 Buffered Master Receiver mode operation
Program I2CCOUNT register with number bytes that need read from slave device I2C-bus (BC[6:0] value from 44h). used Receiver mode PCA9665 know last byte received must acknowledged not. Last received byte acknowledged another sequence executed. Last received byte acknowledged. last sequence before sending STOP Repeated START must executed with Load I2C-bus address I2CDAT buffer.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Program I2CCON register initiate Master Receiver Buffered sequence. Master mode, START command sent. interrupt will asserted I2CCON register after START been sent. I2CSTA register contains status transmission. MODE must each time write I2CCON register performed. After reading I2CSTA status register, I2CCON programmed with That clears previous Interrupt. START command been previously sent, I2C-bus address byte that been loaded into buffer sent I2C-bus, PCA9665 then becomes master receiver device starts receiving data from addressed slave device. Remark: PCA9665 already master receiver device buffered sequence been previously executed. When sequence been executed, Interrupt asserted I2CCON register. I2CSTA register contains status transmission I2CCOUNT register contains number bytes that have been received. I2CDAT buffer contains data that been received read microcontroller. More sequences (program I2CCOUNT register, write I2CCON register, read I2CSTA register when sequence been executed, read I2CDAT buffer) performed long STOP Repeated START command been sent. able reception, last buffered sequence must performed with Master Receiver Buffered mode ends when I2CCOUNT register programmed with
8.5.3 Buffered Slave Transmitter mode
interrupt asserted I2CCON register when PCA9665's slave address been detected I2C-bus slave address defined I2CADR register). Slave Transmitter mode, Program I2CCOUNT register with number bytes that need sent I2C-bus (BC[6:0] value from 44h). used Receiver Buffered mode only. Load data bytes I2CDAT buffer. different bytes sent will stored PCA9665 buffer. There protection against writing over buffer's boundary. more than bytes written buffer, data address will overwritten. number bytes that needs loaded I2CDAT equal BC[6:0] I2CCOUNT register. number data bytes sent equal BC[6:0], therefore, number data bytes loaded greater than BC[6:0], additional data will sent. number data bytes written buffer less than BC[6:0], PCA9665 will still send BC[6:0] data bytes. I2CCON programmed clear previous Interrupt. bytes loaded into buffer sent I2C-bus. MODE bits must each time write I2CCON register performed. When sequence been executed (BC[6:0] bytes sent master sent NACK), Interrupt asserted I2CCON register. I2CSTA register contains status transmission I2CCOUNT register contains number bytes that have been sent I2C-bus.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
More sequences (program I2CCOUNT register, load data bytes I2CDAT buffer, write I2CCON register send data I2C-bus, read I2CSTA register when sequence been executed) performed long master acknowledges bytes sent PCA9665 Slave Transmitter Buffered mode ends when I2C-bus master does acknowledge byte when PCA9665 goes Non-addressed Slave mode.
8.5.4 Buffered Slave Receiver mode
interrupt asserted I2CCON register when PCA9665`s slave address been detected I2C-bus slave address defined I2CADR register). Slave Receiver mode, Program I2CCOUNT register with number bytes that needs read from master device I2C-bus (BC[6:0] value from 44h). used Receiver mode PCA9665 know last byte received must acknowledged not. Last received byte acknowledged another sequence executed. Last received byte acknowledged. I2CCON programmed clear previous Interrupt. PCA9665 receives data from I2C-bus master. MODE must each time write I2CCON register performed. When sequence been executed (BC[6:0] bytes have been received master sent STOP Repeated START command), Interrupt asserted I2CCON register. I2CSTA register contains status transmission I2CCOUNT register contains number bytes that have been received. I2CDAT buffer contains data that been received read microcontroller. More sequence (program I2CCOUNT register, write I2CCON register, read I2CDAT buffer) performed long STOP Repeated START command been sent I2C-bus master. Slave Receiver Buffered mode ends when I2C-bus master sends STOP Repeated START command, when PCA9665 does acknowledge received bytes more.
8.5.5 Example: Read bytes 64-byte sequences EEPROM (I2C-bus address write operations read operations) starting Location
Program I2CCOUNT bytes sent): I2C-bus slave address memory allocation. Write (I2C-bus slave address write command) (Location) into I2CDAT register. Program I2CCON with MODE PCA9665 sends START command PCA9665 sends interrupt, sets updates I2CSTA register I2CSTA reads Program I2CCON with MODE I2C-bus slave address A0h, then EEPROM address sent
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
line held PCA9665 after bytes have been sent PCA9665 sends Interrupt, sets updates I2CSTA register I2CSTA reads Program I2CCOUNT bytes read Last byte acknowledged). Load I2CDAT with (I2C-bus slave address Read command). Program I2CCON with MODE PCA9665 sends ReSTART command interrupt asserted I2CSTA register updated I2CSTA register reads Program I2CCON with MODE address sent followed read data bytes last data byte acknowledged line held PCA9665 after data read PCA9665 sends interrupt updates I2CSTA register I2CSTA reads microcontroller reads data bytes from PCA9665. Program I2CCOUNT bytes Last byte acknowledged). Program I2CCON with MODE PCA9665 reads bytes does acknowledge last byte. PCA9665 sends Interrupt updates I2CSTA register I2CSTA reads line held PCA9665 slave should release line microcontroller reads bytes from PCA9665. Program I2CCON with MODE PCA9665 sends STOP condition interrupt generated PCA9665 I2CSTA register contains
I2CCOUNT register
When write I2CCOUNT register requested, buffer pointer reset points first byte. Loading data I2CDAT buffer then starts first byte. Once operation been performed interrupt generated), I2CCOUNT register contains number bytes that have been received (Receiver mode) number bytes that have been sent (Transmitter mode). Table more information. Buffered Transmitter mode, first byte that sent I2C-bus always first byte that been loaded I2CDAT buffer.
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Buffered Receiver mode, when interrupt generated (after STOP command buffer full condition), buffer pointer reset points first received data byte. Reading I2CCOUNT register then indicates number bytes that have been sent received (BC[6:0]). Reading data from I2CDAT buffer then initiated starting with first received byte.
Table I2CCOUNT register value based performed operation I2CCOUNT register value don't care don't care there interrupt after slave address sent) there interrupt after slave address sent) Master Receiver Buffered mode After START condition After Slave Address Sent received After Slave Address Sent NACK received don't care don't care (because interrupt received here)
Operation performed Master Transmitter Buffered mode After START condition After Slave Address Sent received interrupt received After Slave Address Sent NACK received After Slave Address Sent data bytes sent, received, both address data After Slave Address Sent data bytes sent, last byte After STOP After losing arbitration Slave Address addressed slave After losing arbitration data byte
After losing arbitration slave address addressed slave
After Slave Address Sent data bytes received, received address returned data bytes After Slave Address Sent data bytes received, NACK returned last byte After STOP don't care
After losing arbitration Slave Address addressed slave After losing arbitration slave address addressed slave After losing arbitration byte Slave Receiver Buffered mode (regular slave mode General Call response After Slave Address returned slave address (both regular mode when PCA9665 loses arbitration addressed slave) After receiving bytes, returned bytes After receiving bytes, NACK returned last byte Slave Transmitter Buffered mode After Slave Address returned slave address (both regular mode when PCA9665 loses arbitration addressed slave) After data bytes transmitted received bytes After data bytes transmitted NACK received last byte
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Remark: Request send receive number bytes equal higher than (BC[6:0] 0000 BC[6:0] 0100) will cause data transferred interrupt generated after writing I2CCON register. I2CSTA status register loaded with that indicates that invalid value requested loaded I2CCOUNT.
Acknowledge management (I2C-bus addresses data) Byte Buffered modes
Data acknowledge/not acknowledge management controlled byte basis (Byte mode) sequence basis (Buffered mode). PCA9665 programmed respond (ACK) (NACK) different I2C-bus addresses. Table shows this performed based different control bits (AA, MODE) different modes.
Table slave address, General Call address, Data acknowledge management MODE Address applicable applicable applicable applicable Data received[1] data (each byte) NACK data (each byte) bytes (BC[6:0] bytes) bytes except last (BC[6:0] bytes ACK; last byte NACK data (each byte) NACK data (each byte) bytes BC[6:0] bytes) bytes except last (BC[6:0] bytes ACK; last byte NACK[2] bytes BC[6:0] bytes) bytes except last (BC[6:0] bytes ACK; last byte NACK[2] data (each byte) NACK data (each byte) NACK data (each byte) data (each byte) NACK bytes BC[6:0] bytes) bytes except last (BC[6:0] bytes ACK; last byte NACK[2]
Master mode: PCA9665 generates START command controls I2C-bus
Slave mode: I2C-bus message starting with PCA9665's Slave address address NACK address address NACK address NACK
address address
Slave mode: I2C-bus message starting with General Call address address NACK address address address NACK address address
Assumption that Data Received follows address defined column "Address"); valid slave mode only. Unless master sends STOP command before.
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Table Control bits
Unbuffered Mode (MODE Master Transmitter mode Master Receiver mode
address/data transmitted byte basis
address transmitted data received byte basis NACK returned after byte received NACK returned after slave address received NACK returned after byte received
Slave Transmitter mode
Slave Receiver mode
NACK returned after slave address received switch addressed slave mode time during I2C-bus sequence address/data transmitted byte basis
Master Transmitter mode
Master Receiver mode data received byte basis returned after byte received returned after slave address received returned after byte received
Slave Transmitter mode
Slave Receiver mode
returned after slave address received always addressed during I2C-bus sequence
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Table Control bits
Buffered Mode (MODE Master Transmitter mode Master Receiver mode Master Transmitter mode Master Receiver mode
address/data transmitted multiple byte basis BC[6:0] value
address transmitted data received multiple byte basis BC[6:0] value returned after last byte buffered sequence received (after bytes received BC[6:0] value)
address/data transmitted multiple byte basis BC[6:0] value
address transmitted data received multiple byte basis BC[6:0] value NACK returned after last byte buffered sequence received (after bytes received BC[6:0] value) NACK returned after slave address received addressed mode, data received multiple byte basis BC[6:0] value addressed mode, NACK returned after last byte buffered sequence received (after bytes received BC[6:0] value) addressed mode, switch non-addressed mode after last byte buffered sequence received (after bytes received BC[6:0] value)
Slave Transmitter mode
Slave Receiver mode
Slave Transmitter mode
Slave Receiver mode
NACK returned after slave address received addressed mode, data transmitted multiple byte basis BC[6:0] value addressed mode, switch addressed mode after last byte buffered sequence transmitted (after bytes sent BC[6:0] value)
NACK returned after slave address received addressed mode, data received multiple byte basis BC[6:0] value addressed mode, returned after last byte buffered sequence received (after bytes received BC[6:0] value) addressed mode, switch non-addressed mode after last byte buffered sequence received (after bytes received BC[6:0] value)
NACK returned after slave address received addressed mode, data transmitted multiple byte basis BC[6:0] value addressed mode, switch addressed mode after last byte buffered sequence transmitted (after bytes sent BC[6:0] value)
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Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Table Control bits
Buffered Mode (MODE .continued Master Transmitter mode Master Receiver mode Master Transmitter mode Master Receiver mode
address/data transmitted multiple byte basis BC[6:0] value
address transmitted data received multiple byte basis BC[6:0] value returned after last byte buffered sequence received (after bytes received BC[6:0] value)
address/data transmitted multiple byte basis BC[6:0] value
address transmitted data received multiple byte basis BC[6:0] value NACK returned after last byte buffered sequence received (after bytes received BC[6:0] value) returned after slave address received addressed mode, data received multiple byte basis BC[6:0] value addressed mode, NACK returned after last byte buffered sequence received (after bytes received BC[6:0] value)
Slave Transmitter mode
Slave Receiver mode
Slave Transmitter mode
Slave Receiver mode
returned after slave address received addressed mode, data transmitted multiple byte basis BC[6:0] value always addressed during buffered sequence
returned after slave address received addressed mode, data received multiple byte basis BC[6:0] value addressed mode, returned after last byte buffered sequence received (after bytes received BC[6:0] value)
returned after slave address received addressed mode, data transmitted multiple byte basis BC[6:0] value always addressed during buffered sequence
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PCA9665
Fast-mode Plus parallel I2C-bus controller
Miscellaneous states
There four I2CSTA codes that correspond defined PCA9665 state (see Table 46). These discussed Section 8.8.1 through Section 8.8.4.
Table Miscellaneous states Next action taken PCA9665 MODE into master mode; send START recognition slave address. General Call address will recognized Will recognize slave address. General Call address will recognized Hardware software reset PCA9665 (requires reset return state F8h) Hardware software reset PCA9665 (requires reset return state F8h) Program valid value I2CCOUNT: BC[6:0] between Hardware software reset PCA9665 (requires reset return state F8h)
Status Status I2C-bus Application software response code PCA9665 To/from I2CDAT I2CCON (I2CSTA) hardware software reset STOP I2CDAT action I2CDAT action
I2CDAT action
error stuck
I2CDAT action I2CCON action
error stuck
I2CDAT action I2CCON action
Illegal value I2CCOUNT
I2CDAT action I2CCON action
I2CDAT action I2CCON action error during master slave mode, illegal START STOP condition
8.8.1 I2CSTA
This status code indicates that PCA9665 idle state that relevant information available because serial interrupt flag, set. This occurs STOP condition during hardware software reset event when PCA9665 involved serial transfer.
8.8.2 I2CSTA
This status code indicates that error occurred during serial transfer. error caused when START STOP condition occurs illegal position format frame. Examples such illegal positions during serial transfer address byte, data byte, acknowledge bit. error also caused when external interference disturbs internal PCA9665 signals. When error occurs, set. recover from error, microcontroller must send external hardware software reset signal reset PCA9665.
8.8.3 I2CSTA
This status code indicates that line stuck when PCA9665, master mode, trying send START condition.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
8.8.4 I2CSTA
This status code indicates that line stuck LOW.
Some special cases
PCA9665 facilities handle following special cases that occur during serial transfer.
8.9.1 Simultaneous repeated START conditions from masters
repeated START condition generated Master Transmitter Master Receiver modes. special case occurs another master simultaneously generates repeated START condition (see Figure 15). Until this occurs, arbitration lost either master since they were both transmitting same data. PCA9665 detects repeated START condition I2C-bus before generating repeated START condition itself, will repeated START continue with sending slave address.
DATA
both masters continue with transmission
other master sends repeated START condition earlier
002aab028
Simultaneous repeated START conditions from masters
8.9.2 Data transfer after loss arbitration
Arbitration lost Master Transmitter Master Receiver modes. Loss arbitration indicated following states I2CSTA; 38h, 68h, (see Figure Figure Figure Figure 12). Remark: order exit state 38h, Time-out, Reset, external STOP required. flag I2CCON routines which service these states, then, free again, START condition (state 08h) transmitted without intervention CPU, retry total serial transfer commence.
8.9.3 Forced access I2C-bus
some applications, possible uncontrolled source cause hang-up. such situations, problem caused interference, temporary interruption temporary short-circuit between SCL. uncontrolled source generates superfluous START masks STOP condition, then I2C-bus stays busy indefinitely. flag access obtained within reasonable amount time, then forced access I2C-bus possible. I2C-bus stays idle time period equal time-out period, then PCA9665 concludes that other master using sends START condition.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
time-out flag
line
line START condition
002aab029
Forced access busy I2C-bus
8.9.4 I2C-bus obstructed level
I2C-bus hang-up occurs pulled uncontrolled source. line obstructed (pulled LOW) device bus, further serial transfer possible, PCA9665 cannot resolve this type problem. When this occurs, problem must resolved device that pulling line LOW. When line stays period equal time-out value, PCA9665 concludes that this error behaves manner described Section 7.3.2.4 "The Time-out register, I2CTO (indirect address 04h)". line obstructed another device (e.g., slave device synchronization), problem solved transmitting additional clock pulses line (see Figure 17). PCA9665 sends nine clock pulses followed STOP condition. line released slave pulling LOW, normal START condition transmitted PCA9665, state entered serial transfer continues. line released slave pulling LOW, then PCA9665 concludes that there error, loads I2CSTA, generates interrupt signal, releases lines. After microcontroller reads status register, needs send reset signal (hardware through RESET pin, software through parallel port) order reset PCA9665. Section 8.11 "Reset" more information. forced access occurs repeated START condition transmitted while obstructed (pulled LOW), PCA9665 performs same action described above. each case, state entered after successful START condition transmitted normal serial transfer continues. Note that involved solving these hang-up problems.
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PCA9665
Fast-mode Plus parallel I2C-bus controller
flag
line
line
STOP condition
START condition
002aab030
Recovering from obstruction caused level
8.9.5 error
error occurs when START STOP condition present illegal position format frame. Examples illegal positions during serial transfer address byte, data acknowledge bit. PCA9665 only reacts error when involved serial transfer either master addressed slave. When error detected, PCA9665 releases lines, sets interrupt flag, loads status register with 00h. This status code used vector service routine which either attempts aborted serial transfer again simply recovers from error condition shown Table "Miscellaneous states". microcontroller must send external hardware software reset signal reset PCA9665.
8.10 Power-on reset
When power applied VDD, internal Power-On Reset holds PCA9665 reset condition until reached VPOR. this point, reset condition released PCA9665 goes power-up initialization phase where following operations performed: ENSIO enable internal oscillator. Internal register initialization performed. ENSIO disable internal oscillator non-addressed power mode. complete power-up initialization phase takes performed. During this time, write PCA9665 through parallel port permitted. However, parallel port read. This allows device connected parallel port PCA9665 poll I2CCON register read ENSIO state bit. When ENSIO equal this means that power-up initialization progress. When ENSIO this means that power-up initialization done that PCA9665 initialized ready used.
PCA9665_1
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Objective data sheet
Rev. August 2006
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
8.11 Reset
Reset PCA9665 default state performed different ways:
holding RESET minimum tw(rst). using Parallel Software Reset sequence described Figure
access INDPTR Indirect Register pointer A[1:0] I2CPRESET register selected D[7:0] SWRST data byte access INDIRECT Indirect Data field SWRST data byte
D[7:0] A5h, following byte ignored reset aborted. internal reset signal D[7:0] 5Ah, reset aborted. SWRST Data SWRST Data 5Ah, PCA9665 reset default state.
002aab966
Parallel Software Reset sequence
8.12 I2C-bus timing diagrams, Unbuffered mode
diagrams (Figure through Figure illustrate typical timing diagrams PCA9665 master/slave functions.
7-bit address START condition from slave receiver interrupt first byte interrupt byte interrupt STOP condition
002aab031
Master PCA9665 writes data slave transmitter.
timing diagram; Unbuffered Master Transmitter mode
PCA9665_1
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Objective data sheet
Rev. August 2006
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
7-bit address START condition from slave interrupt first byte interrupt byte from master receiver STOP condition
002aab032
Master PCA9665 reads data from slave transmitter.
timing diagram; Unbuffered Master Receiver mode
7-bit address(1)
interrupt
first byte
interrupt
byte
interrupt STOP condition
002aab033
START condition from slave PCA9665
from master receiver
External master receiver reads data from PCA9665. defined I2CADR register.
timing diagram; Unbuffered Slave Transmitter mode
7-bit address(1)
interrupt
first byte
interrupt
byte
interrupt
interrupt (after STOP) STOP condition
002aab034
START condition from slave PCA9665
Slave PCA9665 written external master transmitter. defined I2CADR register.
timing diagram; Unbuffered Slave Receiver mode
PCA9665_1
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Objective data sheet
Rev. August 2006
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
8.13 I2C-bus timing diagrams, Buffered mode
diagrams (Figure through Figure illustrate typical timing diagrams PCA9665 master/slave functions.
7-bit address(1) first byte(1) byte(1) interrupt STOP condition
002aab267
START condition from slave receiver
Master PCA9665 writes data slave transmitter. 7-bit address byte number bytes sent value programmed I2CCOUNT register (BC[6:0] 68).
timing diagram; Buffered Master Transmitter mode
7-bit address START condition from slave first byte(1) byte(1) from master receiver STOP condition
002aab268
Master PCA9665 reads data from slave transmitter. Number bytes received value programmed I2CCOUNT register (BC[6:0] 68).
timing diagram; Buffered Master Receiver mode
PCA9665_1
Koninklijke Philips Electronics N.V. 2006. rights reserved.
Objective data sheet
Rev. August 2006
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
7-bit address(1)
interrupt
first byte(2)
byte(2) from master receiver
interrupt STOP condition
002aab269
START condition from slave PCA9665
External master receiver reads data from PCA9665. defined I2CADR register. Number bytes received value programmed I2CCOUNT register (BC[6:0] 68).
timing diagram; Buffered Slave Transmitter mode
7-bit address(1)
interrupt
first byte(2)
byte(2)
interrupt
interrupt (after STOP) STOP condition
002aab270
START condition from slave PCA9665
Slave PCA9665 written external master transmitter. defined I2CADR register. Number bytes received value programmed I2CCOUNT register (BC[6:0] 68).
timing diagram; Buffered Slave Receiver mode
7-bit SWRST Call address
interrupt
first byte 0xA5
second byte 0x5A
interrupt (after STOP) STOP condition
002aab488
START condition from slave PCA9665
timing diagram; Software Reset Call
PCA9665_1 Koninklijke Philips Electronics N.V. 2006. rights reserved.
Objective data sheet
Rev. August 2006
Philips Semiconductors
PCA9665
Fast-mode Plus parallel I2C-bus controller
Characteristics I2C-bus
I2C-bus 2-way, 2-line communication between different modules. lines serial data line (SDA) serial clock line (SCL). Both lines must connected positive supply pull-up resistor when connected output stages device. Data transfer initiated only when busy.
transfer
data transferred during each clock pulse. data line must remain stable during HIGH period clock pulse changes data line this time will interpreted control signals (see Figure 28).
data line stable; data valid change data allowed
mba607
transfer
9.1.1 START STOP conditions
Both data clock lines remain HIGH when busy. HIGH-to-LOW transition data line while clock HIGH defined START condition (S). LOW-to-HIGH transition data line while clock HIGH defined STOP condition (see Figure 29).
START condition STOP condition
mba608
Definition START STOP conditions
System configuration
device generating message `transmitter'; device receiving `receiver'. device that controls message `master' devices which controlled master `slaves' (see Figure 30).
PCA9665_1
Koninklijke Philips Electronics N.V. 2006. right
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