PowerNPNP2G Network Processor February 2003 Copyright Discla
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PowerNPNP2G Network Processor
February 2003
Copyright Disclaimer
Copyright International Business Machines Corporation 2003 Rights Reserved
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Printed United States America February 2003
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np2_ds_title.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Contents
About This Book
Should Read This Manual Related Publications Conventions Used This Manual
General Information
Features Ordering Information Overview NP2G-Based Systems Structure 1.5.1 Structure 1.5.1.1 Coprocessors 1.5.1.2 Enhanced Threads 1.5.1.3 Hardware Accelerators 1.5.2 NP2G Memory Data Flow 1.6.1 Basic Data Flow 1.6.2 Data Flow
Physical Description
Information 2.1.1 Ingress-to-Egress Wrap (IEW) Pins 2.1.2 Flow Control Interface Pins 2.1.3 Interface Pins 2.1.4 DRAM Interface Pins 2.1.4.1 Interface Pins 2.1.4.2 D4_0 D4_1 Interface Pins 2.1.4.3 D6_x Interface Pins 2.1.4.4 Interface Pins 2.1.5 Interface Pins 2.1.5.1 Pins 2.1.5.2 GMII Pins 2.1.5.3 SMII Pins 2.1.6 Pins 2.1.7 Management Interface Pins 2.1.8 Miscellaneous Pins 2.1.9 Filter Circuit 2.1.10 Thermal Usage 2.1.10.1 Temperature Calculation 2.1.10.2 Measurement Calibration Clocking Domains Mechanical Specifications IEEE 1149 (JTAG) Compliance 2.4.1 Statement JTAG Compliance 2.4.2 JTAG Compliance Mode
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2.4.3 JTAG Implementation Specifics 2.4.4 Brief Overview JTAG Instructions Signal Lists
Physical Multiplexer
Ethernet Overview 3.1.1 Ethernet Interface Timing Diagrams 3.1.2 Ethernet Counters 3.1.3 Ethernet Support Overview 3.2.1 Timing Diagrams 3.2.2 Counters 3.2.3 Support
Ingress Enqueuer Dequeuer Scheduler
Overview Operation 4.2.1 Operational Details Ingress Flow Control 4.3.1 Flow Control Hardware Facilities 4.3.2 Hardware Function 4.3.2.1 Exponentially Weighted Moving Average (EWMA) 4.3.2.2 Flow Control Hardware Actions
Ingress-to-Egress Wrap
Ingress Cell Data Mover 5.1.1 Cell Header 5.1.2 Frame Header Ingress Cell Interface Egress Cell Interface Egress Cell Data Mover
Egress Enqueuer Dequeuer Scheduler
Functional Blocks Operation Egress Flow Control 6.3.1 Flow Control Hardware Facilities 6.3.2 Remote Egress Status 6.3.2.1 Sequence Timing 6.3.2.2 Configuration 6.3.3 Hardware Function 6.3.3.1 Exponentially Weighted Moving Average 6.3.3.2 Flow Control Hardware Actions Egress Scheduler 6.4.1 Egress Scheduler Components 6.4.1.1 Scheduling Calendars 6.4.1.2 Flow Queues
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6.4.1.3 Target Port Queues 6.4.2 Configuring Flow Queues 6.4.2.1 Additional Configuration Notes 6.4.3 Scheduler Accuracy Capacity
Embedded Processor Complex
Overview 7.1.1 Thread Types Dyadic Protocol Processor Unit (DPPU) 7.2.1 Core Language Processor (CLP) 7.2.1.1 Core Language Processor Address 7.2.2 Opcode Formats 7.2.3 DPPU Coprocessors 7.2.4 Shared Memory Pool Opcode Formats 7.3.1 Control Opcodes 7.3.1.1 Opcode 7.3.1.2 Exit Opcode 7.3.1.3 Test Branch Opcode 7.3.1.4 Branch Link Opcode 7.3.1.5 Return Opcode 7.3.1.6 Branch Register Opcode 7.3.1.7 Branch Relative Opcode 7.3.1.8 Branch Reg+Off Opcode 7.3.2 Data Movement Opcodes 7.3.2.1 Memory Indirect Opcode 7.3.2.2 Memory Address Indirect Opcode 7.3.2.3 Memory Direct Opcode 7.3.2.4 Scalar Access Opcode 7.3.2.5 Scalar Immediate Opcode 7.3.2.6 Transfer Quadword Opcode 7.3.2.7 Zero Array Opcode 7.3.3 Coprocessor Execution Opcodes 7.3.3.1 Execute Direct Opcode 7.3.3.2 Execute Indirect Opcode 7.3.3.3 Execute Direct Conditional Opcode 7.3.3.4 Execute Indirect Conditional Opcode 7.3.3.5 Wait Opcode 7.3.3.6 Wait Branch Opcode 7.3.4 Opcodes 7.3.4.1 Arithmetic Immediate Opcode 7.3.4.2 Logical Immediate Opcode 7.3.4.3 Compare Immediate Opcode 7.3.4.4 Load Immediate Opcode 7.3.4.5 Arithmetic Register Opcode 7.3.4.6 Count Leading Zeros Opcode DPPU Coprocessors 7.4.1 Tree Search Engine Coprocessor 7.4.2 Data Store Coprocessor 7.4.2.1 Data Store Coprocessor Address
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7.4.2.2 Data Store Coprocessor Commands 7.4.3 Control Access (CAB) Coprocessor 7.4.3.1 Coprocessor Address 7.4.3.2 Access NP2G Structures 7.4.3.3 Coprocessor Commands 7.4.4 Enqueue Coprocessor 7.4.4.1 Enqueue Coprocessor Address 7.4.4.2 Enqueue Coprocessor Commands 7.4.5 Checksum Coprocessor 7.4.5.1 Checksum Coprocessor Address 7.4.5.2 Checksum Coprocessor Commands 7.4.6 String Copy Coprocessor 7.4.6.1 String Copy Coprocessor Address 7.4.6.2 String Copy Coprocessor Commands 7.4.7 Policy Coprocessor 7.4.7.1 Policy Coprocessor Address 7.4.7.2 Policy Coprocessor Commands 7.4.8 Counter Coprocessor 7.4.8.1 Counter Coprocessor Address 7.4.8.2 Counter Coprocessor Commands 7.4.9 Coprocessor Response 7.4.9.1 Coprocessor Response Address 7.4.9.2 Coprocessor Response Commands 7.4.9.3 14-bit Coprocessor Response 7.4.10 Semaphore Coprocessor 7.4.10.1 Semaphore Coprocessor Commands 7.4.10.2 Error Conditions 7.4.10.3 Software Models Interrupts Timers 7.5.1 Interrupts 7.5.1.1 Interrupt Vector Registers 7.5.1.2 Interrupt Mask Registers 7.5.1.3 Interrupt Target Registers 7.5.1.4 Software Interrupt Registers 7.5.2 Timers 7.5.2.1 Timer Interrupt Counters Dispatch Unit 7.6.1 Port Configuration Memory 7.6.1.1 Port Configuration Memory Index Definition 7.6.2 Port Configuration Memory Contents Definition 7.6.3 Completion Unit Hardware Classifier 7.7.1 Ingress Classification 7.7.1.1 Ingress Classification Input 7.7.1.2 Ingress Classification Output 7.7.2 Egress Classification 7.7.2.1 Egress Classification Input 7.7.2.2 Egress Classification Output 7.7.3 Completion Unit Label Generation Policy Manager
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Counter Manager 7.9.1 Counter Manager Usage 7.10 Semaphore Manager
Tree Search Engine
Overview 8.1.1 Addressing Control Store (CS) 8.1.2 Control Store. 8.1.3 Logical Memory Views 8.1.4 Control Store Restrictions 8.1.5 Object Shapes 8.1.6 Illegal Memory Access 8.1.7 Memory Range Checking (Address Bounds Check) Trees Tree Searches 8.2.1 Input Color Register Trees 8.2.2 Input Color Register Trees 8.2.3 Direct Table 8.2.3.1 Pattern Search Control Blocks (PSCB) 8.2.3.2 Leaves Compare-at-End Operation 8.2.3.3 Cascade/Cache 8.2.3.4 Cache Flag NrPSCBs Registers 8.2.3.5 Cache Management 8.2.3.6 Search Output 8.2.4 Tree Search Algorithms 8.2.4.1 Trees 8.2.4.2 Trees 8.2.4.3 PSCB Structure Memory 8.2.4.4 Compact PSCB Support 8.2.4.5 Trees with Multibit Compare 8.2.4.6 Trees 8.2.4.7 Compare-at-End Operation 8.2.4.8 Ropes 8.2.4.9 Aging 8.2.5 Tree Configuration Initialization 8.2.5.1 LUDefTable 8.2.5.2 Free Lists (TSE_FL) 8.2.6 Registers Register 8.2.7 Instructions 8.2.7.1 Tree Search (TS_FM) 8.2.7.2 Tree Search (TS_LPM) 8.2.7.3 Tree Search (TS_SMT) 8.2.7.4 Memory Read (MRD) 8.2.7.5 Memory Write (MWR) 8.2.7.6 Hash (HK) 8.2.7.7 Read LUDefTable (RDLUDEF) 8.2.7.8 Compare-at-End (COMPEND) 8.2.7.9 Distinguish Position Fast Table Update (DISTPOS_GDH) 8.2.7.10 Read PSCB Fast Table Update (RDPSCB_GDH) 8.2.7.11 Write PSCB Fast Table Update (WRPSCB_GDH) 8.2.7.12 SetPatBit_GDH
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8.2.8 Hardware Assist Instructions 8.2.8.1 Hash (HK_GTH) 8.2.8.2 Read LUDefTable (RDLUDEF GTH) 8.2.8.3 Tree Search Enqueue Free List (TSENQFL) 8.2.8.4 Tree Search Dequeue Free List (TSDQFL) 8.2.8.5 Read Current Leaf from Rope (RCLR) 8.2.8.6 Advance Rope with Optional Delete Leaf (ARDL) 8.2.8.7 Tree Leaf Insert Rope (TLIR) 8.2.8.8 Clear PSCB (CLRPSCB) 8.2.8.9 Read PSCB (RDPSCB) 8.2.8.10 Write PSCB (WRPSCB) 8.2.8.11 Push PSCB (PUSHPSCB) 8.2.8.12 Distinguish (DISTPOS) 8.2.8.13 TSR0 Pattern (TSR0PAT) 8.2.8.14 Pattern 2DTA (PAT2DTA) 8.2.9 Hash Functions
Serial Parallel Manager Interface
Interface Components Interface Data Flow Interface Protocol Address Space 9.4.1 Byte Access Space 9.4.2 Word Access Space 9.4.3 EEPROM Access Space 9.4.3.1 EEPROM Single-Byte Access 9.4.3.2 EEPROM 2-Byte Access 9.4.3.3 EEPROM 3-Byte Access 9.4.3.4 EEPROM 4-Byte Access
Embedded PowerPCSubsystem
10.1 Description 10.2 Processor Local Device Control Register Buses 10.2.1 Processor Local (PLB) 10.2.2 Device Control Register (DCR) 10.3 Address 10.4 Address 10.5 Universal Interrupt Controller (UIC) Macro 10.6 PCI/PLB Bridge Macro 10.7 Interface Macro 10.7.1 PowerPC Address (PwrPC_CAB_Addr) Register 10.7.2 PowerPC Data (PwrPC_CAB_Data) Register 10.7.3 PowerPC Control (PwrPC_CAB_Cntl) Register 10.7.4 PowerPC Status (PwrPC_CAB_Status) Register 10.7.5 PowerPC Mask (PwrPC_CAB_Mask) Register 10.7.6 PowerPC Write Under Mask Data (PwrPC_CAB_WUM_Data) 10.7.7 Host Address (Host_CAB_Addr) Register 10.7.8 Host Data (Host_CAB_Data) Register 10.7.9 Host Control (Host_CAB_Cntl) Register
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10.7.10 Host Status (Host_CAB_Status) Register 10.7.11 Host Mask (Host_CAB_Mask) Register 10.7.12 Host Write Under Mask Data (Host_CAB_WUM_Data) Register 10.8 Mailbox Communications DRAM Interface Macro 10.8.1 Mailbox Communications Between Host PowerPC Subsystem 10.8.2 Interrupt Status (PCI_Interr_Status) Register 10.8.3 Interrupt Enable (PCI_Interr_Ena) Register 10.8.4 PowerPC Subsystem Host Message Resource (P2H_Msg_Resource) Register 10.8.5 PowerPC Subsystem Host Message Address (P2H_Msg_Addr) Register 10.8.6 PowerPC Subsystem Host Doorbell (P2H_Doorbell) Register 10.8.7 Host PowerPC Subsystem Message Address (H2P_Msg_Addr) Register 10.8.8 Host PowerPC Subsystem Doorbell (H2P_Doorbell) Register 10.8.9 Mailbox Communications Between PowerPC Subsystem 10.8.10 PowerPC Subsystem Resource (E2P_Msg_Resource) Register 10.8.11 PowerPC Subsystem Message Address (E2P_Msg_Addr) Register 10.8.12 PowerPC Subsystem Doorbell (E2P_Doorbell) Register 10.8.13 Interrupt Vector Register 10.8.14 Interrupt Mask Register 10.8.15 PowerPC Subsystem Message Address (P2E_Msg_Addr) Register 10.8.16 PowerPC Subsystem Doorbell (P2E_Doorbell) Register 10.8.17 Mailbox Communications Between Host 10.8.18 Host Resource (E2H_Msg_Resource) Register 10.8.19 Host Message Address (E2H_Msg_Addr) Register 10.8.20 Host Doorbell (E2H_Doorbell) Register 10.8.21 Host Message Address (H2E_Msg_Addr) Register 10.8.22 Host Doorbell (H2E_Doorbell) Register 10.8.23 Message Status (Msg_Status) Register 10.8.24 PowerPC Boot Redirection Instruction Registers (Boot_Redir_Inst) 10.8.25 PowerPC Machine Check (PwrPC_Mach_Chk) Register 10.8.26 Parity Error Status Reporting 10.8.27 Slave Error Address Register (SEAR) 10.8.28 Slave Error Status Register (SESR) 10.8.29 Parity Error Counter (Perr_Count) Register 10.9 System Start-Up Initialization 10.9.1 NP2G Resets 10.9.2 Systems Initialized External Host Processors 10.9.3 Systems with Host Processors Initialized PowerPC Subsystem 10.9.4 Systems Without Host Processors Initialized PowerPC Subsystem 10.9.5 Systems Without Host Delayed Configuration Initialized
Reset Initialization
11.1 Overview 11.2 Step I/Os 11.3 Step Reset NP2G 11.4 Step Boot 11.4.1 Boot Embedded Processor Complex (EPC) 11.4.2 Boot PowerPC 11.4.3 Boot Summary 11.5 Step Setup
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11.6 Step Diagnostics 11.7 Step Setup 11.8 Step Hardware Initialization 11.9 Step Diagnostics 11.10 Step Operational 11.11 Step Configure 11.12 Step Initialization Complete
Debug Facilities
12.1 Debugging Picoprocessors 12.1.1 Single Step 12.1.2 Break Points 12.1.3 Accessible Registers 12.2 RISCWatch
Configuration
13.1 Memory Configuration 13.1.1 Memory Configuration Register (Memory_Config) 13.1.2 DRAM Parameter Register (DRAM_Parm) 13.1.3 Delay Calibration Registers 13.2 Toggle Mode Register 13.3 Format Register 13.3.1 Toggle Mode 13.3.1.1 information 13.3.1.2 ENQE Command Qclass 13.4 Egress Reassembly Sequence Check Register (E_Reassembly_Seq_Ck) 13.5 Aborted Frame Reassembly Action Control Register (AFRAC) 13.6 Packing Registers 13.6.1 Packing Control Register (Pack_Ctrl) 13.6.2 Packing Delay Register (Pack_Dly) 13.7 Initialization Control Registers 13.7.1 Initialization Register (Init) 13.7.2 Initialization Done Register (Init_Done) 13.8 NP2G Ready Register (NPR_Ready) 13.9 Phase-Locked Loop Registers 13.9.1 Phase-Locked Loop Fail Register (PLL_Lock_Fail) 13.10 Software Controlled Reset Register (Soft_Reset) 13.11 Ingress Free Queue Threshold Configuration 13.11.1 BCB_FQ Threshold Registers 13.11.2 BCB_FQ Threshold Guided Traffic (BCB_FQ_Th_GT) 13.11.3 BCB_FQ_Threshold_0 Register (BCB_FQ_TH_0) 13.11.4 BCB_FQ_Threshold_1 Register (BCB_FQ_TH_1) 13.11.5 BCB_FQ_Threshold_2 Register (BCB_FQ_Th_2) 13.12 I-GDQ Threshold Register (I-GDQ_Th) 13.13 Ingress Target Data Storage Register (I_TDMU_DSU) 13.14 Embedded Processor Complex Configuration 13.14.1 PowerPC Core Reset Register (PowerPC_Reset) 13.14.2 PowerPC Boot Redirection Instruction Registers (Boot_Redir_Inst)
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13.14.3 Watch Reset Enable Register (WD_Reset_Ena) 13.14.4 Boot Override Register (Boot_Override) 13.14.5 Thread Enable Register (Thread_Enable) 13.14.6 Data Disable Register (GFH_Data_Dis) 13.14.7 Ingress Maximum Entries (I_Max_DCB) 13.14.8 Egress Maximum Entries (E_Max_DCB) 13.14.9 Ordered Semaphore Enable Register (Ordered_Sem_Ena) 13.14.10 Enhanced Classification Enable Register (Enh_HWC_Ena) 13.15 Flow Control Structures 13.15.1 Ingress Flow Control Hardware Structures 13.15.1.1 Ingress Transmit Probability Memory Register (I_Tx_Prob_Mem) 13.15.1.2 Ingress pseudorandom Number Register (I_Rand_Num) 13.15.1.3 Free Queue Thresholds Register (FQ_Th) 13.15.2 Egress Flow Control Structures 13.15.2.1 Egress Transmit Probability Memory (E_Tx_Prob_Mem) Register 13.15.2.2 Egress pseudorandom Number (E_Rand_Num) 13.15.2.3 Twin Count Threshold (P0_Twin_Th) 13.15.2.4 Twin Count Threshold (P1_Twin_Th) 13.15.2.5 Egress Twin Count EWMA Threshold Register (E_P0_Twin_EWMA_Th) 13.15.2.6 Egress Twin Count EWMA Threshold Register (E_P1_Twin_EWMA_Th) 13.15.3 Exponentially Weighted Moving Average Constant Register (EWMA_K) 13.15.4 Exponentially Weighted Moving Average Sample Period Register (EWMA_T) 13.15.5 Flow Control Force Discard Register (FC_Force_Discard) 13.16 Egress Stack Threshold Register (E_CDM_Stack_Th) 13.17 Free Queue Extended Stack Maximum Size (FQ_ES_Max) Register 13.18 Egress Free Queue Thresholds 13.18.1 FQ_ES_Threshold_0 Register (FQ_ES_Th_0) 13.18.2 FQ_ES_Threshold_1 Register (FQ_ES_Th_1) 13.18.3 FQ_ES_Threshold_2 Register (FQ_ES_Th_2) 13.19 Egress Frame Data Queue Thresholds (E_GRx_GBx_th) 13.20 Discard Flow Register (Discard_QCB) 13.21 Bandwidth Allocation Register (BW_Alloc_Reg) 13.22 Miscellaneous Controls Register (MISC_CNTRL) 13.23 Frame Control Block Size Register (FCB_FQ_Max) 13.24 Data Mover Unit (DMU) Configuration Registers 13.25 Frame Configuration Register (DMU_Pad) 13.26 Ethernet Jumbo Frame Size Register (EN_Jumbo_FS) 13.27 Accuracy Register (QD_Acc) 13.28 Packet Over SONET Control Register (POS_Ctrl) 13.28.1 Initial Value Determination 13.29 Packet Over SONET Maximum Frame Size (POS_Max_FS) 13.30 Ethernet Encapsulation Type Register Control (E_Type_C) 13.31 Ethernet Encapsulation Type Register Data (E_Type_D) 13.32 Source Address Array (SA_Array) 13.33 Destination Address Array (DA_Array) 13.34 Programmable Register (PIO_Reg) 13.35 Ingress-to-Egress Wrap Configuration Registers 13.35.1 Configuration Register (IEW_Config1)
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13.35.2 Configuration Register (IEW_Config2) 13.35.3 Initialization Register (IEW_Init)
Electrical Thermal Specifications
14.1 Driver Specifications 14.2 Receiver Specifications 14.3 Other Driver Receiver Specifications
Glossary Terms Abbreviations Revision
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List Tables
Table 2-1. Signal Functions Table 2-2. Ingress-to-Egress Wrap (IEW) Pins Table 2-3. Flow Control Pins Table 2-4. SRAM Interface Pins Table 2-5. SRAM Interface Pins Table 2-6. SRAM Timing Diagram Legend (for Figure 2-2) Table 2-7. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Table 2-8. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Table 2-9. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Table 2-10. Interface Pins Table 2-11. Memory Pins Table 2-12. D4_0 D4_1 Interface Pins Table 2-13. D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins Table 2-14. Interface Pins Table 2-15. Interface Pins Table 2-16. Interface Multiplexing Table 2-17. Interface Pins: Debug (DMU_D Only) Table 2-18. Parallel Data 8B/10B Position Mapping (TBI Interface) Table 2-19. Interface Pins: Mode Table 2-20. Timing Diagram Legend (for Figure 2-8) Table 2-21. Interface Pins: GMII Mode Table 2-22. GMII Timing Diagram Legend (for Figure 2-9) Table 2-23. Interface Pins: SMII Mode Table 2-24. SMII Timing Diagram Legend (for Figure 2-10) Table 2-25. Signals Table 2-26. Timing Diagram Legend (for Figure 2-11 Figure 2-12) Table 2-27. Pins Table 2-28. Timing Diagram Legend (for Figure 2-13) Table 2-29. Management Pins Table 2-30. Timing Diagram Legend (for Figure 2-14) Table 2-31. Miscellaneous Pins Table 2-32. Signals Requiring Pull-Up Pull-Down Table 2-33. Pins Requiring Connections Other Pins Table 2-34. Alternate Wiring Pins Requiring Connections Other Pins Table 2-35. Mechanical Specifications Table 2-36. JTAG Compliance-Enable Inputs Table 2-37. Implemented JTAG Public Instructions Table 2-38. Complete Signal Listing Signal Name
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Table 2-39. Complete Signal Listing Grid Position Table 3-1. Ingress Ethernet Counters .112 Table 3-2. Egress Ethernet Counters .114 Table 3-3. Ethernet Support .117 Table 3-4. Framer Configurations .118 Table 3-5. Receive Counter Addresses Ingress .122 Table 3-6. Transmit Counter Addresses Egress .124 Table 3-7. Support .126 Table 4-1. Flow Control Hardware Facilities .133 Table 5-1. Cell Header Fields .137 Table 5-2. Frame Header Fields .139 Table 6-1. Flow Control Hardware Facilities .148 Table 6-2. Flow Queue Parameters .152 Table 6-3. Valid Combinations Scheduler Parameters .152 Table 6-4. Configure Flow .158 Table 7-1. Core Language Processor Address .169 Table 7-2. Shared Memory Pool .172 Table 7-3. Condition Codes (Cond Field) .173 Table 7-4. AluOp Field Definition .193 Table 7-5. Field Definition .195 Table 7-6. Arithmetic Opcode Functions .199 Table 7-7. Coprocessor Instruction Format .203 Table 7-8. Data Store Coprocessor Address .204 Table 7-9. Ingress DataPool Byte Address Definitions .206 Table 7-10. Egress Frames DataPool Quadword Addresses .208 Table 7-11. DataPool Byte Addressing with Cell Header Skip .209 Table 7-12. Number Frame-bytes DataPool .210 Table 7-13. WREDS Input .212 Table 7-14. WREDS Output .212 Table 7-15. RDEDS Input .213 Table 7-16. RDEDS Output .214 Table 7-17. WRIDS Input .214 Table 7-18. WRIDS Output .214 Table 7-19. RDIDS Input .215 Table 7-20. RDIDS Output .215 Table 7-21. RDMOREE Input .216 Table 7-22. RDMOREE Output .216 Table 7-23. RDMOREI Input .217 Table 7-24. RDMOREI Output .217
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Table 7-25. LEASETWIN Output Table 7-26. EDIRTY Inputs Table 7-27. EDIRTY Output Table 7-28. IDIRTY Inputs Table 7-29. IDIRTY Output Table 7-30. Coprocessor Address Table 7-31. Address Field Definitions Table 7-32. Address, Functional Island Encoding Table 7-33. CABARB Input Table 7-34. CABACCESS Input Table 7-35. CABACCESS Output Table 7-36. Enqueue Coprocessor Address Table 7-37. Ingress FCBPage Description Table 7-38. Egress FCBPage Description Table 7-39. ENQE Target Queues Table 7-40. Egress Target Queue Selection Coding Table 7-41. Egress Target Queue Parameters Table 7-42. Type Field Discard Queue Table 7-43. ENQE Command Input Table 7-44. Egress Queue Class Definitions Table 7-45. ENQI Target Queues Table 7-46. Ingress Target Queue Selection Coding Table 7-47. Ingress Target Queue FCBPage Parameters Table 7-48. ENQI Command Input Table 7-49. Ingress-Queue Class Definition Table 7-50. ENQCLR Command Input Table 7-51. ENQCLR Output Table 7-52. RELEASE_LABEL Output Table 7-53. Checksum Coprocessor Address Table 7-54. GENGEN/GENGENX Command Inputs Table 7-55. GENGEN/GENGENX/GENIP/GENIPX Command Outputs Table 7-56. GENIP/GENIPX Command Inputs Table 7-57. CHKGEN/CHKGENX Command Inputs Table 7-58. CHKGEN/CHKGENX/CHKIP/CHKIPX Command Outputs Table 7-59. CHKIP/CHKIPX Command Inputs Table 7-60. String Copy Coprocessor Address Table 7-61. StrCopy Command Input Table 7-62. StrCopy Command Output Table 7-63. Policy Coprocessor Address
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Table 7-64. PolAccess Input .248 Table 7-65. PolAccess Output .248 Table 7-66. Counter Coprocessor Address .248 Table 7-67. Ctrinc Input .249 Table 7-68. CtrRInc Input .250 Table 7-69. CtrAdd Input .250 Table 7-70. CtrRAdd Input .250 Table 7-71. CtrRd/CtrRdClr Input .251 Table 7-72. CtrRd/CtrRdClr Output .251 Table 7-73. CtrWr15_0/CtrWr31_16 Input .251 Table 7-74. Coprocessor Response Coprocessor Address .252 Table 7-75. Coprocessor Response Coprocessor Command Summary .252 Table 7-76. CrbSetBusy Output .252 Table 7-77. 14-bit Response Cycle Definition .253 Table 7-78. Semaphore Lock Input .254 Table 7-79. Semaphore Unlock Input .254 Table 7-80. Reservation Release Input .254 Table 7-81. Priority Assignments Dispatch Unit Queue Arbiter .260 Table 7-82. Port Configuration Memory Index .261 Table 7-83. Relationship Between Field, Queue, Port Configuration Memory Index .262 Table 7-84. Port Configuration Memory Content .262 Table 7-85. Protocol Identifiers .265 Table 7-86. HCCIA Table .266 Table 7-87. Protocol Identifiers Frame Encapsulation Types .267 Table 7-88. General Purpose Register Definitions Ingress Classification Flags .268 Table 7-89. Flow Control Information Values .269 Table 7-90. HCCIA Index Definition .270 Table 7-91. General Purpose Register Definitions Egress Classification Flags .270 Table 7-92. Completion Unit Label .271 Table 7-93. PolCB Field Definitions .273 Table 7-94. Counter Manager Components .277 Table 7-95. Counter Types .277 Table 7-96. Counter Actions .277 Table 7-97. Counter Definition Entry Format .278 Table 7-98. Counter Manager Passed Parameters .281 Table 7-99. Counter Manager Address Bits .281 Table 8-1. Control Store Address Mapping References .285 Table 8-2. Address .285 Table 8-3. Control Store Addressing .287
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Table 8-4. DTEntry, PSCB, Leaf Shaping Table 8-5. Height, Width, Offset Restrictions Objects Table 8-6. Tree Fixed Leaf Formats Table 8-7. Tree Fixed Leaf Formats Table 8-8. Search Input Parameters Table 8-9. Cache Status Registers Table 8-10. Search Output Parameters Table 8-11. DTEntry PSCBLine Formats Table 8-12. DTEntry PSCBLine Formats Table 8-13. NLASMT Field Format Table 8-14. CompDefTable Entry Format Table 8-15. LUDefTable Rope Parameters Table 8-16. NLARope Field Format Table 8-17. LUDefTable Entry Definitions Table 8-18. Free List Entry Definition Table 8-19. Scalar Registers Only Table 8-20. Array Registers Table 8-21. Registers (Tree Management) Table 8-22. Scalar Registers Table 8-23. PSCB Register Format Table 8-24. Indirect Registers Table 8-25. Address PSCB0-2 Registers Table 8-26. General Instructions Table 8-27. Tree Search Input Operands Table 8-28. Tree Search Results (TSR) Output Table 8-29. Tree Search Input Operands Table 8-30. Tree Search Results Output Table 8-31. Tree Search Input Operands Table 8-32. Tree Search Results Output Table 8-33. Memory Read Input Operands Table 8-34. Memory Read Output Results Table 8-35. Memory Write Input Operands Table 8-36. Hash Input Operands Table 8-37. Hash Output Results Table 8-38. RDLUDEF Input Operands Table 8-39. RDLUDEF Output Results Table 8-40. COMPEND Input Operands Table 8-41. COMPEND Output Results Table 8-42. DISTPOS_GDH Input Operands
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Table 8-43. DISTPOS_GDH Output Results .328 Table 8-44. RDPSCB_GDH Input Operands .329 Table 8-45. RDPSCB_GDH Output Results .330 Table 8-46. WRPSCB_GDH Input Operands .330 Table 8-47. WRPSCB_GDH Output Results .331 Table 8-48. SetPatBit_GDH Input Operands .332 Table 8-49. SetPatBit_GDH Output Results .332 Table 8-50. General Instructions .333 Table 8-51. Hash Input Operands .334 Table 8-52. Hash Output Results .334 Table 8-53. RDLUDEF_GTH Input Operands .335 Table 8-54. RDLUDEF_GTH Output Results .335 Table 8-55. TSENQFL Input Operands .335 Table 8-56. TSENQFL Output Results .335 Table 8-57. TSDQFL Input Operands .336 Table 8-58. TSDQFL Output Results .336 Table 8-59. RCLR Input Operands .337 Table 8-60. RCLR Output Results .337 Table 8-61. ARDL Input Operands .337 Table 8-62. ARDL Output Results .338 Table 8-63. TLIR Input Operands .338 Table 8-64. TLIR Output Results .338 Table 8-65. CLRPSCB Input Operands .338 Table 8-66. CLRPSCB Output Results .339 Table 8-67. RDPSCB Input Operands .339 Table 8-68. RDPSCB Output Results .339 Table 8-69. WRPSCB Input Operands .340 Table 8-70. PUSHPSCB Input Operands .340 Table 8-71. PUSHPSCB Output Results .340 Table 8-72. DISTPOS Input Operands .341 Table 8-73. DISTPOS Output Results .341 Table 8-74. TSR0PAT Input Operands .341 Table 8-75. TSR0PAT Output Results .341 Table 8-76. PAT2DTA Input Operands .342 Table 8-77. PAT2DTA Output Results .342 Table 8-78. General Hash Functions .342 Table 9-1. Field Definitions Addresses .357 Table 10-1. Master Connections .362 Table 10-2. Device Control Registers .363
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Table 10-3. Address Interface Macro Table 10-4. Address Mailbox DRAM Interface Macro Table 10-5. Address Mailbox DRAM Interface Macro Table 10-6. Interrupt Assignments Table 10-7. NP2G Device Configuration Header Values Table 10-8. Address PCI/PLB Macro Table 10-9. PCI/PLB Bridge Macro Configuration Registers Table 10-10. Reset Domains Table 11-1. Reset Initialization Sequence Table 11-2. I/Os Checklist Table 11-3. Setup Checklist Table 11-4. Diagnostics Checklist Table 11-5. Setup Checklist Table 11-6. Hardware Initialization Checklist Table 11-7. Diagnostic Checklist Table 11-8. Configure Checklist Table 14-1. Absolute Maximum Ratings Table 14-2. Input Capacitance (pF) Table 14-3. Operating Supply Voltages Table 14-4. Operating Supply Currents Table 14-5. Thermal Characteristics Table 14-6. Definition Terms Table 14-7. CMOS Driver Voltage Specifications Table 14-8. CMOS Driver Minimum Currents Rated Voltage Table 14-9. CMOS Driver Voltage Specifications Table 14-10. CMOS Driver Minimum Currents Rated Voltage Table 14-11. V-Tolerant CMOS Driver Voltage Specifications Table 14-12. LVTTL Driver Voltage Specifications Table 14-13. LVTTL/5.0 V-Tolerant Driver Voltage Specifications Table 14-14. LVTTL Driver Minimum Currents Rated Voltage Table 14-15. CMOS Receiver Voltage Specifications Table 14-16. CMOS Receiver Voltage Specifications Table 14-17. LVTTL Receiver Voltage Specifications Table 14-18. LVTTL Tolerant Receiver Voltage Specifications Table 14-19. Receiver Maximum Input Leakage Current Input Specifications Table 14-20. LVDS Receiver Specifications Table 14-21. SSTL2 Specifications
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List Figures
Figure 1-1. Function Placement NP2G-Based System Figure 1-2. NP2G Major Functional Blocks Figure 1-3. Data Flow Overview Figure 1-4. Basic Data Flow Figure 2-1. Device Interfaces Figure 2-2. SRAM Timing Diagram Figure 2-3. Control Timing Diagram Figure 2-4. Read Timing Diagram Figure 2-5. Write Output Timing Diagram Figure 2-6. NP2G Clock Connections Figure 2-7. NP2G Clock Connections (POS Overview) Figure 2-8. Timing Diagram Figure 2-9. GMII Timing Diagram Figure 2-10. SMII Timing Diagram Figure 2-11. Transmit Timing Diagram Figure 2-12. Receive Timing Diagram Figure 2-13. Timing Diagram Figure 2-14. Timing Diagram Figure 2-15. Alternate Wiring Pins Requiring Connection Other Pins Figure 2-16. Filter Circuit Diagram Figure 2-17. Thermal Monitor Figure 2-18. Clock Generation Distribution Figure 2-19. Pins Diagram Figure 2-20. Mechanical Diagram Figure 3-1. Overview Figure 3-2. Ethernet Mode Figure 3-3. SMII Timing Diagram Figure 3-4. GMII Timing Diagram Figure 3-5. Timing Diagram Figure 3-6. GMII Mode Timing Diagram Figure 3-7. OC-3 OC-3c OC-12 Configuration Figure 3-8. Receive POS8 Interface Timing 8-bit Data (OC-3c) Figure 3-9. Transmit POS8 Interface Timing 8-bit Data (OC-3c) Figure 3-10. Receive POS8 Interface Timing 8-bit Data (OC-12c) Figure 3-11. Transmit POS8 Interface Timing 8-bit Data (OC-12c) Figure 4-1. Logical Organization Ingress Data Flow Management Figure 4-2. Ring Structure Figure 4-3. Ingress Logical Structure
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Figure 5-1. Ingress-to Egress Wrap Functional Blocks .135 Figure 5-2. Cell Header Format .136 Figure 5-3. Frame Header Format .138 Figure 6-1. Egress Functional Blocks .142 Figure 6-2. Cell Formats Storage Egress .145 Figure 6-3. TPQ, FCB, Egress Frame Example .146 Figure 6-4. Timing .149 Figure 6-5. Egress Scheduler .153 Figure 7-1. Embedded Processor Complex Block Diagram .164 Figure 7-2. Dyadic Protocol Processor Unit Functional Blocks .167 Figure 7-3. Core Language Processor .169 Figure 7-4. Field Definition: Loading Halfword/Word GPRs from Halfword/Word Array .178 Figure 7-5. Field Definition: Loading Byte From Array Byte .179 Figure 7-6. Field Definition: Loading Halfword/Word from Array Byte .180 Figure 7-7. FIeld Definition: Store Byte/Halfword/Word Array Byte/Halfword/Word .181 Figure 7-8. ot3i Field Definition .194 Figure 7-9. ot2i Field Definition: Compare Halfword/Word Immediate .196 Figure 7-10. ot4i Field Definition Load Immediate Halfword/Word .197 Figure 7-11. ot4i Field Definition: Load Immediate Byte .198 Figure 7-12. ot3r Field Definition .200 Figure 7-13. Frame Ingress Data Store .207 Figure 7-14. Frame Egress Data Store .208 Figure 7-15. Ingress FCBPage Format .225 Figure 7-16. Egress FCBPage Format .228 Figure 7-17. Dispatch Unit .259 Figure 7-18. Split between Picocode Hardware Policy Manager .272 Figure 7-19. Counter Manager Block Diagram .276 Figure 7-20. Counter Definition Entry .279 Figure 7-21. Counter Blocks Sets .280 Figure 8-1. Example Shaping Dimensions .289 Figure 8-2. Effects Using Direct Table .294 Figure 8-3. Example PSCB Detail Layout Memory .298 Figure 8-4. Example PSCB Compact PSCB Layout Memory .300 Figure 8-5. Multibit PSCB Detail Layout .302 Figure 8-6. Example Multibit Tree Layout .303 Figure 8-7. Example Input Leaf Pattern Fields .304 Figure 8-8. Rope Structure .306 Figure 8-9. General Layout Fields Shared Memory Pool .316 Figure 8-10. General Layout RDLUDEF Shared Memory Pool .325
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Figure 8-11. Shared Memory Pool with DISTPOS_GDH Command Subfields Figure 8-12. Shared Memory Pool with PSCB Subfields Figure 8-13. No-Hash Function Figure 8-14. 192-Bit Hash Function Figure 8-15. Hash Function Figure 8-16. Network Dispatcher Hash Function Figure 8-17. 48-Bit Hash Function Figure 8-18. 60-Bit Hash Function Figure 8-19. 8-bit Hash Function Figure 8-20. 12-bit Hash Function Figure 8-21. Hash Function Figure 9-1. Interface Block Diagram Figure 9-2. Boot Image External EEPROM Figure 9-3. Timing Figure 9-4. Interface Write Protocol Figure 9-5. Interface Read Protocol Figure 10-1. PowerPC Subsystem Block Diagram Figure 10-2. Polled Access Flow Diagram Figure 11-1. System Environments Figure 13-1. NP2G Memory Subsystems Figure 14-1. LVTTL Tolerant BP33 IP33 Receiver Input Current/Voltage Curve
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About This Book
This datasheet describes PowerNP NP2G explains basics building system using terms abbreviations list provided Section Glossary Terms Abbreviations page 529.
Should Read This Manual
This datasheet provides information network hardware engineers programmers using NP2G develop interconnect solutions Internet enterprise network providers. includes overview data flow through device descriptions each functional block. addition, provides electrical, physical, thermal, configuration information about device.
Related Publications
PowerPC 405GP Embedded Processor User's Manual Specification, version (http://www.pcisig.com)
Conventions Used This Manual
following conventions used this manual. notation following sections non-IBM, meaning that zero least significant most significant 4-byte word. Section Physical Description Section Physical Multiplexer Section Ingress Enqueuer Dequeuer Scheduler Section Ingress-to-Egress Wrap Section Egress Enqueuer Dequeuer Scheduler Section Embedded Processor Complex Section Serial Parallel Manager Interface
notation Section Tree Search Engine Section Embedded PowerPCSubsystem IBM-standard, meaning that least significant zero most significant 4-byte word. Nibble numbering same byte numbering. left-most nibble most significant starts zero. counters wrap back zero when they exceed their maximum values. Exceptions this rule noted counter definitions. Overbars (TxEnb, example) designate signals that asserted "low."
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PowerNP NP2G Network Processor
Numeric notation follows: Hexadecimal values preceded example: x`0B00'. Binary values text either spelled (zero one) appear quotation marks. example: `10101'. Binary values Default Description columns register sections often isolated from text this example: action read access Auto-reset interrupt request register upon read access Field length conventions follows: byte bits word bytes double word (DW) words bytes quadword (QW) words bytes
signal field definitions, when field designated "Reserved": must sent zero input into NP2G, either signal value reserved field control block used input picocode process. must checked modified output from NP2G, either signal value reserved field control block used input external code process. code point results unpredictable behavior.
About This Book
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PowerNP NP2G
Network Processor
General Information
Features
million packets second (Mpps) Layer Layer switching. dyadic protocol processor units (DPPUs) picocode processors DPPU shared coprocessors DPPU Four threads DPPU Zero context switching overhead between threads Embedded processor external 33/66 32-bit enhanced design flexibility. supports RISCWatch through JTAG interface Integrated Ethernet packet over SONET (POS) medium access controls (MACs) Gigabit Ethernet (plus gigabit uplink/control point attachment port) Fast Ethernet ports, accessed through Serial Media-Independent (SMII), Gigabit Media-Independent (GMII), Ten-Bit (TBI) interfaces, that support industry standard physical layer devices Ethernet statistics counters million software-defined, hardware-assisted counters, enabling support many standard Management Information Bases (MIBs) wire speed OC-3c, OC-12, OC-12c (plus OC-12 OC-12c uplink/control point attachment port) integrated interfaces that support industry standard framers Hardware VLAN support (detection, insertion deletion). PowerPC Advanced flow control mechanisms that tolerate high rates temporary oversubscription without collapse. Fast lookups powerful search engines based geometric hash functions that yield lower collision rates than conventional bitscrambling methods. Hardware support port mirroring. Mirrored traffic share bandwidth with user traffic separate data path, eliminating normal penalty port mirroring. Support jumbo frames. Maximum length determined value Ethernet Jumbo Frame Size register (see Section 13.26 page 489). value increased four octets VLAN tagged frames. Hardware-managed, software-configured bandwidth allocation control 2047 concurrent communication flows. Serial management interface support physical layer devices, board, functions SA-27E, 0.18 technology. Voltage ratings: supply voltage compatibility with drivers receivers 1.25 reference voltage SSTL drivers 1088-pin Bottom Surface Metallurgy Ceramic Column Grid Array (BSM-CCGA) package with Signal I/O. IEEE® 1149.1a JTAG compliant.
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Ordering Information
Part Number IBM32NP160EPXCAA133 IBM32NP160EPXCAB133 Description PowerNP NP2GA (R1.0) Network Processor PowerNP NP2GB (R2.0) Network Processor
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Overview
PowerNPNP2G Network Processor enables network hardware designers create fast, powerful, scalable systems. NP2G contains Embedded Processor Complex (EPC) which processors coprocessors work with hardware accelerators increase processing speed power. Additional features, such integrated search engines, variable packet length schedulers, support functions, support needs customers require high function, high capacity, media-rate switching. heart NP2G, evaluating, defining, processing data. maximizes speed processing power device provides with functionality above that independent switching device. Within EPC, dyadic protocol processor units (DPPUs) combine picocode processors, coprocessors, hardware accelerators support functions such high-speed pattern search, data manipulation, internal chip management, frame parsing, data prefetching. NP2G provides fast switching integrating switching engine, search engine, security functions device. supports Layer Ethernet frame switching, includes three priority levels port mirroring, high priority user frames, priority frames. supports Ethernet, packet over SONET (POS), Point-to-Point Protocol (PPP) protocols. Because device's ability enforce hundreds rules with complex range action specifications, NP2G-based systems uniquely suited server clusters. Systems developed with NP2G distributed software model. support this model, device hardware Code Development Suite include on-chip debugger facilities, picocode assembler, picocode system simulator, which decrease time market applications. order take advantage these features, designer must know device works fits into system. following sections discuss basic placement device within system, major functional blocks, movement data through chapters following this overview explore these issues detail.
NP2G-Based Systems
NP2G designed medium- low-end systems, "desktop routers," with uplink larger switch. high-end systems, PowerNP NP4GS3 Network Processor required. Systems developed with NP2G distributed software model, which relies control point execute software instructions. control point external microprocessor connected through Ethernet link interface. NP2G's embedded PowerPC processor also perform control point functions. this model, functions divided between control point network processor, illustrated Figure 1-1. control point supports Layer Layer routing protocols, Layer Layer network applications, maintenance, Management Information Base (MIB) collection (that control point functions SNMP agent), other systems management functions. Other functions, such forwarding, filtering, classification tables generated routing protocols, performed dyadic protocol processor units (DPPUs) each network processor system. Core Language Processors (CLPs) each DPPU execute EPC's core software instruction set, which includes conditional execution, conditional branching, signed unsigned operations, counts leading zeros, more.
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Figure 1-1. Function Placement NP2G-Based System
Control Store
Data Store PowerNP NP2G
Control Point Support (Spanning Tree.) Support (OSPF.) Network Applications Networking Management Agent (RMON.) Services
PowerNP NP2G Forwarding Filtering Learning Forwarding Filtering Flow Classification Priority Shaping Frame Repository Queueing Flow Control Frame Alteration Multicast Handling Network Management Counters
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Structure
PowerNP NP2G network processor seven major functional blocks, illustrated Figure page Embedded PowerPCSubsystem Ingress Enqueuer Dequeuer Scheduler (Ingress EDS) Egress Enqueuer Dequeuer Scheduler (Egress EDS) Ingress-to-Egress Wrap (IEW) Provides processing functions device. control point device; Control Store interface provides program space embedded PowerPC subsystem. Provides logic frames traveling from physical layer devices.
Provides logic frames traveling physical layer devices.
Transfers frames from ingress side NP2G egress side NP2G.
Ingress Physical Receives frames from physical layer devices. Multiplexer (Ingress PMM) Egress Physical Multiplexer (Egress PMM) Transmits frames physical layer devices.
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Figure 1-2. NP2G Major Functional Blocks
SDRAM SRAM
Ingress Enqueuer Dequeuer Scheduler
Ingress-to-Egress Wrap (IEW)
Egress Enqueuer Dequeuer Scheduler Interface
Internal SRAMs Embedded Power Embedded Processor Complex
Data Store
SDRAM Data Store Egress Multiplexed MACs
Ingress Multiplexed MACs
Physical Layer Devices
1.5.1 Structure contains dyadic protocol processor units (DPPUs). Each DPPU contains Core Language Processors (CLPs) that share coprocessors, coprocessor command bus, memory pool. DPPUs share threads, four which enhanced, three hardware accelerators. Together, DPPUs capable operating frames parallel. They share words internal picocode instruction store, providing 1596 million instructions second (MIPS) processing power. addition, contains Hardware Classifier parse frames fly, preparing them processing picocode.
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1.5.1.1 Coprocessors Each DPPU contains picocode processors, CLPs, that execute EPC's core instruction control thread swapping instruction fetching. CLPs share eight dedicated coprocessors that parallel with CLPs: Checksum Interface Calculates verifies frame header checksums. Controls thread access Control Access (CAB) through Arbiter; Control, Arbiter, Interface enable debug access NP2G data structures. coprocessor response (CRB) interface internal coprocessor that enables attachment external coprocessor with results returned internal register. Picocode determines processing status (busy/ busy) busy managed coprocessor. Updates counters picocode engines. Interfaces frame buffer memory (ingress egress directions), providing 320-byte working area. Provides access Ingress Egress Data Stores. Manages control blocks containing frame parameters; works with Completion Unit hardware accelerator enqueue frames target port output queues. Determines incoming data stream complies with configured profiles. Accelerates data movement between coprocessors within shared memory pool. Performs pattern analysis through tree searches (based algorithms provided picocode) read write accesses, protected memory range checking; accesses Control Store memory independently. Assists controlling access shared resources, such tables control structures, through semaphores; grants semaphores either dispatch order (ordered semaphores) request order (unordered semaphores).
Coprocessor Response
Counter Data Store
Enqueue
Policy String Copy Tree Search Engine
Semaphore Manager
1.5.1.2 Enhanced Threads Each threads, making four threads DPPU, total. Twenty threads General Data Handlers (GDHs), used forwarding frames, four threads enhanced: Guided Frame Handler (GFH) General Table Handler (GTH) Handles Guided Frames, in-band control mechanism between devices system, including control point. Builds table data Control Memory
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General PowerPC Handler Request (GPH-Req) General PowerPC Handler Response (GPH-Resp)
Processes frames bound embedded PowerPC.
Processes responses from embedded PowerPC.
1.5.1.3 Hardware Accelerators DPPUs share three hardware accelerators: Completion Unit Dispatch Unit Control Store Arbiter Assures frame order data exits threads. Fetches data parses work among DPPUs. Enables processors share access Control Store.
1.5.2 NP2G Memory Storage NP2G provided both internal external memories (see Figure page 32). Control Store contains tables, counters, other data needed picocode. Data Stores contain frame data forwarded used picocode (via Data Store coprocessor) create guided traffic. NP2G following stores: common instruction memory that holds instruction words normal processing control functions internal SRAM input frame buffering internal SRAM Control Store High capacity external SDRAM egress frame buffering large forwarding tables; amount memory vary depending configuration. External SRAM fast table access interface interface (for Scheduler)
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Data Flow
Figure 1-3. Data Flow Overview
Ingress-to-Egress Wrap (IEW)
Ingress
Embedded Processor Complex
Egress
Ingress Egress
Physical Layer Devices
1.6.1 Basic Data Flow many data flow routes possibilities exist fully document this overview. However, data generally moves through NP2G following manner (see Figure 1-3): Ingress receives frame from physical layer device forwards Ingress EDS. Ingress identifies frame enqueues EPC. processes frame data (see Section 1.6.2). discard frame modify frame data directly then return updated data Ingress EDS's Data Store. frame enqueued Ingress EDS, Ingress Scheduler selects frame transmission moves data IEW. transfers frames from ingress egress EDS. Egress reassembles frame enqueues once fully reassembled. processes (see Section 1.6.2). discard frame modify using frame alteration hardware assists. extensive modification required, append rewrite frame Data Store.
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frame enqueued Egress EDS, Egress Scheduler, enabled, selects frame transmission moves data Egress PMM. Scheduler enabled, forward frame target port queue, wrap port, GPH. Egress sends frame physical layer device. 1.6.2 Data Flow Figure 1-4. Basic Data Flow
Egress
Ingress Queue Interface
Completion Unit
Egress Queue Interface
Control Store Arbiter
Ingress
Available DPPU
Egress
Enqueue Coprocessor
Data Store Coprocessor
Tree Search Engine Ingress Data Store Instruction Memory Egress Data Store (External) Hardware Classifier
Dispatch Unit
functional center device, plays pivotal role data flow. This section presents basic overview data flow EPC.
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Ingress Side Ingress enqueues data frame EPC. Dispatch Unit fetches portion frame sends next available thread. Simultaneously, Hardware Classifier (HC) determines starting Common Instruction Address (CIA), parses different frame formats (for example: bridged, IPX), forwards results thread. picocode examines information from examine data further; assembles search keys launches Tree Search Engine (TSE). performs table searches, using search algorithms based format downloaded tables. Control Store Arbiter allocates Control Store memory bandwidth among protocol processors. Frame data moves into Data Store coprocessor's memory buffer. Forwarding frame alteration information identified results search. Ingress insert overlay VLAN tags frame (hardware-assisted frame alteration) picocode allocate remove buffers allow alteration frame (flexible frame alteration). Enqueue coprocessor builds necessary information enqueue frame provides Completion Unit (CU), which guarantees frame order data moves from threads DPPU Ingress queues. frame enqueued Ingress EDS. Ingress forwards frame Ingress Scheduler. Scheduler selects frame transmission IEW. Note: entire frame sent once. Scheduler sends cell time. With help Ingress EDS, segments frames into 64-byte cells inserts Cell Header Frame Header bytes that they stored reassembled egress side. Thus, necessary smaller ingress data store store frames while waiting their ends arrive. Egress Side Egress enqueues data frame EPC. Dispatch Unit fetches portion frame sends next available thread. Simultaneously, determines starting CIA, parses different frame formats (for example: bridged, IPX), forwards results thread. picocode examines information from examine data further; assembles search keys launches TSE. performs table searches, using search algorithms based format downloaded tables. Control Store Arbiter allocates Control Store memory bandwidth among protocol processors. Frame information, including alteration instructions, moves into queues Egress EDS; flexible frame alteration used, Data Store coprocessor moves additional frame data Data Store. Forwarding frame alteration information identified results search. NP2G provides frame alteration techniques: hardware-assisted frame alteration flexible frame alteration:
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hardware-assisted frame alteration, commands passed Egress hardware during enqueueing. These commands can, example, update field header, generate frame CRC, overlay existing Layer wrapper with one. flexible frame alteration, picocode allocates additional buffers Data Store coprocessor places data into these buffers. additional buffers allow prepending data received frame bypassing part received data when transmitting. This useful frame fragmentation when when header header must prepended received data order form frame fragment correct size. Enqueue coprocessor builds necessary information enqueue frame Egress provides which guarantees frame order data moves from threads DPPU Egress queues. frame enqueued Egress EDS. frame enqueued Egress EDS, which forwards Egress Scheduler enabled). Scheduler selects frame transmission target port queue. Scheduler enabled, will forward frame directly target queue. Egress selects frames transmission from target port queue moves their data Egress PMM.
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Physical Description
Figure 2-1. Device Interfaces
Data Stores SRAM Control Store SDRAM Control Store D0/2/3 Interface SDRAM Control Store Interface SDRAM Control Store Interface Clk, TEST, RESET, etc. Note: Memory Array consists following SDRAMs: DRAMs devices each DRAMs device each DRAM devices
GMll SMll GMll SMll GMll
SDRAM
PowerNP NP2G
SDRAM
Interface
EEPROM Interface
EEPROM
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Information
This section describes many interfaces associated pins NP2G Network Processor. summary device's interfaces many pins each contains, Table 2-1. information signal locations, Table 2-38: Complete Signal Listing Signal Name page Table 2-39: Complete Signal Listing Grid Position page following table groups interfaces pins function, briefly describes them, points location specific information chapter. Table 2-1. Signal Functions (Page
Type Flow Control Interface with SRAM Interface SRAM lookups Function Resources Table 2-3: Flow Control Pins page Table 2-4: SRAM Interface Pins page Table 2-5: SRAM Interface Pins page Figure 2-2: SRAM Timing Diagram page
Memory
Table 2-10: Interface Pins page Table 2-11: Memory Pins page Interface with SDRAM used implement Figure 2-3: Control Timing Diagram page memories Figure 2-4: Read Timing Diagram page Figure 2-5: Write Output Timing Diagram page Interface with DRAM used implement memories Table 2-12: D4_0 D4_1 Interface Pins page Figure 2-3: Control Timing Diagram page Figure 2-4: Read Timing Diagram page Figure 2-5: Write Output Timing Diagram page Table 2-13: D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins page Figure 2-3: Control Timing Diagram page Figure 2-4: Read Timing Diagram page Figure 2-5: Write Output Timing Diagram page Table 2-14: Interface Pins page Figure 2-3: Control Timing Diagram page Figure 2-4: Read Timing Diagram page Figure 2-5: Write Output Timing Diagram page Table 2-15: Interface Pins page Table 2-16: Interface Multiplexing page Figure 2-6: NP2G Clock Connections page Table 2-18: Parallel Data 8B/10B Position Mapping (TBI Interface) page Table 2-19: Interface Pins: Mode page Figure 2-8: Timing Diagram page Table 2-21: Interface Pins: GMII Mode page Figure 2-9: GMII Timing Diagram page Table 2-23: Interface Pins: SMII Mode page Figure 2-10: SMII Timing Diagram page Figure 2-7: NP2G Clock Connections (POS Overview) page Table 2-25: Signals page Figure 2-11: Transmit Timing Diagram page Figure 2-12: Receive Timing Diagram page
D4_0 D4_1 Memory
D6_5, D6_4, Interface with SDRAM D6_3, D6_2, used implement PowerPC D6_1, D6_0 Store Memory Interface with DRAM used implement memories
Memory
Interface with physical layer devices through following buses:
Interface GMII SMII
Physical Description
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Table 2-1. Signal Functions (Page
Type Interface Management Miscellaneous Function Interface Resources Table 2-27: Pins page Figure 2-13: Timing Diagram page
Table 2-29: Management Pins page Translated into various "host" buses external FPGA (SPM) Figure 2-14: Timing Diagram page Various interfaces Table 2-31: Miscellaneous Pins page Table 2-32: Signals Requiring Pull-Up Pull-Down page
2.1.1 Ingress-to-Egress Wrap (IEW) Pins Table 2-2. Ingress-to-Egress Wrap (IEW) Pins
Signal (Clock Domain) Master_Grant_A(1:0) Master_Grant_B(1:0) (IEW Description These signals used receive status information from egress side. Both bits should connected Send_Grant_A both bits should connected Send_Grant_B pin. Send Grants indicate whether able receive cells from ingress side. Unable Able NP2G changes state these signals corresponding Master_Grant inputs. Type Input V-tolerant LVTTL
Send_Grant_A Send_Grant_B (IEW
Output V-tolerant LVTTL
2.1.2 Flow Control Interface Pins Table 2-3. Flow Control Pins
Signal I_FreeQ_Th Ingress Free Queue Threshold Threshold exceeded Threshold exceeded Remote Egress Status synchronization (sync) driven network processor indicate start time division multiplex cycle passing egress status information ingress side. Remote Egress Status data driven network processor indicate congestion status ingress side during designated time slot. exceeded Network processor's exponentially weighted moving average (EWMA) egress offered rate exceeds configured threshold. Description Type Output V-tolerant LVTTL Input/Output V-tolerant LVTTL Input/Output V-tolerant LVTTL
RES_Sync
RES_Data
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Physical Description
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PowerNP NP2G Network Processor
2.1.3 Interface Pins These pins interface with SRAM lookups described Table Table 2-5. Table 2-4. SRAM Interface Pins
Signal LU_Clk Description Look-Up clock. period (133 MHz). Type Output CMOS Output CMOS Input/Output CMOS Output CMOS Input/Output CMOS
LU_Addr(19:0)
Look-Up Address signals sampled rising edge LU_Clk.
LU_Data(35:0)
Look-Up Data. When used SRAM inputs, rising edge LU_Clk samples these signals. Look-Up Read/Write control signal sampled rising edge LU_Clk. Write Read Coprocessor Response (CRB). Results from external coprocessor sent specified thread's Coprocessor stored into Results register.
LU_R_Wrt
cam_cp_response(13:0)
Table 2-5. SRAM Interface Pins
Signal SCH_Clk Description SRAM Clock input. period (133 MHz). Type Output CMOS Output CMOS Input/Output CMOS Output CMOS
SCH_Addr(18:0)
SRAM Address signals sampled rising edge LU_Clk.
SCH_Data(17:0)
Data bus. When used SRAM input, rising edge SCH_Clk samples these signals. Read/Write control signal sampled rising edge SCH_Clk. Write Read
SCH_R_Wrt
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
Figure 2-2. SRAM Timing Diagram
Outputs
XX_Clk (MAX) XX_Addr (MIN)
tDWE (MAX)
tDWE (MIN)
XX_R_Wrt
tDCKON
tDCKOFF
XX_Data
(MAX)
(MIN)
Inputs
+VDD/2 Notes: Data Invalid
Output Load ohms
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Physical Description
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PowerNP NP2G Network Processor
Table 2-6. SRAM Timing Diagram Legend (for Figure 2-2)
Symbol tDWE tDCKON tDCKOFF Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Read/Write Output Delay Data Output Delay Data Output Turn Data Output Turn Input Data Setup Time Input Data Hold Time Symbol Description Minimum (ns) Maximum (ns)
Note: delays measured with slew time measured from input voltage.
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
2.1.4 DRAM Interface Pins pins described here interface with DRAM implement data store, control store, PowerPC store. control, read, write timing diagrams (Figure 2-3, Figure 2-4, Figure 2-5) apply tables this section. Figure 2-3. Control Timing Diagram
dy_nclk dy_clk (MAX) dx_Addr (MIN)
(MAX) dx_WE
(MIN)
tDCS (MAX) dx_CS
tDCS (MIN)
tDBA (MAX) dy_BA
tDBA (MIN)
tDRAS (MAX) dy_RAS
tDRAS (MIN)
tDCAS (MAX) dy_CAS
tDCAS (MIN)
+VDD/2 Notes: DS0, Data Invalid
Output Load ohms
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Physical Description
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PowerNP NP2G Network Processor
Figure 2-4. Read Timing Diagram
dy_nclk dy_clk
tCSS
dx_dqs
tDQSQ (MIN) tDQSQ (MAX) dx_dq
tDQSQ (MIN) tDQSQ (MAX)
+VDD/2 Notes: DS0, Data Invalid
Ouput Load ohms
Physical Description
Page
np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Figure 2-5. Write Output Timing Diagram
dy_nclk dy_clk
tCSD
dx_dqs
dx_dq
d6_ByteEn
+VDD/2 Notes: DS0, Data Invalid
Ouput Load ohms Byte enablement only.
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Physical Description
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PowerNP NP2G Network Processor
Table 2-7. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Values
DS0,
Symbol tDCS tDRAS tDCAS tCSD tCSS tDQSQ Clock Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Write Enable Output Delay Chip Select Output Delay Bank Address Output Delay Output Delay Output Delay dy_clk dx_dqs Strobe Output Delay Data Strobe Output Setup Time Data Strobe Output Hold Time Clock Strobe Input Skew Data Input Skew Symbol Description Minimum (ns) 0.45 0.45 -2.0 0.55 0.55 Maximum (ns)
Note: delays measured with skew time measured from 10-90% input voltage. measurements made with Test Load ohms dx_dqs descriptions DS0, DS1, interfaces (Section 2.1.4.2 page Section 2.1.4.4 page describe association data strobe data. This association dependent setting Strobe_cntl DRAM configuration register described Section 13.1.2 page 434.
Physical Description
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PowerNP NP2G Preliminary Network Processor
Table 2-8. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Values 4-bit
Interface Mode.
Symbol tDCS tDRAS tDCAS tCSD tCSS Symbol Description Clock Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Write Enable Output Delay Chip Select Output Delay Bank Address Output Delay Output Delay Output Delay dy_clk dx_dqs Strobe Output Delay Data Strobe Output Setup Time Data Strobe Output Hold Time Byte Enable Strobe Setup Time Byte Enable Strobe Hold Time Clock Strobe Input Skew Data Input Skew d6_data_00-03 Data Input Skew d6_data_04-07 Data Input Skew d6_data_08-11 tDQSQ Data Input Skew d6_data_12-15 Data Input Skew d6_parity_00 Data Input Skew d6_parity_01 Note: delays measured with slew time measured from 10-90% input voltage. measurements made with Test Load ohms Minimum (ns) 0.45 0.45 -2.0 0.55 0.55 Maximum (ns)
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Physical Description
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PowerNP NP2G Network Processor
Table 2-9. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Values 16-bit
Interface Mode.
Symbol tDCS tDRAS tDCAS tCSD tCSS Clock Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Write Enable Output Delay Chip Select Output Delay Bank Address Output Delay Output Delay Output Delay dy_clk dx_dqs Strobe Output Delay Data Strobe Output Setup Time Data Strobe Output Hold Time Byte Enable Strobe Setup Time Byte Enable Strobe Hold Time Clock Strobe Input Skew Data Input Skew d6_data_00-07 Data Input Skew d6_data_08-15 tDQSQ Data Input Skew d6_parity_00 Data Input Skew d6_parity_01 Note: delays measured with slew time measured from 10-90% input voltage. measurements made with Test Load ohms Symbol Description Minimum (ns) 0.45 0.45 -2.1 0.55 0.55 Maximum (ns)
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
2.1.4.1 Interface Pins These pins interface with SDRAM used implement control stores. Table 2-10. Interface Pins
Signal Shared Signals DB_Clk positive output differential pair. MHz. Common memory devices. negative output differential pair. MHz. Common memory devices. Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Description Type
DB_Clk
DB_RAS
Common address strobe (common D2).
DB_CAS
Common column address strobe (common D2).
DB_BA(1:0) Signals D3_Addr(12:0)
Common bank address (common D2).
address
Output CMOS Input/Output SSTL2 Input/Output SSTL2 Output CMOS Output CMOS
D3_DQS(1:0)
data strobes
D3_Data(15:0)
data
D3_WE
write enable
D3_CS Signals D2_Addr(12:0)
chip select
address
Output CMOS Input/Output SSTL2 Input/Output SSTL2 Output CMOS Output CMOS
D2_DQS(1:0)
data strobes
D2_Data(15:0)
data
D2_WE
write enable
D2_CS
chip select
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Physical Description
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PowerNP NP2G Network Processor
Table 2-11. Memory Pins
Signal D0_0 D0_1 Shared Signals DE_Clk positive output differential pair. MHz. Common D0_0/1 memory devices. Output SSTL2 Output SSTL2 Output CMOS Output CMOS Output CMOS Output CMOS Input/Output SSTL2 Input/Output SSTL2 Output CMOS Output CMOS Description Type
DE_Clk
negative output differential pair. MHz. Common D0_0/1 devices.
DE_RAS
Common address strobe
DE_CAS
Common column address strobe
DE_BA(1:0)
Common bank address
D0_Addr(12:0)
address
D0_DQS(3:0)
data strobes
D0_Data(31:0)
data
D0_WE
write enable
D0_CS
chip select
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
2.1.4.2 D4_0 D4_1 Interface Pins These pins interface with DRAM used implement control store. Table 2-12. D4_0 D4_1 Interface Pins
Signal DD_Clk Description positive output differential pair. MHz. Common D4_0/1 memory devices. Type Output SSTL2 Output SSTL2 Output CMOS Output CMOS Output CMOS Output CMOS
DD_Clk
negative output differential pair. MHz. Common D4_0/1 memory devices.
DD_RAS
Common address strobe
DD_CAS
Common column address strobe
DD_BA(1:0)
Common bank address
D4_Addr(12:0)
address data strobes. Data bits associated with strobe bits follows: Strobe_cntl `01' Strobe_cntl `00' 31:24 23:16 15:8 31:0 data
D4_DQS(3:0)
Input/Output SSTL2
D4_Data(31:0)
Input/Output SSTL2 Output CMOS Output CMOS
D4_WE
write enable
D4_CS
chip select
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Physical Description
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PowerNP NP2G Network Processor
2.1.4.3 D6_x Interface Pins These pins interface with SDRAM used implement PowerPC store. Table 2-13. D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins
Signal DA_Clk Description positive output differential pair. MHz. Common memory devices. Type Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2
DA_Clk
negative output differential pair. MHz. Common memory devices.
DA_RAS
Common address strobe (common D6).
DA_CAS
Common column address strobe (common D6).
DA_BA(1:0)
Common bank address (common D6).
D6_WE
Common write enable (common D6).
D6_Addr(12:0)
address
D6_CS
chip select data strobes. Data bits associated with strobe bits follows: D6_DRAM_Size `0xx' D6_DRAM_Size `1xx' 15:12 15:8 11:8 data byte enables byte masking write Data masked when D6_ByteEn high. Data bits associated with byte enable follows: 15:8 parity signals, byte. Must separate chips allow byte write capability. Data bits associated with parity bits follows: 15:8 data strobe parity signals
D6_DQS(3:0)
Input/Output SSTL2
D6_Data(15:0)
Input/Output SSTL2 Input/Output SSTL2
D6_ByteEn(1:0)
D6_Parity(1:0)
Input/Output SSTL2 Input/Output SSTL2
D6_DQS_Par(1:0)
Physical Description
Page
np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
2.1.4.4 Interface Pins These pins interface with DRAM used implement data stores. Table 2-14. Interface Pins (Page
Signal Shared Signals DC_Clk positive output differential pair. MHz. Common memory devices. negative output differential pair. MHz. Common memory devices. Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Description Type
DC_Clk
DC_RAS
Common address strobe (common DS0).
DC_CAS
Common Column address strobe (common DS0).
DC_BA(1:0) Signals DS1_Addr(12:0)
Common bank address (common DS0).
address data strobes. Data bits associated with strobe bits follows: Strobe_cntl `01' Strobe_cntl `00' 31:24 23:16 15:8 31:0 data
Output CMOS
DS1_DQS(3:0)
Input/Output SSTL2
DS1_Data(31:0)
Input/Output SSTL2 Output CMOS Output CMOS
DS1_WE
write enable
DS1_CS Signals DS0_Addr(12:0)
chip select
address data strobes. Data bits associated with strobe bits follows: Strobe_cntl `01' Strobe_cntl `00' 31:24 23:16 15:8 31:0
Output CMOS
DS0_DQS(3:0)
Input/Output SSTL2
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-14. Interface Pins (Page
Signal DS0_Data(31:0) data Description Type Input/Output SSTL2 Output CMOS Output CMOS
DS0_WE
write enable
DS0_CS
chip select
2.1.5 Interface Pins These pins allow Physical Multiplexer (PMM) interface with physical layer devices. NP2G different sets pins Ten-Bit (TBI), Gigabit Media-Independent (GMII), Serial Media-Independent (SMII), Packet over SONET (POS) interfaces. Table 2-15. Interface Pins
Signal DMU_A(30:0) DMU_C(30:0) DMU_D(30:0) Description Define first four interfaces configured TBI, SMII, GMII, POS. Table 2-16: Interface Multiplexing page directions definitions. Define third four interfaces configured TBI, SMII, GMII, POS. Table 2-16: Interface Multiplexing page directions definitions. Define fourth four interfaces configured TBI, SMII, GMII, Debug, POS. Table 2-16: Interface Multiplexing page directions definitions. Type V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL
Physical Description
Page
np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Table 2-16. Interface Multiplexing
Mode Pin(s) DMU_A, DMU_C DMU_D Tx_Valid_Byte Tx_Data(7:0) Rx_Data(7:0) Tx_Clk Tx_En Tx_Er Rx_Valid_Byte Tx_Byte_Credit Rx_Clk Rx_DV Rx_Er CPDetect CPF) Input Tx_Data(0:7) Rx_Data(0:7) Tx_Clk Tx_Data(8) Tx_Data(9) Rx_Data(8) Rx_Data(9) Rx_Clk1 Rx_Clk0 Sig_Det CPDetect CPF) Input Activity Output Tx_Data(9:2) Rx_Data(9:2) Tx_Data(1) Tx_Data(0) Rx_Data(1) Rx_Data(0) Sync Sync2 CPDetect CPF) Input Debug(23:16) Debug(15:8) Debug(7) Debug(6) Debug(5) Debug(4) Debug(3) Debug(2) Debug(1) Debug(0) GMII Interface Type SMII Debug (DMU_D only) 8-Bit RxAddr(1) RxAddr(0) TxAddr(1) TxAddr(0) TxSOF TxEOF TxData(7:0) RxData(7:0) TxEn TxPFA RxPFA RxVal RxEOF RxErr RxEnb
(24:17) (16:9)
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Figure 2-6. NP2G Clock Connections
GMII Interface
oscillator
PowerNP NP2G clock125 DMU_*(8) DMU_*(3) Tx_Clk Rx_Clk
GMII port)
SMII Interface
PowerNP NP2G
oscillator
DMU_*(8) DMU_*(3)
Note: trace lengths inputs will matched card.
SMII ports)
SMII ports)
Interface
PowerNP NP2G Clock_Core 53.3 oscillator
oscillator
clock125
asynchronous interface DMU_*(8) Tx_Clk DMU_*(3) Rx_Clk1 62.5 DMU_*(2) Rx_Clk0 62.5
ports)
Notes: Each figure above illustrates single applies three busses. "DMU_*" labels represent three busses (DMU_A, DMU_C, DMU_D).
Physical Description
Page
np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Figure 2-7. NP2G Clock Connections (POS Overview)
Single (applies A-D)
PowerNP NP2G
DMU_*(8)
DMU_*(3) oscillator
TxClk
RxClk
Note: Trace lengths inputs will matched card.
AFramer
2.1.5.1 Pins Table 2-17. Interface Pins: Debug (DMU_D Only)
Signal Description When DMU_D configured debug bus, signals internal NP2G available observed externally. This mode supported only when directed Network Processor Application Engineer. recommended that board designs provide attachment scope probes observe this interface which runs MHz. Type Output V-tolerant LVTTL
Debug (23:0)
Table 2-18. Parallel Data 8B/10B Position Mapping (TBI Interface)
Parallel Data 8B/10B Position
Table 2-19. Interface Pins: Mode (Page
Signal Tx_Data(9:0) Description Transmit data. Data PHY, synchronous Tx_Clk. Type Output V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL
Rx_Data(9:0)
Receive data. Data from PHY, synchronous Rx_Clk1 Rx_Clk0. (Data switches double frequency Rx_Clk1 Rx_Clk0.)
Rx_Clk1
Receive Clock, 62.5 MHz. Rx_Data valid rising edge this clock.
Rx_Clk0
Receive Clock, 62.5 MHz. This signal degrees phase with Rx_Clk1. Rx_Data valid rising edge this clock.
Note: Table 2-16: Interface Multiplexing page directions (I/O) definitions.
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-19. Interface Pins: Mode (Page
Signal Sig_Det Description Signal Detect. Signal asserted indicate that physical media valid. This must pulled indicate when Control Point active this interface. Otherwise, this signal should pulled high (inactive). state signal captured Data Mover Unit (DMU) Configuration (page 485) when Reset signal deasserted. After configuration, this signal driven network processor indicate status interface. interface data pass state (link down) interface data pass state (occurs when auto-negotiation complete, when idles detected disabled)) pulse interface data pass state either receiving transmitting. line pulses once frame transmitted received maximum rate 8Hz. clock Transmit clock PHY. During operation, network processor drives this signal indicate that transmit receive progress this interface. Type Input V-tolerant LVTTL
CPDetect
Input/Output V-tolerant LVTTL
Tx_Clk
Output V-tolerant LVTTL
Note: Table 2-16: Interface Multiplexing page directions (I/O) definitions.
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
Figure 2-8. Timing Diagram
Transmit Timings tXCK tXCH Tx_Clk (MAX) (MIN) Tx_Data tXCL
Receive Timings
tRCK tRCH tRCL
Rx_Clk0 tRDH Rx_Data tRDS tRCK tRCL Rx_Clk1 tRDH Rx_Data tRDS tRCH tRSH
+VDD/2 Notes: tRSS Data Invalid
Output Load ohms
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-20. Timing Diagram Legend (for Figure 2-8)
Symbol tXCK tXCH tXCL tRCK tRCH tRCL tRDS tRDH tRDS tRDH Tx_Clk Transmit Cycle Time Tx_Clk Pulse Width High Tx_Clk Pulse Width Tx_Data_(7:0) Output Delay Rx_Clk0/Rx_Clk1 Receive Cycle Time Rx_Clk0/Rx_Clk1 Pulse Width High Rx_Clk0/Rx_Clk1 Pulse Width Rx_Data_(9:0) Setup Time Clk0 Rx_Data_(9:0) Hold Time Clk0 Rx_Data_(9:0) Setup Time Clk1 Rx_Data_(9:0) Hold Time Clk1 Symbol Description Minimum (ns) Maximum (ns)
Note: delays measured with slew time measured from 10-90% input voltage.
Physical Description
Page
np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
2.1.5.2 GMII Pins Table 2-21. Interface Pins: GMII Mode
Signal Tx_Data(7:0) Description Transmit Data. Data PHY, synchronous Tx_Clk. Type Output V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
Rx_Data(7:0)
Received Data. Data from PHY, synchronous Rx_Clk. Transmit data Enabled PHY, synchronous Tx_Clk. frame transmission Active frame transmission Transmit Error, synchronous Tx_Clk. error detected Informs that detected error Receive valid data, synchronous Rx_Clk. Data invalid Byte data (from PHY) Rx_Data valid. standard GMII connection, this signal tied card. Transmit next data value, asynchronous. send next data byte Asserted. indicates that next Tx_Data value sent. standard GMII connection, this signal tied card. Transmit valid data, synchronous Tx_Clock Data invalid Byte data (from Network Processor) Tx_Data valid. Receive Medium clock generated PHY. Receive Data Valid (from PHY), synchronous Rx_Clk. frame transmission. Active frame transmission. Receive Error, synchronous Rx_Clk. error detected Informs that detected error transmit clock PHY. During operation, network processor drives this signal indicate that transmit progress this interface. This must pulled indicate when Control Point active this interface. Otherwise, this signal should pulled high (inactive). state signal captured Data Mover Unit (DMU) Configuration (page 485) when Reset signal deasserted.
Tx_En
Tx_Er
Rx_Valid_Byte
Tx_Byte_Credit
Input V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
Tx_Valid_Byte
Rx_Clk
Rx_DV
Rx_Er
Tx_Clk
CPDetect
Note: NP2G supports GMII Full-Duplex Mode only. Table 2-16: Interface Multiplexing page directions (I/O) definitions.
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Figure 2-9. GMII Timing Diagram
Transmit Timings tXCH Tx_Clk (MAX) Tx_Data tDEN (MAX) Tx_En tDER (MAX) Tx_Er tDVB (MAX) Tx_Valid_Byte tDBV (MIN) tDER (MIN) tDEN (MIN) (MIN) tXCL
Receive Timings tRCH Rx_Clk tRDH Rx_Data tRDS tRVH Rx_Valid_Byte tRVS tREH Rx_Er tRES tRDVH Rx_DV tRDVS tRCL
Notes: Data Invalid
Output Load ohms
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
Table 2-22. GMII Timing Diagram Legend (for Figure 2-9)
Symbol tXCH tXCL tRCH tRCL tDER tDVB tDEN tRDS tRDH tRVS tRVH tRES tREH tRDVS tRDVH Tx_Clk Cycle Time Transmit Clock Pulse Width High Transmit Clock Pulse Width Receive Clock Pulse Width High Receive Clock Pulse Width Tx_data Output Delay Tx_Er Output Delay Tx_Valid_Byte Output Delay Tx_En Output Delay Rx_data Setup Time Rx_data Hold Time Rx_Valid_Byte Setup Time Rx_Valid_Byte Hold Time Rx_Er Setup Time Rx_Er Hold Time Rx_DV Setup Time Rx_DV Hold Time Symbol Description Minimum (ns) Maximum (ns)
delays measured with slew time measured from 10-90% input voltage.
2.1.5.3 SMII Pins Table 2-23. Interface Pins: SMII Mode
Signal Tx_Data(9:0) Description Transmit Data. Data contains streams serial transmit data. Each serial stream connected unique port. Synchronous common clock (Clk). Received Data. Data from contains streams serial receive data. Each serial stream connected unique port. Synchronous common clock (Clk). Asserted Tx_Clk cycle once every Tx_Clk cycles. Assertion indicates beginning 10-bit segment both Tx_Data Rx_Data. Type Output V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
Rx_Data(9:0)
Sync
Sync2
Logically identical Sync provided fanout purposes. This must pulled indicate when Control Point active this interface. Otherwise, this signal should pulled high (inactive). state signal captured Data Mover Unit (DMU) Configuration (see 13.24 Data Mover Unit (DMU) Configuration Registers page 485) when Reset signal deasserted.
CPDetect
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Figure 2-10. SMII Timing Diagram
Transmit Timings (MAX) Tx_Data (MAX) Sync tDS2 (MAX) Sync2 tDS2 (MIN) (MIN) (MIN)
Receive Timings Rx_Data +VDD/2
Notes: Data Invalid
Output Load ohms
Table 2-24. SMII Timing Diagram Legend (for Figure 2-10)
Symbol tDS2 Cycle Time Pulse Width High Pulse Width Tx_data_(9:0) Output Delay Sync Output Delay Sync2 Output Delay Rx_data_(9:0) Setup Time Rx_data_(9:0) Hold Time Symbol Description Minimum (ns) Maximum (ns)
delays measured with slew time measured from 10-90% input voltage.
Physical Description
Page
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PowerNP NP2G Preliminary Network Processor
Table 2-25. Signals
Signal RxAddr(1:0) RxData(7:0) 8-bit mode Description Receive address selects particular port framer data transfer. Valid rising edge Clk. Receive data carries frame word that read from Framer's FIFO. RxData transports frame data 8-bit format. RxData[7:0] updated rising edge Clk. clock provides timing Framer interface. must cycle lower instantaneous rate. Receive read enable controls read access from Framer's receive interface. framer's addressed FIFO selected falling edge RxEnb. Generated rising edge Clk. Receive end-of-frame marks last word frame RxData. Updated rising edge Clk. Receive packet error indicates that received packet contains error must discarded. Only asserted last word packet (when RxEOF also asserted). Updated rising edge Clk. Receive valid data output indicates receive signals RxData, RxEOF, RxErr valid from framer. Updated rising edge Clk. Receive polled frame-available input indicates that framers polled receive FIFO contains data. Updated rising edge Clk. Transmit UTOPIA data carries frame word that written framer's transmit FIFO. Considered valid written framer's transmit FIFO only when transmit interface selected using TxEnb. Sampled rising edge Clk. Transmit write enable controls write access transmit interface. framer port selected falling edge TxEnb. Sampled rising edge Clk. Transmit address uses TxEnb select particular FIFO within framer data transfer. Sampled rising edge Clk. Transmit start-of-frame marks first word frame TxData. Sampled rising edge Clk. Transmit end-of-frame marks last word frame TxData. Sampled rising edge Clk. Transmit padding length indicates number padding bytes included last word packet transferred TxData. Sampled rising edge Clk. When configured 32-bit mode last word contain zero, one, three padding bytes only TxPADL[1:0] used. TxPADL[1:0] (32-bit mode) packet ends TxData[7:0] (TxData DDDD) packet ends TxData[15:8] (TxData DDDP) packet ends TxData[23:16] (TxData DDPP) packet ends TxData[31:24] (TxData DPPP) Transmit polled frame-available output indicates that polled framer's transmit FIFO free available space NP2G write data into framer's FIFO. Updated rising edge Clk. Type V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL
RxEnb
RxEOF
RxErr
RxVal RxPFA TxData (7:0) 8-bit mode (31:0) 32-bit mode TxEn TxAddr(1:0) TxSOF TxEOF
TxPADL (1:0)
V-tolerant LVTTL
TxPFA
V-tolerant LVTTL
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Figure 2-11. Transmit Timing Diagram
(MAX) TxData tDXA (MAX) TxAddr tDRA (MAX) RxAddr tDSOF (MAX) TxSOF tDEOF (MAX) TxEOF tDEN (MAX) TxEN tDPADL (MAX) TxPADL tDREN (MAX) RxEnb +VDD/2 Notes: Output Load ohms Data Invalid tDREN (MIN) tDPADL (MIN) tDEN (MIN) tDEOF (MIN) tDSOF (MIN) tDRA (MIN) tDXA (MIN) (MIN)
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Figure 2-12. Receive Timing Diagram
tRXH RxData tRXS tRPFH RxPFA tRPFS tTPFH RxErr tTPFS tRVH RxVal tRVS
tREOFH RxEOF tREOFS tTPFH TxPFA tTPFS tRPADH RxPADL tRPADS +VDD/2
Notes:
Data Invalid
Output Load ohms
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-26. Timing Diagram Legend (for Figure 2-11 Figure 2-12)
Symbol tDXA tDRA tDSOF tDEOF tDEN tDPADL tDREN tRXS tRXH tRVS tRVH tRERS tRERH tREOFS tREOFH tRPFS tRPFH tTPFS tTPFH tRPADS tRPADH Cycle Time Clock Width High Clock Width Tx_data_(31:0) Output Delay Tx_ADDR_(1:0) Output Delay Rx_ADDR_(1:0) Output Delay TxSOF Output Delay TxEOF Output Delay TxEn Output Delay TxPADL_(1:0) Output Delay RxEnb Output Delay Rx_data_(31:0) Setup Time Rx_data_(31:0) Hold Time RxVal Setup Time RxVal Hold Time RxErr Setup Time RxErr Hold Time RxEOF Setup Time RxEOF Hold Time RxPFA Setup Time RxPFA Hold Time TxPFA Setup Time TxPFA Hold Time RxPADL Setup Time RxPADL Hold Time Symbol Description Minimum (ns) Maximum (ns)
delays measured with slew time measured from 10-90% input voltage.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
2.1.6 Pins These pins interface with bus. Table 2-27. Pins (Page
Signal PCI_Clk Description Clock Signal (See PCI_Speed field below) Type Input (in)/ Input/Output (t/s) Input/Output (t/s) Input/Output (s/t/s) Input/Output (s/t/s) Input/Output (s/t/s) Input/Output (s/t/s) Input/Output (s/t/s) Output (t/s) Input (t/s) Input (in) Input/Output (s/t/s) Input/Output (o/d) Output (o/d) Input/Output (t/s)
PCI_AD(31:0)
Multiplexed Address Data Signals
PCI_CBE(3:0)
Command/Byte Enable Signals
PCI_Frame
Frame Signal
PCI_IRdy
Initiator (Master) Ready Signal
PCI_TRdy
Target (Slave) Ready Signal
PCI_DevSel
Device Select Signal
PCI_Stop
Stop Signal
PCI_Request
Request Signal
PCI_Grant
Grant Signal
PCI_IDSel
Initialization Device Select Signal
PCI_PErr
Parity Error Signal
PCI_SErr
System Error Signal
PCI_IntA
Level Sensitive Interrupt
PCI_Par
Parity Signal. Covers data/address four command/BE signals.
Note: I/Os configured multi-point operation.
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-27. Pins (Page
Signal Description Speed. Controls Acceptable Frequency Asynchronous Range setting PLB/PCI clock ratio. PLB:PCI Mode 2:1. Acceptable Frequency Asynchronous Range 34.5 66.6 PLB:PCI Mode 3:1. Acceptable Frequency Asynchronous Range 23.5 44.5 External Non-maskable Interrupt active polarity interrupt programmable PowerPC. Type Input V-tolerant Input Input
PCI_Speed
PCI_Bus_NM_Int
PCI_Bus_M_Int
External Maskable Interrupt active polarity interrupt programmable PowerPC.
Note: I/Os configured multi-point operation.
Figure 2-13. Timing Diagram
Outputs
PCI_Clk tVAL
tOFF
Inputs
VDD/2
Notes: Data Invalid
Output Load ohms
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Table 2-28. Timing Diagram Legend (for Figure 2-13)
Symbol tVAL tOFF Cycle Time Clock Width High Clock Width Worst Case Output Delay Turn Output Delay Turn Output Delay Input Setup Time Input Hold Time Symbol Description Minimum (ns) Maximum (ns)
Note: delays measured with slew time measured from 10-90% input voltage.
2.1.7 Management Interface Pins signals from these pins translated into various "host" buses external field-programmable gate array (FPGA) Serial/Parallel Manager (SPM). Table 2-29. Management Pins
Signal MG_Data Description Serial Data. Supports Address/Control/Data protocol. Type Input/Output V-tolerant Output V-tolerant Input V-tolerant
MG_Clk
33.33 clock
MG_nIntr
Rising-edge sensitive interrupt input
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Figure 2-14. Timing Diagram
Outputs
MG_Clk (MAX) (MIN)
MG_Data
Inputs MG_Data
VDD/2
Notes:
Data Invalid
Output Load ohms
Table 2-30. Timing Diagram Legend (for Figure 2-14)
Symbol Cycle Time Clock Pulse Width High Clock Pulse Width Data Output Delay Data Setup Time Data Hold Time Symbol Description Minimum (ns) 14.4 14.4 15.6 15.6 Maximum (ns)
Note: mg_nintr asynchronous input timed. delays measured with slew time measured from 10-90% input voltage.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
2.1.8 Miscellaneous Pins Table 2-31. Miscellaneous Pins (Page
Signal Description positive input differential pair. 50.6875 62.5 MHz. Generates clock domains. Required have cycle-to-cycle jitter ±150 Duty Cycle tolerance must ±10%. on-chip differential terminator ohms present between this complement pin. negative input differential pair. 50.6875 62.5 MHz. positive input differential pair. 50.6875 62.5 MHz. Generates clock domains. Required have cycle-to-cycle jitter ±150 Duty Cycle tolerance must ±10%. on-chip differential terminator ohms present between this complement pin. negative input differential pair. 50.6875 62.5 MHz. Type LVDS (see page 526) Input LVDS (see page 526) LVDS (see page 526) Input LVDS (see page 526) Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Output (o/d) V-tolerant LVTTL
IEW_Clock_A
IEW_Clock_A
IEW_Clock_B
IEW_Clock_B
Core_Clock
53.33 oscillator generates /133 clock domains. Required have cycle-to-cycle jitter ±150 Duty Cycle tolerance must ±10%. oscillator. Required have cycle-to-cycle jitter Duty Cycle tolerance must This clock required only when supporting GMII modes. Reset NP2G signal must driven active minimum ensure proper reset NP2G. input clocks (IEW_Clock_A, IEW_Clock_A, IEW_Clock_B, IEW_Clock_B, Core_Clock, Clock125 use, PCI_Clk) must running prior activation this signal. NP2G operational driven active when both NP2G Ingress Egress Macros have completed their initialization. remains active until subsequent Reset issued. Functional Mode, including concurrent JTAG interface RISCWatch CABWatch operations. Debug Mode Debug mode must indicated Testmode debug (DMU_D) output gated from probe. JTAG Test Mode LSSD Test Mode
Clock125
Reset
Operational
Testmode(1:0)
Input CMOS
JTAG_TRst
JTAG test reset. normal functional operation, this must connected same card source that connected Reset input. When JTAG interface used JTAG test functions, this controlled JTAG interface logic card. JTAG test mode select. normal functional operation, this should tied either high. JTAG test data out. normal functional operation, this should tied either high.
Input V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG test data normal functional operation, this should tied either high.
JTAG_TCk
JTAG test clock. normal functional operation, this should tied either high.
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-31. Miscellaneous Pins (Page
Signal Description These pins serve +1.8 Volt supply critical noise-sensitive portion phaselocked loop (PLL) circuits. serves analog each circuit. prevent noise these pins from introducing phase jitter outputs, place filters board level isolate these pins from noisy digital pins. Place separate filters each analog prevent noise from being introduced into another. section 2.1.9 Filter Circuit page filter circuit details. These pins serve ground connection critical noise portion phase lock loop (PLL). serves analog each circuit. Each should connected digital ground plane VDDA node filter capacitor shown Figure 2-16: Filter Circuit Diagram page Input thermal monitor (resistor). 2.1.10 Thermal Usage page details thermal monitor usage Output thermal monitor (resistor) Voltage reference SSTL2 I/Os (approximately four pins side device that contains SSTL2 I/O) Voltage reference SSTL2 I/Os (approximately four pins side device that contains SSTL2 I/O) Voltage reference SSTL2 I/Os (approximately four pins side device that contains SSTL2 I/O) Determines location network processor picocode load location. Load from Load from external source (typically Power bus) Determines location Power code start location. Start from Start from Unused signals needed Manufacturing Test. Spare_Tst_Rcvr (9:5,1) should tied card. Spare_Tst_Rcvr (4:2,0) should tied card. This signal, when asserted low, forces embedded PowerPC processor stop processing instructions. normal functional operation, this signal should tied inactive high. Programmable These used chip manufacturing test purposes should left unconnected card. Type
PLLA_VDD PLLB_VDD PLLC_VDD
Input PLL_VDD
PLLA_GND PLLB_GND PLLC_GND Thermal_In Thermal_Out VRef1(2), VRef2(8,7,6)
Input PLL_GND Thermal Thermal Input VRef 1.25 Input VRef 1.25 Input VRef 1.25 Input V-tolerant Input V-tolerant Input CMOS Input V-tolerant LVTTL Input/Output CMOS
VRef1(1), VRef2(5,4,3)
VRef1(0), VRef2(2,1,0)
Boot_Picocode
Boot_PPC
Spare_Tst_Rcvr(9:0)
C405_Debug_Halt
PIO(2:0) PGM_GND PGM_VDD
termination network details signals same those NP4GS3. guidelines contained PowerNP NP4GS3 Card Layout Guidelines.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Table 2-32. Signals Requiring Pull-Up Pull-Down
Signal Name Function Value
Signals requiring connection that same value applications Testmode(1:0) JTAG_TDI JTAG_TMS JTAG_TCk C405_Debug_Halt Spare_Tst_Rcvr (9:5, Spare_Tst_Rcvr (4:2, Reserved_IO (17:18) Reserved_IO (19:21, 23:26, 28:49, Reserved_IO (50:53) RES_Data RES_Sync Signals requiring connection that varies across different applications PCI_Speed MG_nIntr MG_Data Boot_Picocode Boot_PPC Choose down based system speed Pull-down system device drives this signal Pull-down when external module attached Choose down based picocode load location Choose down based code load location Pull when system diagnostics uses SRAM hold information through software controlled reset (see Software Controlled Reset Register (Soft_Reset) page 455). Pull-down Pull-up Pull-up Pull-up Pull-up Pull-down Pull-up Pull down Pull down GND1 Pull-up Pull-down connect with other signals Pull-down connect with other signals
LU_R_WRT, SCH_R_WRT
Signals that have connection, also require pull-up pull-down Operational DMU_A(0), DMU_C(0), DMU_D(0) DMU_A(30:29), DMU_C(30:29), DMU_D(30:29) DMU_A(4), DMU_C(4), DMU_D(4) D3_DQS(1:0), D2_DQS(1:0) D0_DQS(3:0), D4_DQS(3:0), D6_DQS(3:0) DS0_DQS(3:0), DS1_DQS(3:0) CPDetect 8-bit mode. RxAddr (1:0) mode. RxVal Pull-up control point then pull-down, otherwise pull-up Pull-down Pull-down Pull-down Pull-down Pull-down
eight I/Os that pulled same voltage connected single resistor value close ohms. individual resistors used, they 1000 ohms. Note: addition signals this table, interface signals used particular application should pulled their inactive state control signals either state data signals. This prevents extraneous switching circuitry, which cause current surges affect other signals.
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-33. Pins Requiring Connections Other Pins
First Grid Location AK01 AJ02 AF01 AE02 AH01 AH03 AE01 AE03 AD03 AD01 AC02 AC03 AB03 AA04 AA03 AG27 Second Grid Location AA01 AB01 AA02 AC06 AC05 AC07 AD05 AE04 AE05 AF03 AF05 AG04 AG02 AE25 Third Grid Location Notes
Note: pins same should connected together board. wiring congestion occurs, pins these rows rewired shown Table 2-34 Figure 2-15.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
alternate wiring scheme illustrated Table 2-34 Figure 2-15 used wiring congestion occurs. Note: This scheme applies only subset pins requiring connections other pins (see Table 2-33). Table 2-34. Alternate Wiring Pins Requiring Connections Other Pins
First Grid Location AK01 AJ02 AF01 AE02 AH01 AH03 AE01 AE03 AD03 AD01 AC02 AC03 AB03 AA04 AA03 Second Grid Location AC07 AG02 AF03 AD05 AG04 AF05 AE04 AE05 AC06 AA01 AB01 AC05 AA02
Figure 2-15. Alternate Wiring Pins Requiring Connection Other Pins
AK01 AH01 AF01 AE01 AB01 AA01
AD01
AE02 AJO2 AH03 AF03 AG04 AE04 AG02 AE03 AD03
AC02
AA02
AC03
AB03
AA03
AA04
AF05
AE05
AD05 AC05 AC06
AC07
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
2.1.9 Filter Circuit VDDA voltage supply analog circuits PLL. Noise VDDA causes phase jitter output PLL. VDDA brought package isolate from noisy internal digital signal. little noise expected board level, then VDDA connected directly digital plane. most circumstances, however, prudent place filter circuit VDDA shown below. Note: wire lengths should kept short possible minimize coupling from other signals. impedance ferrite bead should much greater than that capacitor frequencies where noise expected. Many applications have found that resistor does better reducing jitter than ferrite bead does. resistor should kept value lower than Experimentation best determine optimal filter design specific application. Note: filter circuit used PLLA PLLB, second filter circuit should used PLLC. Figure 2-16. Filter Circuit Diagram
Ferrite Bead Digital (via board) VDDA PLL)
2.1.10 Thermal Usage thermal monitor consists resistor connected between pins PADA PADB. 25°C this resistance estimated 1500 ohms. published temperature coefficient resistance this technology 0.33% determine actual temperature coefficient, Measurement Calibration page Figure 2-17. Thermal Monitor
Thermal PADA PADB
Note: There electrostatic discharge (ESD) diode PADA PADB.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
2.1.10.1 Temperature Calculation chip temperature calculated from chip (Rmeasured Rcalibrated) where: measured resistance measured between PADA PADB test temperature. calibrated resistance measured between PADA PADB known temperature. calibrated known temperature used measure calibrated. 2.1.10.2 Measurement Calibration this thermal monitor accurately, must first calibrated. calibrate, measure voltage drop different known temperatures package while device dissipating little (less than Tcalibrated
power. Apply wait fixed time where approximately Keep short minimize heating effects thermal monitor resistance. Then measure Next, turn change package temperature. Reapply Idc, wait again measure
temperature coefficient
-Idc
where: temperature change, voltage drop, applied current, Vsupply Maximum
PADA Thermal PADB
Maximum measure voltage drop
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Clocking Domains
Figure 2-18. Clock Generation Distribution
Clock Generator
Oscillator
IEW_Clk_A MHz)
IEW_Clk_B MHz)
NP2G 9.09 4.54-5 Clock Domain 9.09 4.54-5 Clock Domain Clock_Core
Divide
Divide
36.3 Divide 3.75
36.3 53.3
Core, DDR, Clock Domain
SMII, TBI, GMII Clock Domain Rx_Clk Tx_Clk Devices Note: IEW_Clk_A frequencies shown illustration purposes. These clocks range from 50.6875 62.5 MHz. Clock125 TBI, GMII DMU_*(03) SMII
NP2G Clock Connections page NP2G Clock Connections (POS Overview) page related clock information.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Figure 2-19. Pins Diagram
Corner
Signal Test Viewed through package Test Ground Note: illustrative purposes only.
VDD2 (3.3 VDD3 (2.5 VDD4 (2.5 VDD5 (2.5
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
Mechanical Specifications
Figure 2-20. Mechanical Diagram
view Chip
Lidless
Terminal identifier
±ccc Bottom view Note: location
±ccc
Notes:
Refer Table 2-35 page mechanical dimensions. Mechanical drawing scale. your representative more information. square outline conforms JEDEC MO-158.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
Table 2-35. Mechanical Specifications
Mechanical Dimensions Min2 (DLA) Max3 Min2 (Lidless) Max3
Weight
Value1 6.23 6.83 4.23 4.83 2.21 0.48 0.52 1.27 0.15 0.20 0.30 0.10 42.50 40.64 42.50 40.64 10885
Basic
dimensions millimeters, except where noted. Minimum package thickness calculated using nominal thickness parts. nominal thickness 8-layer package used package thickness. Maximum package thickness calculated using nominal thickness parts. nominal thickness 12-layer package used package thickness. matrix size. maximum number I/Os. number I/Os shown table amount after depopulation. Product with 1.27 pitch depopulated corner array.
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Network Processor
IEEE 1149 (JTAG) Compliance
2.4.1 Statement JTAG Compliance NP2G compliant with IEEE Standard 1149.1a. 2.4.2 JTAG Compliance Mode Compliance with IEEE 1149.1a enabled applying compliance-enable pattern compliance-enable inputs shown Table 2-36. Table 2-36. JTAG Compliance-Enable Inputs
Compliance-Enable Inputs Testmode(1:0) Spare_Tst_Rcvr(9) Spare_Tst_Rcvr(4) Spare_Tst_Rcvr(3) Spare_Tst_Rcvr(2) Compliance-Enable Pattern `10'
Note: achieve reset JTAG test logic, JTAG_TRst input must driven when compliance-enable pattern applied.
2.4.3 JTAG Implementation Specifics mandatory JTAG public instructions implemented NP2G's design. Table 2-37 documents implemented public instructions. Table 2-37. Implemented JTAG Public Instructions
Instruction Name BYPASS CLAMP EXTEST HIGHZ SAMPLE/PRELOAD Binary Code 1111 1101 1000 1010 1001
Serial Data connected TDI/TDO
Control Source (driver data driver enable) System, functional values JTAG JTAG JTAG, drivers disabled System, functional values
Bypass Bypass BoundaryScan Bypass BoundaryScan
Device output driver only enabled during Controller states Shift_IR Shift_DR.
Physical Description
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np2_ds_sec02_phys.fm.01 February 2003
PowerNP NP2G Preliminary Network Processor
2.4.4 Brief Overview JTAG Instructions
Instruction Description Connects bypass data register between pins. bypass data register single shift-register stage that provides minimum-length serial path between pins when test operation device required. Bypass does disturb normal functional connection control pins. Causes output pins driven from corresponding JTAG parallel boundary scan register. SAMPLE/PRELOAD instruction typically used load desired values into parallel boundary scan register. Since clamp instruction causes serial TDI/TDO path connected bypass data registers, scanning through device very fast when clamp instruction loaded. Allows JTAG logic control output values connecting each output data enable signal corresponding parallel boundary scan register. desired controlling values output data enable signals shifted into scan boundary scan register during shiftDR state. parallel boundary scan register loaded from scan boundary scan register during updateDR state. EXTEST instruction also allows JTAG logic sample input receiver output enable values. values loaded into scan boundary scan register during captureDR state. Causes JTAG logic tri-state output drivers while connecting bypass register serial TDI/TDO path. Allows JTAG logic sample input values load parallel boundary scan register without disturbing normal functional connection control pins. sample phase instruction occurs captureDR state, which time scan boundary scan register loaded with corresponding input receiver output enable values. (Note that input pins that connected common I/O, scan boundary scan register only updates with input receiver sample corresponding output driver common disabled; otherwise scan register updated with output data signal.) desired controlling values output pins shifted into scan boundary scan register during shiftDR state loaded from scan boundary scan register parallel boundary scan register during updateDR state.
BYPASS
CLAMP
EXTEST
HIGHZ
SAMPLE/PRELOAD
np2_ds_sec02_phys.fm.01 February 2003
Physical Description
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PowerNP NP2G Preliminary Network Processor
Signal Lists
Table 2-38. Complete Signal Listing Signal Name (Continued)
Table 2-38. Complete Signal Listing Signal Name
Signal Name Boot_Picocode Boot_PPC C405_Debug_Halt cam_cp_response(00) cam_cp_response(01) cam_cp_response(02) cam_cp_response(03) cam_cp_response(04) cam_cp_response(05) cam_cp_response(06) cam_cp_response(07) cam_cp_response(08) cam_cp_response(09) cam_cp_response(10) cam_cp_response(11) cam_cp_response(12) cam_cp_response(13) Clock125 Core_Clock D0_Addr(00) D0_Addr(01) D0_Addr(02) D0_Addr(03) D0_Addr(04) D0_Addr(05) D0_Addr(06) D0_Addr(07) D0_Addr(08) D0_Addr(09) D0_Addr(10) D0_Addr(11) D0_Addr(12) D0_CS D0_Data(00)
Grid Position AB23 AL10 AN10 AJ09 AN06 AA14 AB15 AM07 AL08 AM11 AL11 AC14 AG10 AF11 AN09 AA12
Signal Name D0_Data(01) D0_Data(02) D0_Data(03) D0_Data(04) D0_Data(05) D0_Data(06) D0_Data(07) D0_Data(08) D0_Data(09) D0_Data(10) D0_Data(11) D0_Data(12) D0_Data(13) D0_Data(14) D0_Data(15) D0_Data(16) D0_Data(17) D0_Data(18) D0_Data(19) D0_Data(20) D0_Data(21) D0_Data(22) D0_Data(23) D0_Data(24) D0_Data(25) D0_Data(26) D0_Data(27) D0_Data(28) D0_Data(29) D0_Data(30) D0_Data(31) D0_DQS(0) D0_DQS(1) D0_DQS(2)
Grid Position AD09 AG07 AB11 AN02 AM03 AN01 AN03 AL04 AG03 AH07 AE09 AL03 AC11 AJ06 AK05 AJ07 AN04 AN07 AL07 AF09 AG08 AE10 AD11 AN08 AL09 AL06 AM05 AB13 AC15 AK07 AJ08 AG09 AC12 AE11
Signal Name D0_DQS(3) D0_WE D2_Addr(00) D2_Addr(01) D2_Addr(02) D2_Addr(03) D2_Addr(04) D2_Addr(05) D2_Addr(06) D2_Addr(07) D2_Addr(08) D2_Addr(09) D2_Addr(10) D2_Addr(11) D2_Addr(12) D2_CS D2_Data(00) D2_Data(01) D2_Data(02) D2_Data(03) D2_Data(04) D2_Data(05) D2_Data(06) D2_Data(07) D2_Data(08) D2_Data(09) D2_Data(10) D2_Data(11) D2_Data(12) D2_Data(13) D2_Data(14) D2_Data(15) D2_DQS(0) D2_DQS(1)
Grid Position AH09 AM09 AJ22 AH21 AN21 AM21 AH23 AC20 AD21 AG23 AN22 AL21 AK23 AJ23 AA19 AL22 AN18 AJ19 AA18 AJ20 AL20 AN19 AE20 AE17 AE21 AG22 AN20 AM19 AK21 AJ21 AB19 AK25
February 2003
Physical Description
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PowerNP NP2G Preliminary Network Processor
Table 2-38. Complete Signal Listing Signal Name (Continued)
Signal Name D2_WE D3_Addr(00) D3_Addr(01) D3_Addr(02) D3_Addr(03) D3_Addr(04) D3_Addr(05) D3_Addr(06) D3_Addr(07) D3_Addr(08) D3_Addr(09) D3_Addr(10) D3_Addr(11) D3_Addr(12) D3_CS D3_Data(00) D3_Data(01) D3_Data(02) D3_Data(03) D3_Data(04) D3_Data(05) D3_Data(06) D3_Data(07) D3_Data(08) D3_Data(09) D3_Data(10) D3_Data(11) D3_Data(12) D3_Data(13) D3_Data(14) D3_Data(15) D3_DQS(0) D3_DQS(1) D3_WE D4_Addr(00) Grid Position AJ24 AG19 AJ16 AF17 AJ17 AG18 AE18 AA17 AC18 AK19 AL19 AN17 AK17 AE19 AL18 AG13 AA16 AG14 AE15 AL17 AM17 AL15 AK15 AE16 AG16 AH17 AG17 AG15 AF15 AF19 AG20 AC17 AD19 Signal Name D4_Addr(01) D4_Addr(02) D4_Addr(03) D4_Addr(04) D4_Addr(05) D4_Addr(06) D4_Addr(07) D4_Addr(08) D4_Addr(09) D4_Addr(10) D4_Addr(11) D4_Addr(12) D4_CS D4_Data(00) D4_Data(01) D4_Data(02) D4_Data(03) D4_Data(04) D4_Data(05) D4_Data(06) D4_Data(07) D4_Data(08) D4_Data(09) D4_Data(10) D4_Data(11) D4_Data(12) D4_Data(13) D4_Data(14) D4_Data(15) D4_Data(16) D4_Data(17) D4_Data(18) D4_Data(19) D4_Data(20) D4_Data(21) Grid Position Signal Name D4_Data(22) D4_Data(23) D4_Data(24) D4_Data(25) D4_Data(26) D4_Data(27) D4_Data(28) D4_Data(29) D4_Data(30) D4_Data(31) D4_DQS(0) D4_DQS(1) D4_DQS(2) D4_DQS(3) D4_WE D6_Addr(00) D6_Addr(01) D6_Addr(02) D6_Addr(03) D6_Addr(04) D6_Addr(05) D6_Addr(06) D6_Addr(07) D6_Addr(08) D6_Addr(09) D6_Addr(10) D6_Addr(11) D6_Addr(12) D6_ByteEn(0) D6_ByteEn(1) D6_CS D6_Data(00) D6_Data(01) D6_Data(02) D6_Data(03) Grid Position AL28 AN26 AE24 AG26 AF25 AL27 AN30 AJ27 AK29 AJ28 AL29 AG21 AH27 AG24 AF23 AL31 AL23 AM23 AL26 AM27
February 2003
Physical Description
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PowerNP NP2G Network Processor
Table 2-38. Complete Signal Listing Signal Name (Continued)
Signal Name D6_Data(04) D6_Data(05) D6
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