with PLL, based 64Mx4 SDRAM with LVTTL, banks Refresh HYM72V64C73
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64Mx72 bits PC133 SDRAM Registered DIMM
with PLL, based 64Mx4 SDRAM with LVTTL, banks Refresh
HYM72V64C736T4M Series Preliminary
HYM72V64C736T4M Series 64Mx72bits Synchronous DRAM Modules. modules composed eighteen 64Mx4bits CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, 2Kbit EEPROM 8pin TSSOP package 168pin glass-epoxy printed circuit board. 0.22uF 0.0022uF decoupling capacitors each SDRAM mounted PCB. HYM72V64C736T4M Series Dual In-line Memory Modules suitable easy interchange addition 512Mbytes memory. HYM72V64C736T4M Series fully synchronous operation referenced positive edge clock inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth.
FEATURES
PC133 PC100 support 1.125" (28.56mm) Height 168-Pin Registered DIMM with Double Sided support 0.22µF 0.0022µF decoupling capacitors adopted Serial Presence Detect with Serial EEPROM Register Buffers Inverter used (with PLL) Supports Flow-through Register mode (REGE) Meets other JEDEC specifications Single 3.3V±0.3V power supply device pins LVTTL compatible 8192 refresh cycles every 64ms Auto precharge/precharge banks flag Possible assert random column address every clock cycle Interleaved auto refresh mode Programmable burst lengths sequences 1,2,4,8,full page Sequential type 1,2,4,8 Interleave type Programmable /CAS latency clocks Support clock suspend/power down mode CKE0 Data mask function Mode register programming Burst termination command Self refresh provides minimum power, full internal refresh control
ORDERING INFORMATION
Part
HYM72V64C736T4M-H
Clock Frequency
133MHz
Internal Bank
Banks
Ref.
Power
Normal
SDRAM Package
TSOP-II
Plating
Gold
This document general product description subject change without notice. Hyundai Electronics does assume responsibility circuits described. patent licenses implied. Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
CK0~CK3 CKE0 /S0, BA0, /RAS, /CAS, REGE DQM0~DQM7 DQ63 SA0~2 NAME Clock Inputs Clock Enable Chip Select SDRAM Bank Address Address Address Strobe, Column Address Strobe, Write Enable Register Enable Data Input/Output Mask Data Input/Output Check Input/Output Power Supply (3.3V) Ground Clock Input Data Input/Output Address Input Write Protect Connection
HYM72V64C736T4M Series Preliminary
DESCRIPTION system clock input. other inputs registered SDRAM rising edge Controls internal clock signal when deactivated, SDRAM will states among power down, suspend self refresh Enables disables inputs except Selects bank activated during /RAS activity Selects bank read/written during /CAS activity Address RA12, Column Address CA9, CA12 Auto-precharge flag /RAS, /CAS define operation Refer function truth table details Register Enable which permits DIMM operateion Buffered Mode when REGE input Low, Registered Mode when REGE input High Controls output buffers read mode masks input data write mode Multiplexed data input output Check bits Power supply internal circuits input buffers Ground Serial Presence Detect Clock input Serial Presence Detect Data input/output Serial Presence Detect Address Input Write Protect Serial Presence Detect DIMM connection
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
ASSIGNMENTS
FRONT SIDE
HYM72V64C736T4M Series Preliminary
BACK SIDE
FRONT SIDE
BACK SIDE
NAME
NAME
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
NAME
DQM2 DQM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
NAME
*CK1 CKE0 DQM6 DQM7 DQ48 DQ49 DQ50 DQ51 DQ52 REGE DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 *CK3
Architecture
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 DQM1 A10/AP DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQM4 DQM5 /RAS
Voltage
Note connected with termination (Rsfer block diagram)
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
BLOCK DIAGRAM
HYM72V64C736T4M Series Preliminary
Note serial resistor values 10ohms padding capacitance termination CK1~CK3 12pF
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
SERIAL PRESENCE DETECT
BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 BYTE62 BYTE63 BYTE64 BYTE65 FUNCTION DESCRIPTION Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly (Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time @/CAS Latency=3 Access Time from Clock @/CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lenth Supported Banks Each SDRAM Device SDRAM Device Attributes, /CAS Lataency SDRAM Device Attributes, Lataency SDRAM Device Attributes, Lataency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @/CAS Latency=2 Access Time from Clock @/CAS Latency=2 SDRAM Cycle Time @/CAS Latency=1 Access Time from Clock @/CAS Latency=1 Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Minimum /RAS /CAS Delay (tRCD) Minimum /RAS Pulse Width (tRAS) Module Bank Density Command Address Signal Input Setup Time Command Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may used future) Revision Checksum Byte 0~62 Manufacturer JEDEC Code .Manufacturer JEDEC Code FUNCTION Bytes Bytes SDRAM Bank Bits LVTTL 7.8125us Self Refresh Supported tCCD 1,2,4,8,Full Page Banks /CAS Latency=3 Latency=0 Latency=0 Registered/Buffered inputs, with voltage tolerence, Burst Read Single Write, Precharge All, Auto Precharge, Early Precharge 20ns 15ns 20ns 45ns 512MB 1.5ns 0.8ns 1.5ns 0.8ns Intel 1.2B Hynix JEDED Unused Hynix (Korea Area) (United States Area) (Europe Area) (Japan Area) ASIA Area
HYM72V64C736T4M Series Preliminary
VALUE NOTE
BYTE72
Manufacturing Location
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
HYM72V64C736T4M Series Preliminary Continued
BYTE NUMBER
BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 BYTE87 BYTE91 BYTE92 BYTE93 BYTE94 BYTE95 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256
FUNCTION Manufacturer' Part Number (Component) Manufacturer' Part Number (256Mb based) Manufacturer' Part Number (Voltage Interface) Manufacturer' Part Number (Memory Width) .Manufacturer' Part Number (Memory Width) Manufacturer' Part Number (Module Type) Manufacturer' Part Number (Data Width) .Manufacturer' Part Number (Data Width) Manufacturer' Part Number (Refresh, SDRAM Bank) Manufacturer' Part Number (Package Type) Manufacturer' Part Number (Component Configuration) Manufacturer' Part Number Revision) Manufacturer' Part Number (Hyphen) Manufacturer' Part Number (Min. Cycle Time) Manufacturer' Part Number Revision Code (for Component) .Revision Code (for PCB) Manufacturing Date .Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may used future) Reserved Intel Specification detail 100MHz support Unused Storage Locations
FUNCTION
(SDRAM) (3.3V, LVTTL) 6(8K Refresh, 4Banks) based) M(Low Profile) (Hyphen) Blanks Process Code Process Code Work Week Year Serial Number None Refer Note9 Refer Note7
VALUE
NOTE
Note bank address excluded Interleave Burst Type adopted ASCII adopted Basically Hynix writes Part except HYM'in Byte 73~90 limited bytes from byte byte fixed dependent connected DIMM, junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge suport Refer most recent Intel JEDEC Specification These values applied PC100 applications only Intel SDRAM specification Refer Hynix site.
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Soldering Temperature Time TSTG VIN, VOUT VDD, VDDQ TSOLDER Symbol -1.0 -1.0 Rating
HYM72V64C736T4M Series Preliminary
Unit
Note Operation above absolute maximum rating adversely affect device reliability.
OPERATING CONDITION (TA=0 70°C)
Parameter Power Supply Voltage Input High voltage Input voltage Symbol VDD, VDDQ -0.3 VDDQ Unit Note
Note 1.All voltages referenced 2.VIH(max) acceptable 5.6V pulse width with <=3ns duration. 3.VIL(min) acceptable -2.0V pulse width with <=3ns duration.
OPERATING TEST CONDITION (TA=0 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter Input High Level Voltage Input Timing Measurement Reference Level Voltage Input Rise Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement Symbol Vtrip Voutref Value 2.4/0.4 Unit Note
Note 1.Output load measure access times equivalent gates capacitor (50pF). details, refer AC/DC output load circuit
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
CAPACITANCE (TA=25°C, f=1MHz)
Parameter CKE0 Input Capacitance /S0, A0~12, BA0, /RAS, /CAS, DQM0~DQM7 Data Input Output Capacitance DQ63 Symbol CI/O Unit
HYM72V64C736T4M Series Preliminary
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Output
Output 50pF
50pF
Output Load Circuit
Output Load Circuit
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
CHARACTERISTICS (TA=0 70°C, VDD=3.3±0.3V)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Symbol Min.
HYM72V64C736T4M Series Preliminary
Unit Note -2mA +2mA
Note 1.VIN 3.6V, other pins tested under 2.DOUT disabled, VOUT=0
CHARACTERISTICS
Speed Parameter Symbol Test Condition Operating Current IDD1 Burst length=1, bank active tRC(min), IOL=0mA VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. tCK(min), IOL=0mA banks active tRRC tRRC(min), banks active 0.2V CL=3 2400
Unit
Note
Precharge Standby Current IDD2P Power Down Mode IDD2PS
IDD2N Precharge Standby Current Power Down Mode IDD2NS Active Standby Current Power Down Mode IDD3P IDD3PS
IDD3N Active Standby Current Power Down Mode IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current
1120
IDD4 IDD5 IDD6
3000 4900
Note IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open Min. tRRC (Refresh cycle time) shown CHARACTERISTICS values measured with Registered
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Symbol System Clock Cycle Time Latency tCK3 tCHW tCLW tAC3 tCKS tCKH tOLZ 1000 Unit Note
HYM72V64C736T4M Series Preliminary
Clock High Pulse Width Clock Pulse Width Access Time From Clock Latency
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time Data Output Low-Z Time Data Output High-Z Time
Latency
tOHZ3
Note Registered DIMM, data delayed additional clock cycle register (this Device DIMM Assume (input rise fall time 1ns, 1ns, then [(tR+tF)/2-1]ns should added parameter Access times measured with input signals 1v/ns edge rate, from 0.8v 2.0v 1ns, then (tR/2-0.5)ns should added parameter
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
CHARACTERISTICS
Parameter Symbol Operation Cycle Time Auto Refresh Delay Active Time Precharge Time Bank Active Delay Delay Write Command Data-In Delay Data-In Precharge Command Data-In Active Command Data-Out Hi-Z Data-In Mask Command Precharge Data Latency Output Hi-Z Power Down Exit Time Self Refresh Exit Time Refresh Time tRRC tRCD tRAS tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPDE tSRE tREF 100K Unit Note
HYM72V64C736T4M Series Preliminary
Note Timing delay register considered registered DIMM command given tRRC after self refresh exit
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
DEVICE OPERATING OPTION TABLE
HYM72V64C736T4M-H
Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs 9CLKs 9CLKs 7CLKs 3CLKs 3CLKs 2CLKs 5.4ns 2.7ns
HYM72V64C736T4M Series Preliminary
Note DIMM/CAS Latency Device (Registered Mode)
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Burst Stop Auto Refresh Entry Self Refresh1 Exit Entry Precharge power down Exit Clock Suspend Entry Exit CKEn-1 CKEn
ADDR
A10/ code
Note
Note Exiting Self Refresh occurs asynchronously bringing from high Dont care, Logic High, Logic Low. =Bank Address, Address, Column Address, Opcode Operand Code, Operation
Rev. 0.1/Jun. 2001
PC133 SDRAM Registered DIMM
PACKAGE DEMENSION
HYM72V64C736T4M Series Preliminary
1/1000 inches)
5250(133.35)
157.48(4.0)
700(17.78)
450(11.43)
"C"1450(36.83)
1700(43.18)
250(6.35) 4550(115.57) 5013.78(127.35)
2150(54.61)
320(8.13) max.
(Front Side)
157.48(4.0) min.
(Rear Side)
1125(28.56)
50(1.27)
122.83(3.12)
78.74(2.0) R78.74 (2.0)
39.37(1.0) 125(3.175)
39.37(1.0) R78.74 (2.0)
125(3.175) 39.37(1.0) 78.74(2.0)
50(1.27)
DETAIL
DETAIL
DETAIL
NOTE Tolerances dimensions +/-5 (0.127) unless otherwise specified. Thickness includes Plating Metallization.
Rev. 0.1/Jun. 2001
100(2.54) min.
5.9(0.15)
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