Virtex2.5 Field Programmable Gate Arrays DS003-1 (v2.5 April 2001

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Virtex2.5 Field Programmable Gate Arrays DS003-1 (v2.5 April 2001

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Virtex2.5 Field Programmable Gate Arrays
DS003-1 (v2.5 April 2001
Product Specification
Features
Fast, high-density Field-Programmable Gate Arrays Densities from system gates System performance 66-MHz Compliant Hot-swappable Compact Multi-standard SelectIOinterfaces high-performance interface standards Connects directly ZBTRAM devices Built-in clock-management circuitry Four dedicated delay-locked loops (DLLs) advanced clock control Four primary low-skew global clock distribution nets, plus secondary local clock nets Hierarchical memory system LUTs configurable 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, 16-bit Shift Register Configurable synchronous dual-ported 4k-bit RAMs Fast interfaces external high-performance RAMs Flexible architecture that balances speed density Dedicated carry logic high-speed arithmetic Dedicated multiplier support Cascade chain wide-input functions Abundant registers/latches with clock enable, dual synchronous/asynchronous reset Internal 3-state bussing IEEE 1149.1 boundary-scan logic Die-temperature sensor diode Supported FPGA Foundationand Alliance Development Systems Complete support Unified Libraries, Relationally Placed Macros, Design Manager Wide selection workstation platforms SRAM-based in-system configuration Unlimited re-programmability Four programming modes 0.22 5-layer metal process 100% factory tested
Description
Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases silicon efficiency result from optimizing architecture place-and-route efficiency exploiting aggressive 5-layer-metal 0.22 CMOS process. These advances make Virtex FPGAs powerful flexible alternatives mask-programmed gate arrays. Virtex family comprises nine members shown Table Building experience gained from previous generations FPGAs, Virtex family represents revolutionary step forward programmable logic design. Combining wide variety programmable system features, rich hierarchy fast, flexible interconnect resources, advanced process technology, Virtex family delivers high-speed high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Table Virtex Field-Programmable Gate Array Family Members Device
XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV100
System Gates
57,906 108,904 164,674 236,666 322,970 468,252 661,111 888,439 1,124,022
Array
16x24 20x30 24x36 28x42 32x48 40x60 48x72 56x84 64x96
Logic Cells
1,728 2,700 3,888 5,292 6,912 10,800 15,552 21,168 27,648
Maximum Available
Block Bits
32,768 40,960 49,152 57,344 65,536 81,920 98,304 114,688 131,072
Maximum SelectRAM+Bits
24,576 38,400 55,296 75,264 98,304 153,600 221,184 301,056 393,216
2001 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS003-1 (v2.5 April 2001 Product Specification
www.xilinx.com 1-800-255-7778
Module
Virtex2.5 Field Programmable Gate Arrays
Virtex Architecture
Virtex devices feature flexible, regular architecture that comprises array configurable logic blocks (CLBs) surrounded programmable input/output blocks (IOBs), interconnected rich hierarchy fast, versatile routing resources. abundance routing resources permits Virtex family accommodate even largest most complex designs. Virtex FPGAs SRAM-based, customized loading configuration data into internal memory cells. some modes, FPGA reads configuration data from external PROM (master serial mode). Otherwise, configuration data written into FPGA (SelectMAPTM, slave serial, JTAG modes). standard Xilinx Foundationand Alliance SeriesDevelopment systems deliver complete design support Virtex, covering every aspect from behavioral schematic entry, through simulation, automatic design translation implementation, creation, downloading, readback configuration stream.
Xilinx thoroughly benchmarked Virtex family. While performance design-dependent, many designs operated internally speeds excess achieve MHz. Table shows performance data representative circuits, using worst-case timing parameters. Table Performance Common Circuit Functions Function Register-to-Register Adder Pipelined Multiplier Address Decoder 16:1 Multiplexer Parity Tree Chip-to-Chip HSTL Class LVTTL,16mA, fast slew Bits Virtex
Higher Performance
Virtex devices provide better performance than previous generations FPGA. Designs achieve synchronous system clock rates including I/O. Virtex inputs outputs comply fully with specifications, interfaces implemented that operate MHz. Additionally, Virtex supports hot-swapping requirements Compact PCI.
Module
www.xilinx.com 1-800-255-7778
DS003-1 (v2.5 April 2001 Product Specification
Virtex2.5 Field Programmable Gate Arrays
Virtex Device/Package Combinations Maximum
Table Virtex Family Maximum User Device/Package (Excluding Dedicated Clock Pins) Package CS144 TQ144 PQ240 HQ240 BG256 BG352 BG432 BG560 FG256 FG456 FG676 FG680 XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV100
Virtex Ordering Information
Example:
Device Type Speed Grade
XCV300
Temperature Range Commercial +85°C) Industrial -40°C +100°C) Number Pins Package Type Ball Grid Array Fine-pitch Ball Grid Array Plastic Quad Flat Pack High Heat Dissipation Thin Quad Flat Pack Chip-scale Package Figure Virtex Ordering Information
DS003-1 (v2.5 April 2001 Product Specification
www.xilinx.com 1-800-255-7778
Module
Virtex2.5 Field Programmable Gate Arrays
Revision History
Date 11/98 01/99 02/99 05/99 05/99 07/99 Version Initial Xilinx release. Updated package drawings specs. Update package drawings, updated specifications. Addition package drawings specifications. Replaced FG680 package drawings. Changed Boundary Scan Information changed Figure Boundary Scan Sequence. Updated Input Output delays. Added Capacitance info different Standards. Added tolerant information. Added Parameters waveforms Pin-to-pin Input Output Parameter tables Global Clock Input Output Setup Hold. Changed Configuration Information including Figures Added device-dependent listings quiescent currents ICCINTQ ICCOQ. Updated Input Output Delays based default standard LVTTL, Fast Slew Rate. Added Input Switching Characteristics Standard Adjustments. Speed grade update preliminary status, Power-on specification Clock-to-Out Minimums additions, hold time listing explanation, quiescent current listing update, Figure ADDRA input label correction. Added TIJITCC parameter, changed TOJIT TOPHASE. Update speed.txt file 1.96. Corrections 111036,111137, 112697, 115479, 117153, 117154, 117612. Modified notes Recommended Operating Conditions (voltage temperature). Changed Bank information VCCO CS144 package p.43. Updated Jitter Parameter table waveforms, added Delay Measurement Methodology table different standards, changed buffered line info Input/Output Timing measurement notes. TBCKO values; corrected FG680 package connection drawing; note about status CCLK after configuration. Modified "Pins listed statement. Speed grade update Final status. Modified Table 04/01 Added XCV400 values table under Minimum Clock-to-Out Virtex Devices. Corrected Units column table under Input Switching Characteristics. Added values table under SelectRAM Switching Characteristics. Corrected Pinout information devices BG256, BG432, BG560 packages Table Corrected BG256 Function Diagram. Revised minimums Global Clock Set-Up Hold LVTTL Standard, with DLL. Converted file modularized format. Virtex Data Sheet section. Revision
09/99
01/0
01/0
03/00 05/00 05/00 09/0
10/0
Virtex Data Sheet
Virtex Data Sheet contains following modules: DS003-1, Virtex 2.5V FPGAs:
Introduction Ordering Information (Module
DS003-3, Virtex 2.5V FPGAs:
Switching Characteristics (Module
DS003-2, Virtex 2.5V FPGAs:
Functional Description (Module
DS003-4, Virtex 2.5V FPGAs:
Pinout Tables (Module
Module
www.xilinx.com 1-800-255-7778
DS003-1 (v2.5 April 2001 Product Specification

Virtex2.5 Field Programmable Gate Arrays DS003-1 (v2.5 April 2001

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