FEPS DATA SHEET DESCRIPTION Fast Ethernet, Parallel Port, SC
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STP2002QFP
FEPS
DATA SHEET DESCRIPTION
Fast Ethernet, Parallel Port, SCSI (FEPS) STP2002QFP provides integrated high-performance fast wide SCSI, 10/100Base-T Ethernet, Centronics-compatible parallel port.
Fast Ethernet, Parallel Port, SCSI
FEATURES
IEEE 1496 SBus Master interface with support 64-bit mode access IEEE 1496 SBus Slave interface, 32-bit mode only 20-Mbps fast wide single-ended SCSI using QLogic FAS366 core 10-/100-Mbps Ethernet motherboard Media independent interface (MII) support external transceivers DMA2-compatible Centronics parallel port with maximum throughput Mbps Supports SBus-card device Provides path FCode PROM SBus boards IEEE standard 1149.1 (JTAG) support boundary- internal-scan testing
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STP2002QFP
FEPS Fast Ethernet, Parallel Port, SCSI
FUNCTIONAL DESCRIPTION
Interface
FEPS control data path signal interfacing shown Figure detailed listing each located page this data sheet.
RESET SB_ACK[2:0] SB_AS SB_BG SB_BR SB_CLK SB_D[31:0] SB_DATAPAR SB_LERR SB_PA[27:0] SB_RD SB_SEL SB_SIZ[2:0] ENET_BUFFER_EN_ ENET_COL ENET_CRS ENET_MDC ENET_MDIO0 ENET_MDIO1 ENET_RX_CLK ENET_RXD[3:0] ENET_RX_DV ENET_RX_ER ENET_TX_CLK ENET_TX_CLKO ENET_TXD[3:0] ENET_TX_EN SB_ET_INT FEPS STP2002QFP ID_CS PP_ACK PP_ACKDIR PP_AFXN PP_BSY PP_BSYDIR PP_DATA[7:0] PP_DIR PP_DSDIR PP_ERROR PP_INIT PP_PE PP_SLCT PP_SLCT_IN PP_STB SB_PP_INT
SBus
Ethernet
SB_SC_INT SCSI_ACK SCSI_ATN SCSI_BSY SCSI_CD SCSI SCSI_D[15:0] SCSI_DP[1:0] SCSI_IO SCSI_MSG SCSI_REQ SCSI_RST SCSI_SEL SCSI_XTAL1 SCSI_XTAL2
Parallel Port
JTAG_CLK JTAG_TDI Scan JTAG_TDO JTAG_TMS JTAG_RST
CLK_10M MODE STOP_CLOCK
Miscellaneous
Figure External Interfaces
Components
FEPS internal block diagram shown Figure following description each major components.
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FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP
SBus Adapter (SBA) This functional unit layer between channel engine interface SBus. provides buffering conversion between SBus channel engine interface. includes master port SBus side funnel SCSI, Ethernet, parallel port engines onto SBus, slave port provide SBus access those three engines. SBA's primary function data path flow control between SBus channel engine interface. supports only 32-bit programmed SBus. There 64-byte write buffers allow buffered writes. round-robin arbitration scheme used between three channel engines. Interrupts from channel engines directly SBus. contains software-accessible registers. master accesses: compliant with IEEE 1496. support 64-bit/32-bit transfer mode. support byte/half-word/word transfer size. support burst transfer size from bytes. have parity generation/checking. issue atomic transactions. support sizing. slave accesses: support byte/half-word/word access, burst transfer support 32-bit transfer mode. have parity generation/checking. generate late error. generate Rerun Ack. Have maximum latency less than SBus clocks. Channel Engine Interface (CEI) provides common interface three channel engines, thus reducing verification time. This interface limits amount awareness that concerning transactions. channel engine's specifies specific transaction size, executes exact transaction SBus. Signals either shared, going from engines, dedicated, going from channel engine to/from SBA. Transactions include slave write, slave read, write (channel engine memory). Ethernet Channel Engine (ECE) major functions provide media-access control (MAC) function 10-/100-Mbps CSMA/CD protocol-based network, provide high-performance two-channel DVMA host interface between BigMAC SBus. high-performance, full-duplex device permitting simultaneous transfers data to/from host memory to/from "wire." BigMAC portion compliant with IEEE 802.3u (100Base-T) standard. implements management portion external transceiver, defined IEEE 802.3 specification.
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FEPS Fast Ethernet, Parallel Port, SCSI
Ethernet transmit functions provide engine transferring frames from host memory BigMAC. contains local buffer bytes rate adaptation between available bandwidth SBus network. Ethernet receive functions supply engine transferring frames from BigMAC host memory. also contains local buffer bytes rate adaptation. Other features include: Conformation ISO/IEC 8802-3. Programmable network parameters standard's extension and/or private applications. Flexible transceiver choice MII. Host packet management descriptor rings. checksum support hardware. Transmit "gather" function. Programmable first alignment receive. Support 32-bit 64-bit SBus, maximum 64-byte bursts. SCSI Channel Engine SCSI channel consists SCSI DVMA (also referred SCSI Channel Engine) FAS366. FAS366 "fast wide" SCSI controller core integrated hard macro into FEPS. SCSI DVMA provides 64-byte buffers used transfer data to/from FAS366. FAS366 supplies 16-bit SCSI data path throughput Mbps. programmed access FAS366 driven SCSI DVMA. Several programmable registers used SCSI device driver direct SCSI engine FAS366 move blocks data to/from host memory to/from devices SCSI bus. Once transfer complete, interrupt generated SBus inform driver that block movement complete, freeing initiate further transfers. Parallel Port Engine This engine allows send data standard Centronics printer both programmed modes. parallel interface support bidirectional transfers using Xerox (master read/write) (master write) schemes. 64-byte buffer used data from Channel Engine Interface parallel port mode, depending direction transfer. synchrononus mode, port support data transfer rate Mbps. parallel port interface also provides data path read FCode EPROM when FEPS chip used SBus-extended card. external 8-bit latches needed most significant byte (MSB) least significant byte (LSB) EPROM address. JTAG JTAG Test Access Port other testability features built FEPS chip. JTAG macro, which implements IEEE standard 1149.1-1990, provides access test structures chip.
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FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP
SBus
SBus Adapter
Channel Engine Interface
SCSI Engine
Ethernet Engine
Parallel Port Engine
FEPS
SCSI
ENET
Parallel Port
FAS366
Parallel Port Core
SCSI
Parallel Port
Boot PROM
Figure FEPS Functional Block Diagram
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FEPS Fast Ethernet, Parallel Port, SCSI
SIGNAL DESCRIPTIONS
SBus Interface Signals
Signal Name RESET SB_ACK[2:0] Description Reset signal from SBus controller; used reset SBus devices power-on other time necessary. Slave acknowledge codes response master SB_SEL signals. Decoded follows: Idle/Wait Error acknowledgment Byte acknowledgment Rerun acknowledgment Word acknowledgment Double-word (64-bit) acknowledgment Half-word acknowledgment Reserved SB_AS SB_BG SB_BR SB_CLK SB_D[31:0] SB_DATAPAR SBus address strobe asserted SBus controller when physical address valid appropriate slave SB_SEL signal set. SBus grant, used SBus arbitration; SBus controller asserts this signal when available requesting master's use. SBus request, used SBus arbitration; SBus master asserts this signal when wants access bus. SBus clock generated SBus controller. rising edge provides SBus' timing reference used sample synchronous signals. SBus data, primarily data path, also used transfer virtual addresses SBus controller translation. SBus data parity; driven that total number signals checked group number. This signal generated time, parity errors will only reported data's source also generates parity. SBus late error; reports errors after acknowledgment already been issued. alternate report errors, without generating error acknowledgment. SBus physical address; SBus controller drives physical address lines with results virtual address translation performs SBus master.
SB_LERR SB_PA[27:0]
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STP2002QFP
SBus Interface Signals (Continued)
Signal Name SB_RD Description SBus direction; generated SBus master. When high during transfer, this signal indicates read (data transfer from slave master) operation requested. write (data transfer from master slave) operation indicated signal low. SBus slave select; each slave unique SB_SEL. After SBus controller determined which slave being addressed, asserts that slave's SB_SEL. SBus size lines; master encodes size transfer perform these three lines. Their decodes, active high, follows: Word bytes) transfer Byte transfer Half-word bytes) transfer Extended transfer Four-word bytes) transfer Eight-word bytes) transfer Sixteen-word bytes) transfer Two-word bytes) transfer
SB_SEL SB_SIZ[2:0]
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FEPS Fast Ethernet, Parallel Port, SCSI
SCSI Interface Signals
Signal Name SB_SC_INT SCSI_ACK SCSI_ATN SCSI_BSY SCSI_CD SCSI_D[15:0] SCSI_DP[1:0] SCSI_IO SCSI_MSG SCSI_REQ SCSI_RST SCSI_SEL SCSI_XTAL1 SCSI_XTAL2 Type Description SCSI interrupt request SBus SCSI acknowledge; signal that acknowledges information transfer handshake SCSI attention SCSI busy; OR-tied signal that indicates being used SCSI control/data; indicates whether control (active low) data (active high) information data SCSI data; 16-data-bit bus, most significant highest priority during arbitration phase. SCSI data parity; parity (active low) data bits SCSI_D[7:0], parity (active low) SCSI_D[15:8]. SCSI direction; signal that controls direction data movement data with respect initiator. True (active low) indicates input. SCSI message; signal generated target during message phase transfer sequence. SCSI request; signal generated target indicating request information transfer handshake. SCSI reset; OR-tied signal that indicates RESET condition. SCSI select; OR-tied signal used initiator select target, target reselect initiator. Input connection 40-MHz crystal used clock SCSI controller core (FAS366) Output connection 40-MHz crystal
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STP2002QFP
Ethernet Interface Signals
Signal Name ENET_BUFFER_EN_0 ENET_COL Type Description Ethernet buffer enable; when active high, this signal enables receive buffer board devices connected recognized. Ethernet collision; high upon detection collision medium remains while collision condition persists. response signal quality error. Ethernet carrier sense; high when either transmit receive function active. always during collision. cleared when both transmit receive functions idle. Ethernet management device clock; when active high, timing reference transfer information MDIO signal. Ethernet management device data on-board transceiver when active high, transceiver use. Ethernet management device data on-board transceiver when active high, transceiver Ethernet receive clock; continuous clock that provides timing reference transfer RX_DV, RXD, RX_ER signals. Ethernet receive data; bundle four data signals which transition synchronously with respect RX_CLK. RXD[0] least significant bit. Ethernet receive data valid; when active high, indicates that recovered decoded nibbles RXD[3:0] bundle being received that data synchronous RX_CLK. Ethernet receive error; (active high) more RX_CLK periods indicate that error (coding, etc.) detected somewhere frame presently being transferred. Ethernet transmit clock; continuous clock that provides timing reference transfer TX_EN, TXD, TX_ER signals. Ethernet transmit clock output; this output loops back clock signal ENET_TX_CLK input. Ethernet transmit data; bundle four data signals which transition synchronously with respect TX_CLK. TXD[0] least significant bit. Ethernet transmit enable; when (active high) indicates that nibbles being presented transmission. asserted with first nibble preamble remains while nibbles transmitted. Ethernet interrupt; Ethernet request SBus.
ENET_CRS
ENET_MDC ENET_MDIO0 ENET_MDIO1 ENET_RX_CLK ENET_RXD[3:0]
ENET_RX_DV
ENET_RX_ER
ENET_TX_CLK ENET_TX_CLKO ENET_TXD[3:0]
ENET_TX_EN
SB_ET_INT
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FEPS Fast Ethernet, Parallel Port, SCSI
Parallel Port Interface Signals
Signal Name ID_CS PP_ACK PP_ACKDIR PP_AFXN Type Description PROM chip select; selects FCode PROM FEPS mounted SBus exapnsion slot. Parallel port acknowledge; pulsed printer when received data from parallel port. Parallel port direction; signal high output acknowledge target, input acknowledge from target Parallel port audio feed; address byte; dual-function pin. During normal operations, high indicates autofeed active. During boot operations, high indicates address byte enabled FCode access. Parallel port busy; indicates that printer cannot accept another character. Parallel port busy direction; signal high output Busy target; input busy from target. Parallel port data bus; bidirectional data lines, LSB, MSB. Parallel port data direction; active high when data being output target, when data being input from target. Parallel port data strobe direction; active high when data strobe output target, when data strobe input from target. Parallel port error; high printer when detected error. Parallel port initialize; high address byte; dual-function pin. During normal operations, high indicates port initialization. During boot operations, high indicates high address byte enabled FCode access. Parallel port paper end; printer when paper. Parallel port select; printer when selected. Parallel port select when high, this signal selects printer. Parallel port data strobe; indicates printer that valid data available printer port. Parallel port interrupt; parallel port interrupt request SBus.
PP_BSY PP_BSYDIR PP_DATA[7:0] PP_DDIR PP_DSDIR PP_ERROR PP_INIT
PP_PE PP_SLCT PP_SLCT_IN PP_STB SB_PP_INT
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JTAG/Miscellaneous Signals
Signal Name CLK_10M JTAG_CLK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_RST MODE Type Description 10-MHz clock output; sets ENET clock 10-Mbps network with ticks JTAG clock; provides timing signals during scan mode JTAG test data serial-bit stream JTAG input data JTAG test data out; serial stream JTAG output data JTAG test mode select; serial stream controlling JTAG state machine JTAG reset; asynchronous JTAG state machine reset Mode select; configures FEPS stand-alone (forced high FCode PROM FEPS SBus card) mode compatibility with MACIO SLAVIO boards, chipset (forced FCode PROM accessed EBus through SLAVIO ASIC) mode that will conflict with starting address PROM connected SLAVIO. Power-on detect; used tri-state SCSI allow FEPS power cycled (for example, during "hot plugging") without generating glitches SCSI bus. Used during testing scan mode stop ENET SBus clocks. Thereafter JTAG clocks control scan timing.
STOP_CLOCK
FEPS Address
PA[27:00] 000_0000 880_0000 8C0_0000 C80_0000 FCode PROM SCSI channel Ethernet channel Parallel port channel Device
Total Count
Interface JTAG/Scan SBus SCSI Ethernet Miscellaneous Subtotal Power/Ground Total count Count
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FEPS Fast Ethernet, Parallel Port, SCSI
SIGNAL TIMING
following diagrams represent timing conditions most common FEPS functions.
SB_CLK SB_BR SB_BG SB_D[31:0]FFFFFFFF SB_DATAPAR SB_RD SB_A[27:0] SB_AS SB_ACK[2:0] SB_LERR SB_SEL 0000* 4090D65 5E5* 0AA* AF24* 53B* B49* F85* F5F* 000* 600* FFF* 6000* 017* E85* 6B0* EBC6* 629* C27* 588* 29D* FFFFFFFF
Figure SBus Read
SB_CLK SB_BR SB_BG SB_D[31:0] FFFFFFFF SB_DATAPAR SB_RD SB_A[27:0] SB_AS SB_ACK[2:0] SB_LERR SB_SEL 0000* 0000* 6800* FFFFFFF FFF*
Figure SBus Write
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STP2002QFP
CLK_40M SCSI_ATN SCSI_BSY SCSI_CD SCSI_IO SCSI_MSG SCSI_RST SCSI_SEL SCSI_ACK SCSI_REQ SCSI_D[15:0] DB6F SCSI_DP[0] SCSI_DP[1] SB_SC_INT 4F59 7F91 4860 5C58 B7B0
Figure SCSI Asynchronous Read
CLK_40M SCSI_ATN SCSI_BSY SCSI_CD SCSI_IO SCSI_MSG SCSI_RST SCSI_SEL SCSI_ACK SCSI_REQ SCSI_D[15:0] FFFF SCSI_DP[0] SCSI_DP[1] SB_SC_INT B757 53DB FC6E 857E DEDE 946F
Figure SCSI Asynchronous Write
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FEPS Fast Ethernet, Parallel Port, SCSI
CLK_40M SCSI_ATN SCSI_BSY SCSI_CD SCSI_IO SCSI_MSG SCSI_RST SCSI_SEL SCSI_ACK SCSI_REQ SCSI_D[15:0] DB6F SCSI_DP[0] SCSI_DP[1] SB_SC_INT 4F59 7F91 4860 5C58 B7B0 E8C5 4B39
Figure SCSI Synchronous Read
CLK_40M SCSI_ATN SCSI_BSY SCSI_CD SCSI_IO SCSI_MSG SCSI_RST SCSI_SEL SCSI_ACK SCSI_REQ SCSI_D[15:0] FFFF SCSI_DP[0] SCSI_DP[1] SB_SC_INT B757 53DB FC6E 857E DEDE 946F
Figure SCSI Synchronous Write
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STP2002QFP
ENET_COL ENET_CRS ENET_TX_CLK ENET_TX_CLKO ENET_TXD[3:0] ENET_TX_EN ENET_RX_CLK ENET_RXD[3:0] ENET_RX_DV ENET_RX_ER ENET_BUFFER_EN
Figure Ethernet
ENET_COL ENET_CRS ENET_TX_CLK ENET_TX_CLKO ENET_TXD[3:0] ENET_TX_EN ENET_RX_CLK ENET_RXD[3:0] ENET_RX_DV ENET_RX_ER ENET_BUFFER_EN
Figure Ethernet-Collision Detected
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FEPS Fast Ethernet, Parallel Port, SCSI
ID_CS PP_ACK PP_BSY PP_DATA[7:0] PP_DDIR PP_DSTRB PP_SLCT PP_AFXN PP_INIT PP_ACKDIR PP_BSYDIR PP_DSDIR PP_SLCT_IN SB_PP_INT
Figure Parallel Port-EPROM Read
ID_CS PP_ACK PP_BSY PP_DATA[7:0] PP_DDIR PP_DSTRB PP_SLCT PP_AFXN PP_INIT PP_ACKDIR PP_BSYDIR PP_DSDIR PP_SLCT_IN SB_PP_INT
Figure Parallel Port-IBM Read
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STP2002QFP
ID_CS PP_ACK PP_BSY PP_DATA[7:0] PP_DDIR PP_DSTRB PP_SLCT PP_AFXN PP_INIT PP_ACKDIR PP_BSYDIR PP_DSDIR PP_SLCT_IN SB_PP_INT
Figure Parallel Port-IBM Write
ID_CS PP_ACK PP_BSY PP_DATA[7:0] PP_DDIR PP_DSTRB PP_SLCT PP_AFXN PP_INIT PP_ACKDIR PP_BSYDIR PP_DSDIR PP_SLCT_IN SB_PP_INT
Figure Parallel Port-Xerox Read
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FEPS Fast Ethernet, Parallel Port, SCSI
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Symbol Supply voltage Input voltage range input current Power dissipation Parameter -0.5 -0.5 Units
Recommended Operating Conditions
Symbol VDD_CORE VDD_IO Parameter Core supply voltage supply voltage Input voltage Operating temperature 4.75 4.75 5.25 5.25 Units
Characteristics
Symbol Parameter Voltage input Conditions CMOS Voltage input high CMOS Low-to-high threshold voltage (Schmitt Trigger) High-to-low threshold voltage (Schmitt Trigger) Minimum hysteresis (Schmitt Trigger) CMOS CMOS CMOS Voltage output (TTL) 0.95 1.40 0.80 Units
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STP2002QFP
Characteristics (Continued)
Symbol Parameter Voltage output (CMOS) Conditions Voltage output high (TTL) Voltage output high (CMOS) Over full process variation, volts Units
Characteristics
SBus Interface Inputs Input signals RESET, SB_CLK, SB_SEL, SB_AS, SB_LERR, SB_BG.
SBus Interface Input Signals
Parameter tsck (min) (min) (min) Reference Signal SB_CLK SB_CLK SB_CLK Description SBus clock period Setup time Hold time Tester Condition Value (ns)
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FEPS Fast Ethernet, Parallel Port, SCSI
SBus Interface Outputs Output signals SB_BR, SB_ET_INT, SB_SC_INT, SB_PP_INT.
SBus Interface Output Signals
Parameter (max) (min) Reference Signal SB_CLK SB_CLK Description Propagation delay Propagation delay Tester Condition (pF) Value (ns)
SBus Interface Bidirectionals Bidirectional signals SB_D[31:0], SB_SIZ[2:0], SB_RD, SB_ACK[2:0], SB_DTPAR, SB_PA[27:0]. These signals must meet inputs. These signals must also meet outputs. Ethernet Inputs signals ENET_RX_ERR, ENET_RX_DV, ENET_RXD[3:0] Ethernet Input Signals table below.
Ethernet Input Signals
Parameter tmrs (min) tmrh (min) Reference Signal ENET_RX_CLK ENET_RX_CLK Description Setup time Hold time Tester Condition Value (ns)
ENET_CRS ENET_COL asynchronous system. ENET_RX_CLK input ENET_RX_CLK frequency should equal data rate received signal. example 100-Mbps traffic, frequency should MHz. accuracy should duty cycle should between 35-65%, both numbers inclusive. ENET_TX_CLKI input ENET_TX_CLKI frequency should equal data rate transmit data rate. tolerance duty cycle should between 65%, both numbers inclusive.
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STP2002QFP
Ethernet Outputs signals ENET_TX_EN, ENET_TXD[3:0], ENET_TX_CLKO, Ethernet Output Signals table below.
Ethernet Output Signals
Parameter tmxd (max) tmxd (min) Reference Signal ENET_TX_CLKI ENET_TX_CLKI Description Delay time Delay time Tester Condition (pF) Value (ns)
signal ENET_BUFFER_EN ENET_BUFFER_EN Signal table below.
ENET_BUFFER_EN Signal
Parameter tmbd (max) tmbd (min) Reference Signal ENET_TX_CLKI ENET_TX_CLKI Description Delay time Delay time Tester Condition (pF) Value (ns)
signal ENET_MDC ENET_MDC Signal table below.
ENET_MDC Signal
Parameter tmcd (max) Reference Signal SB_CLK Description Delay time Tester Condition (pF) Value (ns)
Ethernet Bidirectionals signals ENET_MDIO0 ENET_MDIO1 ENET_MDIO0 ENET_MDIO1 Signals table.
ENET_MDIO0 ENET_MDIO1 Signals
Parameter tmcs (min) tmch (min) tmcd (max) tmcd (min) Reference Signal SB_CLK SB_CLK SB_CLK SB_CLK Description Setup time Hold time Delay time Delay time Tester Condition (pF) Value (ns)
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FEPS Fast Ethernet, Parallel Port, SCSI
SCSI Interface Clock Timing details timings SCSI bus, refer FAS366 manual.
Figure SCSI Clock
FASTCLK Reset
Symbol Description Clock period (1/frequency) Synchronization latency 83.3 Unit Note
FASTCLK Reset
Symbol fCPA fCPS Description Clock frequency, asynchronous Clock frequency, synchronous Clock high Clock 14.58 14.58 0.65 0.65 Unit Note
synchronous SCSI transfers FASTCLK disabled, clock must also meet following requirements: 97.92 97.92 ns).
FASTCLK
Symbol fCPA fCPS Description Clock frequency, asynchronous Clock frequency, synchronous Clock high Clock 0.40 0.40 0.60 0.60 Unit
Note: signal CLK_10M, which output from FEPS, SCSI clock divided signal. 40-MHz SCSI clock, CLK_10M 10-MHz clock signal.
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SCSI Interface Asynchronous Output Signals
Parameter tardso (min) taadso (min) tarhdo (min) taahdo (min) Description Data setup reqn(out) Data setup ackn(out) Data hold from reqn(in) high Data hold from ackn(in) Tester Condition (pF) Value (ns)
SCSI Interface Asynchronous Input Signals
Parameter tarsdi (min) taadsi (min) tarhdi (max) taahdi (max) Description Data setup reqn(in) Data setup ackn(in) Data hold from reqn(in) Data hold from ackn(in) Tester Condition Value (ns)
SCSI Interface Asynchronous Bidirectional Signals
Parameter taaroh (max) taarol (max) taraoh (max) taraol (max) Description ackn(in) reqn(out) high ackn(in) high reqn(out) reqn(in) high ackn(out) high reqn(in) ackn(out) Tester Condition (pF) Value (ns)
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SCSI Synchronous Output Signals
Parameter tsasto (min) tsnego (min) tsdso (min) tshdo (min) Description reqn(out) ackn(out) assertion period reqn(out) ackn(out) negation period Data setup reqn(out) ackn(out) Data hold from reqn(out) ackn(out) Tester Condition (pF) Value (ns)
SCSI Synchronous Input Signals
Parameter tsrasti (min) tsrnegi (min) tsaasti (min) tsanegi (min) tsdsi (min) tshdi (min) Description reqn(in) assertion period reqn(in) negation period ackn(in) assertion period ackn(in) negation period Data setup reqn(in) ackn(in) Data hold reqn(in) ackn(in) Tester Condition Value (ns)
SCSI Fast Synchronous Output Signals
Parameter tsasto (min) tsnego (min) tsdso (min) tshdo (min) Description reqn(out) ackn(out) assertion period reqn(out) ackn(out) negation period Data setup reqn(out) ackn(out) Data hold from reqn(out) ackn(out) Tester Condition (pF) Value (ns)
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SCSI Fast Synchronous Input Signals
Parameter tsrasti (min) tsrnegi (min) tsaasti (min) tsanegi (min) tsdsi (min) tshdi (min) Description reqn(in) assertion period reqn(in) negation period ackn(in) assertion period ackn(in) negation period Data setup reqn(in) ackn(in) Data hold reqn(in) ackn(in) Tester Condition Value (ns)
Parallel Port Inputs These signals asynchronous system. They specified only testing purposes. signals PP_PE, PP_SLCT, PP_ERROR, MODE Parallel Port Input Signals table below.
Parallel Port Input Signals
Parameter Reference Signal SB_CLK SB_CLK Description Setup time Hold time Tester Condition Value (ns)
Parallel Port Outputs These signals asynchronous system. They specified only testing purposes. signals PP_INIT, PP_SLCTIN, PP_AFXN, PP_DSDIR, PP_BSYDIR, PP_ACKDIR, PP_DDIR Parallel Port Output Signals table below.
Parallel Port Output Signals
Parameter (max) (min) Reference Signal SB_CLK SB_CLK Description Delay time Delay time Tester Condition (pF) Value (ns)
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FEPS Fast Ethernet, Parallel Port, SCSI
Parallel Port Bidirectionals signals PP_D[7:0], PP_STB, PP_BSY, PP_ACK, system must meet inputs when output direction.
JTAG Inputs signals JTAG_RST, JTAG_TMS, JTAG_TDI, STOP_CLK JTAG Input Signals table below. maximum allowable frequency JTAG_CLK MHz.
JTAG Input Signals
Parameter (min) (min) Reference Signal JTAG_CLK JTAG_CLK Description Setup time Hold time Tester Condition Value (ns)
JTAG_RST asynchronous signal system, specification applies only when testing tester.
JTAG Outputs signal JTAG_TDO, output delay specified with respect negative edge JTAG_CLK clock, JTAG Output Signals table below timing.
JTAG Output Signals
Parameter (max) (min) Reference Signal JTAG_CLK JTAG_CLK Description Delay time Delay time Tester Condition (pF) Value (ns)
Thermal Resistance Versus Flow Approximately °C/W ft/min
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STP2002QFP
PACKAGE INFORMATION
Assignments
STP2002QFP Assignments table below describes assignments STP2002QFP 240-pin PQFP package.
STP2002QFP Assignments
Number Signal Name PP_STB PP_AFXN PP_ERROR MODE JTAG_TDI JTAG_RST JTAG_CLK JTAG_TMS VSS_IO JTAG_TDO STOP_CLK ENET_CRS VDD_IO ENET_COL VSS_IO ENET_TXD[3] ENET_TXD[2] VSS_IO ENET_TXD[1] ENET_TXD[0] ENET_TX_EN VSS_IO ENET_TX_CLK ENET_TX_CLKO VDD_IO ENET_RX_ER ENET_RX_CLK ENET_RX_DV ENET_RXD[0] VSS_CORE ENET_RXD[1] VDD_CORE ENET_RXD[2] ENET_RXD[3] I_SCSI_RDN I_SCSI_WRN I_SCSI_A3 I_SCSI_A1 I_SCSI_CSN I_SCSI_A0 I_SCSI_A2 I_SCSI_MODE1 I_SCSI_MODE0 I_SCSI_DACKN I_SCSI_RESETN Dual Function (FAS366 Test Mode Only)
STP2002QFP.backup.frm Page Monday, August 1997 3:19
STP2002QFP
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP Assignments (Continued)
Number Signal Name VSS_IO ENET_BUFFER_EN_0 ENET_MDC ENET_MDIO0 VDD_IO ENET_MDIO1 VSS_IO SCSI_D[11] SCSI_D[10] SCSI_D[9] VSS_IO SCSI_D[8] SCSI_IO SCSI_REQ VSS_IO SCSI_CD SCSI_SEL SCSI_MSG VSS_IO SCSI_RST SCSI_ACK SCSI_BSY VSS_IO SCSI_ATN SCSI_SDP[0] SCSI_D[7] VSS_IO SCSI_D[6] SCSI_D[5] SCSI_D[4] VSS_IO SCSI_D[3] SCSI_D[2] SCSI_D[1] VSS_IO SCSI_D[0] SCSI_SDP[1] SCSI_D[15] VSS_IO SCSI_D[14] SCSI_D[13] Dual Function (FAS366 Test Mode Only)
STP2002QFP.backup.frm Page Monday, August 1997 3:19
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP
STP2002QFP Assignments (Continued)
Number Signal Name SCSI_D[12] VSS_IO SCSI_XTAL1 SCSI_XTAL2 VDD_IO Reserved VSS_IO CLK_10M VSS_IO SB_SC_INT SB_ET_INT SB_PP_INT VSS_IO SB_CLK VDD_IO VDD_CORE SB_BR VSS_CORE VSS_IO SB_SEL SB_AS SB_D[0] VDD_IO SB_D[1] VSS_IO SB_D[2] SB_D[3] VSS_IO SB_D[4] SB_D[5] VDD_IO SB_D[6] VSS_IO SB_D[7] SB_D[8] VSS_IO SB_D[9] SB_D[10] VSS_IO SB_D[11] IO_SCSI_DB[11] IO_SCSI_DB[9] IO_SCSI_DB[10] IO_SCSI_DB[8] Dual Function (FAS366 Test Mode Only)
STP2002QFP.backup.frm Page Monday, August 1997 3:19
STP2002QFP
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP Assignments (Continued)
Number Signal Name VDD_IO SB_D[12] SB_D[13] SB_BG VSS_IO SB_D[14] SB_D[15] VSS_IO SB_D[16] VDD_IO SB_D[17] VSS_IO SB_D[18] SB_D[19] SB_D[20] VSS_IO SB_D[21] VDD_IO SB_D[22] VSS_IO SB_D[23] SB_D[24] VSS_IO SB_ACK[0] SB_ACK[1] VDD_IO SB_ACK[2] VSS_IO SB_D[25] VDD_CORE SB_D[26] VSS_IO SB_D[27] VSS_CORE SB_D[28] VSS_IO SB_D[29] VDD_IO SB_D[30] SB_D[31] VSS_IO IO_SCSI_DBP1 IO_SCSI_DB[14] IO_SCSI_DB[12] IO_SCSI_DB[13] Dual Function (FAS366 Test Mode Only)
STP2002QFP.backup.frm Page Monday, August 1997 3:19
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP
STP2002QFP Assignments (Continued)
Number Signal Name SB_SIZ[2] SB_SIZ[1] VSS_IO SB_SIZ[0] VDD_IO SB_RD VSS_IO SB_PA[0] SB_PA[1] SB_PA[2] VSS_IO SB_PA[3] SB_PA[4] VSS_IO SB_PA[5] VDD_IO SB_LERR SB_PA[6] VSS_IO SB_PA[7] SB_PA[8] VSS_IO SB_PA[9] VDD_IO SB_PA[10] VSS_IO SB_PA[11] SB_PA[12] VSS_IO SB_PA[13] VDD_IO SB_PA[14] SB_PA[15] VSS_IO SB_PA[16] SB_PA[17] VSS_IO SB_PA[18] VDD_IO SB_PA[19] IO_SCSI_DBP0 IO_SCSI_DB[01] IO_SCSI_DB[00] IO_SCSI_DB[04] IO_SCSI_DB[03] IO_SCSI_DB[02] IO_SCSI_DB[05] Dual Function (FAS366 Test Mode Only) IO_SCSI_DB[07] IO_SCSI_DB[06]
STP2002QFP.backup.frm Page Monday, August 1997 3:19
STP2002QFP
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP Assignments (Continued)
Number Signal Name SB_PA[20] SB_PA[21] SB_PA[22] VSS_IO SB_PA[23] VDD_IO SB_PA[24] VSS_IO SB_PA[25] VDD_CORE SB_PA[26] VSS_IO VSS_CORE SB_PA[27] SB_DATPAR RESET ID_CS PP_SLCT PP_PE VDD_IO PP_BSYDIR VSS_IO PP_BSY PP_ACKDIR PP_ACK PP_DDIR PP_D[7] VSS_IO PP_D[6] PP_D[5] VDD_IO PP_D[4] PP_D[3] PP_D[2] VSS_IO PP_D[1] PP_D[0] PP_SLCT_IN I_SCSI_DBWRN I_SCSI_DBRDN I_SCSI_PAUSE Dual Function (FAS366 Test Mode Only)
STP2002QFP.backup.frm Page Monday, August 1997 3:19
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP
STP2002QFP Assignments (Continued)
Number Signal Name PP_INIT VDD_IO PP_DS_DIR VSS_IO Dual Function (FAS366 Test Mode Only)
STP2002QFP.backup.frm Page Monday, August 1997 3:19
STP2002QFP
FEPS Fast Ethernet, Parallel Port, SCSI
PACKAGE DIMENSION INFORMATION
FEPS packaged plastic quad flat pack (PQFP) with leads. Below mechanical drawing.
View
Side View
Dimension (mm) 4.10 0.25 3.20 3.40
Dimension (inch) 0.181 0.010
Dimension (mm) 10.5°
3.60 0.126 0.134 0.142 1.352 1.260 1.362 1.260 0.75 0.18 0.024 0.030 0.052 0.25 0.005 0.007 0.010 0.005
34.60 32.00 34.60 32.00 0.45 0.60
0.40
Dimension (inch) 10.5° 0.00 0.20 0.20 0.08 0.00 0.10 0.015
1.30 0.13 0.13 0.17 0.17 0.09 0.08 0.025 0.05 10.5° 2.5° 0.22 0.20 0.19
0.27 0.007 0.009 0.011 0.23 0.007 0.008 0.009 0.20 0.004 0.15 0.004 0.008 0.008
Notes: dimensions tolerances conform ANSI Y14.5M-1982. Datums determined Datum Plane -H-. determined Seating Plane -C-. Dimensions include mold protrusion. Allowable protrusion 0.255 side. Dimensions maximum plastic body size dimensions including mold mismatch. Controlling dimension: millimeter. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08 total excess dimension maximum material condition. Dambar cannot located lower radius foot. When converting from millimeters inches, four significant digits right decimal point necessary board layout purposes. Minimum space between lead 0.15 (0.006") regardless conformance with lead positionaltolerance ddd. This variation standard configuration. other variations available options only.
0.020 0.003 10.5° 2.5°
STP2002QFP.backup.frm Page Monday, August 1997 3:19
FEPS Fast Ethernet, Parallel Port, SCSI
STP2002QFP
ORDERING INFORMATION
Part Number STP2002QFP
Description Fast Ethernet, Parallel Port, SCSI (FEPS)
Document Part Number: STP2002
STP2002QFP.backup.frm Page Monday, August 1997 3:19
STP2002QFP
FEPS Fast Ethernet, Parallel Port, SCSI
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