Master STP2000 Master Controller integrated SBus master device wi

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Master STP2000 Master Controller integrated SBus master device wi

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STP2000QFP
Master
STP2000 Master Controller integrated SBus master device with built-in standard capabilities general purpose computing embedded applications. STP2000 directly interfaces through system bus, SBus, three major channels peripherals. channels include SCSI-II, ethernet parallel port. Together, with STP2001 Slave Controller, provides complete subsystem. STP2000 SBus interface 32-bit interface that supports both slave modes. There data buffering flow control each channels. Each channel access SBus through controller which capable transfers 32-byte bursts. SBus slave port used mostly status control. STP2000 incorporates ethernet controller, Fast 8-bit SCSI-II controller, Centronics parallel port controller single package. SCSI-II channel directly drives external peripherals. ethernet channel connected external transceiver chip that supports twisted pair ethernet ethernet. parallel port channel routed external transceivers.
32-bit SBus Master Controller
Features
Single-chip solution standard SPARC DVMA devices Compatible with microSPARC, SuperSPARC SBus based system Supports concurrent MByte/sec SCSI transfers, 1.25 MByte/sec Ethernet transfers, MByte/sec Parallel Port transfers Direct master/slave SBus interface JTAG internal boundary SCAN logic 160-pin PQFP packaging also available from Corp. NCR89C100)
Benefits
Saves cost, power, board space, weight Standard low-cost solution Improved system performance
Improved system performance Improved chip board level testability Cost effective packaging Second source
STP2000QFP
Master 32-bit SBus Master Controller
BLOCK, APPLICATION, LOGIC DIAGRAMS
SBus Control JTAG XTAL Osc. SBUS DVMA Master Data Address Slave Clocks Interrupts PROM
Parallel Port
ETHERNET® Controller (NCR92C990)
SCSI Controller (NCR53C9x)
Data
Control
Data Control
Data
Control
CENTRONICS® Parallel Port
Ethernet Network Adaptor
SCSI
Figure STP2000 Block Diagram
SCSI Connector SCSI Ethernet Parallel
160-Pin Connector Video Floppy Key/Mouse Audio Serial
DRAM Banks RAMDAC VRAM Bank MicroSPARC STP2000 Master Frame Buffer
SBUS
Slot Slot SBus Connectors
STP2001 Slave Floppy Connector Internal EBus
TOD/NVRA
Boot PROM
Figure STP2000 Typical Application
Master 32-bit SBus Master Controller
STP2000QFP
SCSI_D[7:0] SCSI_DP SCSI_SEL SB_A26 593.51 lB*BT5.75 5.75241.09 588.67 TmCK[0-2:0] SCSI_BSY SB_RESET SB_LERR SB_CLK SB_RD SB_SEL SB_D_IRQ SB_E_IRQ SB_P_IRQ SB_SIZ[2:0] MACIO_SEL SB_PA_W SB_PA_X SB_PA_Y SB_PA[5:0] SB_AS ENET_AUI ENET_TX ENET_TENA ENET_CLSN ENET_RX ENET_RENA ENET_TCLK ENET_RCLK SCC_20_IN SCC_20_OUT SCC_CLK20 FPY_24_IN FPY_24_OUT FPY_CLK24 FPY_32_IN FPY_32_OUT FPY_CLK32 JTAG_TDO JTAG_TDI JTAG_CLK JTAG_TMS JTAG_RST P_DATA[0-7] P_D_STRB P_BSY P_ACK (ELP_PE) P_PE P_SLCT P_ERROR P_INIT P_SLCT_IN P_AFXN P_DS_DIR P_BSY_DIR P_ACK_DIR P_D_DIR ID_CS SCSI_REQ SCSI_ACK SCSI_MSG SCSI_CD SCSI_IO SCSI_ATN SCSI_RST SCSI_XTAL_IN SCSI_XTAL_OUT
Figure STP2000 Logical Connections
STP2000QFP
Master 32-bit SBus Master Controller
SIGNAL DESCRIPTIONS
SBus Interface
Name SB_D[31:0] SB_BR SB_BG SB_ACK[2:0] SB_RESET SB_LERR SB_CLK SB_RD SB_SEL SB_D_IRQ SB_E_IRQ SB_P_IRQ SB_SIZ[2:0] SB_AS CHIP_SEL SB_PA[W] SB_PA[X] SB_PA[Y] SB_PA[5:0] Type Input Input Input Input Input Output Output Output Input Input Input Input Input Input SBus Data (MSB) SBus Request SBus Grant SBus Acknowledge SBus Reset SBus Late Error (INT15) SBus Clock Input SBus Read/Write SBus Select SBus Interrupt SCSI transfers (open-drain) SBus Interrupt ETHERNET transfers (open-drain) SBus Interrupt Parallel Port Transfers (open-drain) SBus Transfer Size SBus Address Strobe (address valid) High order physical address High order physical address High order physical address High order physical address order physical address bits Description
CHIP_SEL additional qualifier (active high) SB_SEL line. some system configurations where STP2000 (Master Controller) STP2001 (Slave Controller) share single SBus select line, PA[27] used select between two.
Master 32-bit SBus Master Controller
STP2000QFP
Ethernet Interface
Name ENET_AUI ENET_TX ENET_TENA ENET_CLSN ENET_RX ENET_RENA ENET_TCLK ENET_RCLK Type Output Output Output Input Input Input Input Input Ethernet TP/AUI select Ethernet Transmit data Ethernet Transmit enable Ethernet Collision detect Ethernet Receive data Ethernet Receiver enable (carrier sense) Ethernet Transmit clock Ethernet Receive clock Description
Drives input AT&T T7213 chip select between twisted pair AUI-type Ethernet interfaces, with ENET_AUI selecting AUI.
SCSI Interface
Name SCSI_D[7:0] SCSI_DP SCSI_SEL SCSI_BSY SCSI_REQ SCSI_ACK SCSI_MSG SCSI_CD SCSI_IO SCSI_ATN SCSI_RST SCSI_XTAL_IN SCSI_XTAL_OUT Type Input Output SCSI Data SCSI Data Parity SCSI Select SCSI Busy SCSI Request SCSI Acknowledge SCSI Message SCSI Command/Data SCSI Input/Output SCSI Attention SCSI Reset SCSI Clock Crystal (can drive with external CMOS clock) SCSI Clock Crystal (must connect external load) Description
SCSI pads (except crystal oscillator pads) custom bidirectional open-drain pads with hysteresis inputs.
Parallel Port Interface
Name P_DATA[7:0] P_D_STRB P_BSY Type 3-State Parallel Port Data Parallel Port Data Strobe pull-down) Parallel Port Busy pull-up) Description
STP2000QFP
Master 32-bit SBus Master Controller
Parallel Port Interface
Name P_ACK (ELP_PE) P_PE P_SLCT P_ERROR P_INIT P_SLCT_IN P_AFXN P_DS_DIR P_BSY_DIR
Type Input Output Output Output Output Output Output Output Output
Description Parallel Port Acknowledge pull-down) Parallel Port Paper Error Parallel Port Select Parallel Port Error Parallel Port Initialize Parallel Port Select Parallel Port Auto Feed Parallel Port Data Strobe Direction Parallel Port Busy Direction Parallel Port Acknowledge Direction Parallel Port Data Direction Secondary Device Select (boot prom) output; pull specify absence external PROM
P_ACK_DIR P_D_DIR ID_CS
Parallel Port control data line direction bits, (for example, P_*_DIR), gang programmed Transfer Control Register. DIR=0 sets transfer direction away from STP2000 (P_D_DIR=P_DS_DIR=1; P_BSY_DIR=P_ACK_DIR=0); DIR=1 sets transfer direction towards STP2000 (P_D_DIR=P_DS_DIR=0; P_BSY_DIR=P_ACK_DIR=1).
JTAG Interface
Name JTAG_TDO JTAG_TDI JTAG_CLK JTAG_TMS JTAG_RST Type Output Input Input Input Input JTAG Test Data Output JTAG Test Data Input (100 pull-up) JTAG Clock JTAG Test Mode Select (100 pull-up) JTAG Reset (100 pull-up) Description
Clock/Oscillator Interface
Name SCC_20_IN SCC_20_OUT SCC_CLK20 FPY_24_IN FPY_24_OUT FPY_CLK24 Type Input Output Output Input Output Output Description Clock Crystal (19.66 MHz) (can drive with external CMOS clock) Clock Crystal (19.66 MHz) (must connect external load) Clock (19.66 MHz) Floppy Clock Crystal MHz) (can drive with external CMOS clock) Floppy Clock Crystal MHz) (must connect external load) Floppy Clock MHz)
Master 32-bit SBus Master Controller
STP2000QFP
Clock/Oscillator Interface (Continued)
Name FPY_32_IN FPY_32_OUT FPY_CLK32 Type Input Output Output Description Floppy Clock Crystal MHz) (can drive with external CMOS clock) Floppy Clock Crystal MHz) (must connect external load) Floppy Clock MHz)
some system configurations, STP2000 provides these three clocks STP2001 (Slave Controller) (which limited). These really general-purpose 20-50 crystal oscillator pads that operate both fundamental overtone mode.
STP2000QFP
Master 32-bit SBus Master Controller
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Symbol Power supply voltage Input voltage Current Drain Lead temperature (less than second soldering) Operating temperature Storage temperature Parameter Rating +150 Units
Operation device values excess those listed above will result degradation destruction device. voltages defined with respect ground. Functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
Recommended Operating Conditions
Symbol Supply voltage Operating Temperature Power consumption SBus) Parameter 4.75 5.25 1400 Units
Capacitance
Symbol COUT CSCSI Input capacitance Output capacitance Bidirectional capacitance SCSI capacitance Parameter Units
Master 32-bit SBus Master Controller
STP2000QFP
Characteristics
Symbol Input high voltage Input voltage High level output voltage level output voltage Input leakage current High level source current (VOH 16.0 24.0 level sink current (VOL -2.0 -4.0 -8.0 -16.0 -24.0 -48.0 SCSIPAD (VOL SCSIPADF (VOL Parameter Units
STP2000QFP
Master 32-bit SBus Master Controller
Characteristics: SBus Timing
Signal Clock Period Clock High Clock Hold Rising Setup Rising Hold Rising Parameter Conditions 40.0 17.0 17.0 15.0 load load 60.0 22.5 20.0 Units
Hold Rising Rising Output Valid Rising Output Invalid
This only violation SBus Specification B.0. known implementation date provides less than hold time these signals.
Characteristics: Parallel Port Timing
Signal Parameter P_D_STRB P_D_STRB nominal width P_DATA valid P_D_STRB assert P_DATA valid (nominal) P_ACK, P_BSY setup P_ACK, P_BSY input pulse width P_D_STRB setup P_D_STRB input pulse width P_DATA setup P_D_STRB P_DATA input hold from P_D_STRB P_D_STRB P_BSY valid P_ACK, P_BSY P_ACK, P_BSY nominal pulse width output Conditions DSW=0,1,2,3 DSS=0, DSN=3 Units
SB_CLK periods
SB_CLK periods
SB_CLK periods
SB_CLK periods
SB_CLK periods SB_CLK periods
SB_CLK periods
Master 32-bit SBus Master Controller
STP2000QFP
Characteristics: SCSI TIming
Signal Clock period (tCP) Synchronization latency With FASTCLK reset Clock frequency, asynchronous 14.58 14.58 With FASTCLK Clock frequency, asynchronous Clock frequency, synchronous Clock high Clock (tCL) Asynchronous SCSI Data setup SCSI_ACK/SCSI_REQ Data hold from SCSI_REQ high/SCSI_ACK SCSI_ACK SCSI_REQ high SCSI_ACK high SCSI_REQ (data already setup) SCSI_REQ high SCSI_ACK high SCSI_REQ SCSI_ACK (data already setup) Data setup SCSI_REQ/SCSI_ACK Data hold from SCSI_REQ/SCSI_ACK Synchronous SCSI Normal SCSI Data setup SCSI_REQ/SCSI_ACK Data hold from SCSI_REQ/SCSI_ACK SCSI_REQ/SCSI_ACK assertion period SCSI_REQ/SCSI_ACK negation period Synchronous SCSI Fast SCSI Data setup SCSI_REQ/SCSI_ACK Data hold from SCSI_REQ/SCSI_ACK SCSI_REQ/SCSI_ACK assertion period SCSI_REQ/SCSI_ACK negation period FIFO full. FIFO full. FIFO empty 0.40 0.40 0.60 0.60 0.65 0.65 Clock frequency, synchronous Clock high Clock (tCL) Parameter Conditions 83.3 Units
STP2000QFP
Master 32-bit SBus Master Controller
Characteristics: SCSI TIming (Continued)
Signal Parameter Conditions Synchronous SCSI Input Cycle Data setup SCSI_REQ/SCSI_ACK Data hold from SCSI_REQ/SCSI_ACK SCSI_REQ assertion period SCSI_REQ negation period SCSI_ACK assertion period SCSI_ACK negation period Units
These minimum numbers required comply with ANSI SCSI spec. Synchronous SCSI data transfers FASTCLK enabled, clock inputs must also meet following requirements: tCL> 97.92 97.92
Characteristics: Ethernet Timing
Signal ENET_TCLK period ENET_TCLK high pulse duration ENET_TCLK pulse duration ENET_TCLK rise time ENET_TCLK fall time ENET_TENA propagation delay after rising edge ENET_TCLK ENET_TENA hold time after ENET_TCLK rising ENET_TX propagation delay after ENET_TCLK rising ENET_TX hold time after ENET_TCLK rising ENET_RCLK period ENET_RCLK high pulse duration ENET_RCLK pulse duration ENET_RCLK rise time ENET_RCLK fall time ENET_RX data rise time ENET_RX data fall time ENET_RX data hold time from ENET_RCLK rising ENET_RX data setup time ENET_RCLK rising ENET_RENA duration ENET_CLSN high duration ENET_RENA hold time after rising edge ENET_RCLK ENET_RENA defer before ENET_TENA ENET_RENA extended after ENET_RCLK last falling Parameter Units
Master 32-bit SBus Master Controller
STP2000QFP
TIMING DIAGRAMS
SB_CLK
SB_BG, SB_SEL
SB_PA[W, 5:0] CHIP_SEL, SB_RD SB_AS, SB_D[31:0] SB_SIZ[2:0] SB_ACK[2:0] SB_LERR
Figure SBus Input Timing
SB_CLK
SB_RD, SB_D[31:0] SB_ACK[2:0] SB_SIZ[2:0] SB_BR
Figure SBus Output Timing
STP2000QFP
Master 32-bit SBus Master Controller
SB_CLK P_D_STRB(out) P_DATA[7:0] (out) P_ACK (in)
P_BSY (in)
Figure Parallel Port Input Timing
SB_CLK P_D_STRB(out) P_DATA[7:0] (out) P_ACK (in)
P_BSY (in)
Figure Parallel Port Output Timing
SB_CLK P_SLET_IN, P_AFXN, P_INIT, P_ACK_DIR, P_BSY_DIR P_DS_DIR, P_D_DIR
Figure Parallel Port Other Timing
Master 32-bit SBus Master Controller
STP2000QFP
SCSI_STAL_IN
Figure SCSI Clock Timing
SCSI_REQ (out)
SCSI_ACK (out)
SCSI_REQ (in)
SCSI_ACK (in)
SCSI_D
Figure SCSI Asynchronous Input Timing
SCSI_REQ (out)
SCSI_ACK (out)
SCSI_REQ (in)
SCSI_ACK (in)
SCSI_D
Figure SCSI Asynchronous Output Timing
STP2000QFP
Master 32-bit SBus Master Controller
SCSI_REQ (in)
SCSI_ACK (in) SCSI_D (in)
Figure SCSI Synchronous Input Timing
SCSI_REQ (out)
SCSI_ACK (out) SCSI_D (in)
SCSI_D (out)
Figure SCSI Synchronous Output Timing
Master 32-bit SBus Master Controller
STP2000QFP
ENET_TCLK
ENET_TENA
ENET_TX
ENET_RCLK
ENET_RENA
ENET_RX
Figure Ethernet Transmit/Receive Timing
ENET_CLSN
Figure Ethernet Collision Timing
STP2000QFP
Master 32-bit SBus Master Controller
PACKAGE INFORMATION
160-Pin PQFP Assignment
Name SB_D[22] SB_D[23] SB_D[24] SB_D[25] SB_D[26] SB_D[27] SB_D[28] SB_D[29] SB_D[30] SB_D[31] ID_CS SB_RESET SB_P_IRQ SB_E_IRQ P_ACK P_BSY P_D_STRB P_DATA[7] P_DATA[6] Name P_DATA[5] P_DATA[4] P_DATA[3] P_DATA[2] P_DATA[1] P_DATA[0] P_ERROR P_SLCT P_PE P_SLCT_IN P_AFXN P_INIT P_ACK_DIR P_BSY_DIR P_DS_DIR P_D_DIR FPY_CLK24 FPY_24_OUT FPY_24_IN FPY_32_IN FPY_32_OUT FPY_CLK32 ENET_AUI ENET_TX ENET_TENA ENET_CLSN ENET_RX ENET_RENA ENET_TCLK ENET_RCLK JTAG_TDO JTAG_CLK JTAG_TDI JTAG_TMS JTAG_RST SCSI_D[0] SCSI_D[1] SCSI_D[2] SCSI_D[3] SCSI_D[4] SCSI_D[5] SCSI_D[6] SCSI_D[7] SCSI_DP Name Name SCSI_SEL SCSI_BSY SCSI_REQ SCSI_ACK SCSI_MSG SCSI_CD SCSI_IO SCSI_ATN SCSI_RST SCSI_XTAL_OUT SCSI_XTAL_IN SCC_20_IN SCC_20_OUT SCC_CLK20 SB_D_IRQ SB_RD SB_D[0] Name SB_D[1] SB_D[2] SB_D[3] SB_D[4] SB_D[5] SB_D[6] SB_D[7] SB_D[8] SB_D[9] SB_D[10] SB_D[11] SB_D[12] SB_D[13] SB_D[14] SB_D[15] SB_ACK[2] SB_ACK[1] SB_BR SB_BG SB_LERR CHIP_SEL SB_SEL Name SB_AS SB_ACK[0] SB_SIZ[2] SB_SIZ[1] SB_SIZ[0] SB_CLK SB_PA_W SB_PA_X SB_P_Y SB_PA[4] SB_PA[3] SB_PA[2] SB_PA[1] SB_PA[0] SB_PA[5] SB_D[16] SB_D[17] SB_D[18] SB_D[19] SB_D[20] SB_D[21]
Master 32-bit SBus Master Controller
STP2000QFP
July 1997160-Lead PQFP Package Dimensions
STP2000QFP
Master 32-bit SBus Master Controller
ORDERING INFORMATION
Part Number STP2000QFP 160-Pin Plastic Quad Flat Package (PQFP)
Document Part Number: STP2000
Description

Master STP2000 Master Controller integrated SBus master device wi

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