SDRAM Unbuffered uSODIMM 144pin Unbuffered uSODIMM based 128Mb E-
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64MB Unbuffered uSODIMM
SDRAM Unbuffered uSODIMM
144pin Unbuffered uSODIMM based 128Mb E-die (x16) 64-bit
Revision May. 2003
Rev. May. 2003
64MB Unbuffered uSODIMM
Revision History
Revision (Nov., 2002) First release Revision (May, 2003) Delete CL=2 @133MHz.
Rev. May. 2003
64MB Unbuffered uSODIMM
144Pi Unbuffered uSODIMM based 128Mb E-die (x16)
Ordering Information
Part Number M463S0924ET1-C(L)7A Density 64MB Organization Component Composition 8Mx16(K4S281632E)
Interface LVTTL
Operating Frequencies
Speed @CL3 CL-tRCD-tRP 133MHz(7.5ns) 3-3-3
FEATURE
Burst mode operation Auto self refresh capability (4096 Cycles/64ms) LVTTL compatible inputs outputs Single 3.3V 0.3V power supply cycle with address programs Latency (Access from column address) Burst length Full page) Data scramble (Sequential Interleave) inputs sampled positive going edge system clock Serial presence detect with EEPROM Height (30mm) double sided component
Rev. May. 2003
64MB Unbuffered uSODIMM
CONFIGURATIONS (Front side/back side)
Front DQM0 DQM1 DQ10 DQ11 DQ12 DQ13 Back DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM4 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 Front DQ14 DQ15 Back DQ46 DQ47 Front DQ21 DQ22 DQ23 A10/AP DQM2 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 **SDA
Back DQ53 DQ54 DQ55 DQM6 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 **SCL
Voltage
CLK0 *CS1 DQ16 DQ17 DQ18 DQ19 DQ20 CKE0 *CKE1 *A12 *A13 *CLK1 DQ48 DQ49 DQ50 DQ51 DQ52
NAMES
Name DQ63 CLK0 CKE0 Select bank Data input/output Clock input Clock enable input Chip select input address storbe Column address strobe Function Address input (Multiplexed) DQM0 Name Write enable Power supply (3.3V) Ground Serial data Serial clock Dont connection Function
These pins used this module. These pins should system which does support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves right change products specifications without notice.
Rev. May. 2003
64MB Unbuffered uSODIMM
CONFIGURATION DESCRIPTION
Name System clock Chip select Input Function Active positive going edge sample inputs.
Disables enables device operation masking enabling inputs except CLK, Masks system clock freeze operation from next clock cycle. should enabled least cycle prior command. Disable input buffers power down standby. should enabled 1CLK+tSS prior valid command. Row/column addresses multiplexed same pins. address RA11, Column address Selects bank activated during address latch time. Selects bank read/write during column address latch time. Latches addresses positive going edge with low. Enables access precharge. Latches column addresses positive going edge with low. Enables column access. Enables write operation precharge. Latches data starting from CAS, active. Makes data output Hi-Z, tSHZ after clock masks output. Blocks data input when active. (Byte masking) Data inputs/outputs multiplexed same pins. Power ground input buffers core logic.
Clock enable
DQM0 VDD/VSS
Address Bank select address address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Rev. May. 2003
64MB Unbuffered uSODIMM
64MB, 8Mx64 Module (M463S0924ET1) (Populated bank SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
DQM0 LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM4 LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM2 LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDRAM SDRAM SDRAM SDRAM SDRAM Three 0.1uF Capacitors each SDRAM SDRAMs Every SDRAM
DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM UDQM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Serial
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 A11, CKE0
CLK0 CLK1 10pF
Note zero jumper isolate from SDRAM pins non-256Mbit designs.
Rev. May. 2003
64MB Unbuffered uSODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG Value -1.0 -1.0 +150
Unit
Note Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS CHARACTERISTICS
Recommended operating conditions (Voltage referenced 70°C) Parameter Supply voltage Input high voltage Input voltage Output high voltage Output voltage Input leakage current Symbol -0.3 VDDQ+0.3 Unit -2mA Note
Notes (max) 5.6V AC.The overshoot voltage duration 3ns. (min) -2.0V undershoot voltage duration 3ns. input VDDQ. Input leakage currents include Hi-Z output leakage bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD 3.3V, 23°C, 1MHz, VREF 1.4V Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT Unit
Parameter Input capacitance A11, BA1) Input capacitance (RAS, CAS, Input capacitance (CKE0) Input capacitance (CLK0) Input capacitance (CS0) Input capacitance (DQM0 DQM7) Data input/output capacitance (DQ0 DQ63)
Rev. May. 2003
64MB Unbuffered uSODIMM
CHARACTERISTICS
M463S0924ET1(64MB, 8Mx64 Module)
(Recommended operating condition unless otherwise noted, 70°C) Parameter Symbol Burst length tRC(min) VIL(max), 10ns VIL(max), VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable VIL(max), 10ns VIL(max), VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable Page burst 4Banks activated tCCD 2CLKs tRC(min) 0.2V Notes Measured with outputs open. Refresh period 64ms. Unless otherwise noted, input swing level CMOS(VIH/VIL=VDDQ/VSSQ) Version Test Condition Unit Note
Operating current (One bank active) Precharge standby current power-down mode
ICC1 ICC2P ICC2PS ICC2N
Precharge standby current power-down mode ICC2NS Active standby current power-down mode ICC3P ICC3PS ICC3N ICC3NS
Active standby current power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
ICC5 ICC6
Rev. May. 2003
64MB Unbuffered uSODIMM
OPERATING TEST CONDITIONS (VDD 3.3V 0.3V, 70°C)
Parameter input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition Value 2.4/0.4 tr/tf Fig.
Unit
3.3V
1.4V
1200 Output 50pF (DC) 2.4V, -2mA (DC) 0.4V, Output
50pF
(Fig. output load circuit
(Fig. output load circuit
OPERATING PARAMETER
operating conditions unless otherwise noted) Parameter active active delay delay precharge time active time cycle time Last data precharge Last data Active delay Last data col. address delay Last data burst stop Col. address col. address delay Number valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) latency=3 latency=2 Version Unit Note
Notes minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. parts allow every cycle column address change. case precharge interrupt, auto precharge read burst stop.
Rev. May. 2003
64MB Unbuffered uSODIMM
CHARACTERISTICS operating conditions unless otherwise noted) REFER INDIVIDUAL COMPONENET, WHOLE MODULE.
Parameter cycle time valid output delay Output data hold time latency=3 latency=2 latency=3 latency=2 latency=3 latency=2 tSLZ tSHZ tSAC Symbol 1000 Unit
Note
high pulse width pulse width Input setup time Input hold time output Low-Z output Hi-Z latency=3 latency=2
Notes Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
Rev. May. 2003
64MB Unbuffered uSODIMM
SIMPLIFIED TRUTH TABLE
Command Register Mode register Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
BA0,1 A10/AP Note
code
address
Column address Column address
Bank active addr. Read column address Write column address Burst stop Precharge Bank selection banks Clock suspend active power down Entry Exit Entry Precharge power down mode Exit operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
Notes Code Operand code Program keys. MRS) issued only banks precharge state. command issued after clock cycles MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. both "Low" read, write, active precharge, bank selected. "High" "Low" read, write, active precharge, bank selected. "Low" "High" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in very (Write latency makes Hi-Z state data-out cycles after. (Read latency
Rev. May. 2003
64MB Unbuffered uSODIMM
PACKAGE DIMENSIONS
Units Millimeters
42.00 38.00 1.00 1.80 1.00 2.50
3.80
5.00
35.50
7.00
0.875
15.00
3.50
30.00
0.80 0.08
DETAIL
1.00 R1.00 0.10
37.00
0.50 4.00 0.10
3.50
0.37 0.03 R1.00
Detail
1.80
used device 8Mx16 SDRAM, TSOPII SDRAM Part K4S281632E
Rev. May. 2003
0.25
2.00
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