Order this document MC100EP221/D Low-Voltage 1:20 Differential EC

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Low-Voltage 1:20 Differential ECL/PECL Clock Driver
MC100EP221 skew 1-to-20 differential driver, designed with clock distribution mind. accepts clock sources into input multiplexer. input signals either differential single-ended output used. selected signal fanned identical differential outputs.
MC100EP221
270ps max. Part-to-Part Skew 50ps max. Output-to-Output Skew Differential Design Output Voltage Temperature Compensated Outputs Supports 3.3V 2.5V, PECL Operation Supports HSTL PECL Clock Systems
LOW-VOLTAGE 1:20 DIFFERENTIAL ECL/PECL CLOCK DRIVER
EP221 specifically designed, modeled produced with skew goal. Optimal design layout serve minimize gate- to-gate skew within device, empirical modeling used determine process control limits that ensure consistent distributions from lot. result dependable, guaranteed skew device. SUFFIX ensure that tight skew specification necessary that 52-LEAD LQFP PACKAGE both sides differential output terminated into even only EXPOSED CASE 1336 side being used. most applications, differential pairs will used therefore terminated. case where fewer than pairs used, necessary terminate least output pairs same package side pair(s) being used that side, order maintain minimum skew. Failure this will result small degradations propagation delay order 10-20ps) output(s) being used which, while being catastrophic most designs, will mean loss skew margin. MC100EP221, with most other devices, operated from positive supply PECL mode. This allows EP221 used high performance clock distribution +3.3V +2.5V systems. Designers take advantage EP221's performance distribute skew clocks across backplane. PECL environment, series Thevenin line terminations typically used they require additional power supplies.
08/01
Motorola, Inc. 2001
MC100EP221
Pinout: 52-Lead LQFP (Top View)
VCCO
VCCO
VCCO
MC100EP211
CLKSEL
CLK0
CLK0
CLK1
VCCO
CLK1
FUNCTION
CLK_SEL Active Input CLK0, CLK0 CLK1, CLK1
LOGIC SYMBOL
CLK0
CLK0
Q1:18 Q1:18
CLK1
CLK1
CLK_SEL
TIMING SOLUTIONS
MC100EP221
Table CONFIGURATION
CLK0, CLK0 CLK1, CLK1 CLK_SEL Q[0-19], Q[0-19] VEEa VCC, VCCO Input Input Input Output Supply Supply Output Type ECL/LVPECL ECL/LVPECL HSTL LVPECL LVPECL Function Differential reference clock signal input Alternative differential reference clock signal input Output frequency divider select Differential clock outputs Negative power supply Positive power supply. VCCO pins must connected positive power supply correct operation bias output single ended input operation
mode (negative power supply mode), either -3.3V -2.5V connected (0V). PECL mode (positive power supply mode), connected (0V) either +3.3V +2.5V. both modes, input output levels referrenced most positive supply (VCC).
Table ABSOLUTE MAXIMUM RATINGSa
Symbol VOUT IOUT Supply Voltage Input Voltage Output Voltage Input Current Output Current Storage temperature Characteristics -0.3 -0.3 -0.3 VCC+0.3 VCC+0.3 Unit Condition
Absolute maximum continuos ratings those maximum values beyond which damage device occur. Exposure these conditions conditions beyond those indicated adversely affect device reliability. Functional operation absolute-maximum-rated conditions implied.
Table GENERAL SPECIFICATIONS
Symbol Thermal resistance junction ambient Characteristics Output termination voltage Protection (Machine model) Protection (Human body model) Protection (Charged device model) Latch-up immunity 1500 application informationb Unit Inputs Condition
Thermal resistance junction case application information Output termination voltage VCC=2.5V operation supported power consumption device will increase. Proper thermal management critical reliable system operation. This especially true high-fanout high drive capability products. Thermal package information exposed land pattern design recommendations available applications section this datasheet. addition, means calculating power consumption, corresponding temperature relationsship long-term reliability addressed Motorola application note AN1545. Thermal modeling recommended MC100EP221.
TIMING SOLUTIONS
MC100EP221
Table PECL HSTL Characteristics (VCCO 2.375V 3.8V, GND)
Symbol Characteristics -40°C 25°C 85°C Unit Condition
Clock input pair CLK0, CLK0, CLK1, CLK1a (LVPECL differential signals) Differential input voltageb VCC=3.3V VCC=2.5V Differential cross point voltagec CLK0 CLK1 0.10 0.15 VCC-0.4 VCC-1.0 0.10 0.15 VCC-0.4 VCC-1.0 0.10 0.15 VCC-0.4 VCC-1.0
VCMR
Clock input pair CLK1, CLK1d (HSTL differential signals) VDIF Differential input voltagee VCC=3.3V VCC=2.5V Differential cross point voltagef Input high voltage Input voltage 0.68 VX+0.2 VX-0.5 VCC-1.165 VCC-1.810 VX+0.5 VX-0.2 VCC-0.880 VCC-1.480 0.68 VX+0.2 VX-0.5 VCC-1.165 VCC-1.810 VX+0.5 VX-0.2 VCC-0.880 VCC-1.480 0.68 VX+0.2 VX-0.5 VCC-1.165 VCC-1.810 VX+0.5 VX-0.2 VCC-0.880 VCC-1.480
inputs (LVPECL single ended signals) Input high voltage Input voltage Input Current IOH= -30mAg IOL= -5mAg pins
LVPECL clock outputs (Q0-19, Q0-19) Output High Voltage Output Voltage VCC-1.20 VCC-1.90 VCC-0.82 VCC-1.40 VCC-1.15 VCC-1.90 VCC-0.82 VCC-1.40 VCC-1.15 VCC-1.9 VCC-0.82 VCC-1.40
Supply current Max. Supply Current Max. Supply Currenth
Output reference voltagei VCC=3.3V VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.24 VCC=2.5V VCC-1.35 VCC-1.24 VCC-1.35 VCC-1.22 VCC-1.35 VCC-1.22 input pairs CLK0, CLK1 compatible differential signaling standards. CLK0 compatible LVPECL signals CLK1 meets both HSTL LVPECL differential signal specifications. difference between CLK0 CLK1 differential input threshold voltage (VCMR). minimum differential input voltage swing required maintain device functionality. VCMR (DC) crosspoint differential input signal. Functional operation obtained when crosspoint within VCMR (DC) range input swing lies within (DC) specification. Clock inputs driven differential HSTL compatible signals. Only applicable CLK1, CLK1. VDIF (DC) minimum differential HSTL input voltage swing required device functionality. Only applicable CLK1, CLK1. VCMR (DC) crosspoint differential input signal. Functional operation obtained when crosspoint within VCMR (DC) range input swing lies within (DC) specification. Equivalent output termination VTT. includes current through output resistors (all outputs terminated VTT). output used bias complementary input when device used with single ended clock signals. sink max. current.
TIMING SOLUTIONS
MC100EP221
Table Characteristics (VCC VCCO GND, -3.8V -2.375V)
Symbol Characteristics -40°C 25°C 85°C Unit Condition
Clock input pair CLK0, CLK0, CLK1, CLK1a differential signals Differential input voltageb 0.10 0.10 VEE=-3.3V 0.15 0.15 VEE=-2.5V VCMR Differential cross point voltage -0.4 VEE+1.0 CLK0 VEE+1.0 -1.0 VEE+0.1 CLK1 VEE+0.1 inputs single ended signals Input high voltage Input voltage Input Current -1.165 -1.810 -0.880 -1.480 -1.165 -1.810
0.10 0.15 -0.4 -1.0 VEE+1.0 VEE+0.1 -1.165 -1.810 -0.4 -1.0
-0.880 -1.480
-0.880 -1.480
IOH= IOL= Pins
LVPECL clock outputs (Q0-19, Q0-19) Output High Voltage Output Voltage -1.20 -1.90 -0.82 -1.40 -1.20 -1.90 -0.82 -1.40 -1.20 -1.90 -0.82 -1.40
Supply current Max. Supply Current Max. Supply Currente
Output reference voltagef -1.35 -1.24 -1.35 -1.24 -1.35 -1.24 VEE=-3.3V -1.35 -1.24 -1.35 -1.22 -1.35 -1.22 VEE=-2.5V input pairs CLK0, CLK1 compatible differential signaling standards such ECL. difference between CLK0 CLK1 differential input threshold voltage (VCMR). minimum differential input voltage swing required maintain device functionality. VCMR (DC) crosspoint differential input signal. Functional operation obtained when crosspoint within VCMR (DC) range input swing lies within (DC) specification. Equivalent output termination VTT. includes current through output resistors (all outputs terminated VTT). output used bias complementary input when device used with single ended clock signals. sink max. current.
TIMING SOLUTIONS
MC100EP221
Table PECL/ECL/HSTL Characteristicsa (VCC VCCO 2.375V 3.8V, GND) (VEE -3.8V -2.375V, VCCO GND)
Symbol Characteristics -40°C 25°C 85°C Unit Condition
Clock input pair CLK0, CLK0, CLK1, CLK1b PECL differential signals Differential input voltagec (peak-to-peak) VCMR Differential cross point voltaged CLK0 CLK1 Input Frequency (PECL) VCC-0.4 VCC-1.3
fCLK VCMR
VCC-0.4 VCC-1.3
VCC-0.4 VCC-1.3
Clock input pair CLK0, CLK0, CLK1, CLK1 differential signals Differential input voltage (peak-to-peak)
fCLK
Differential cross point voltage CLK0 VEE+1.0 CLK1 VEE+0.3 Input Frequency (ECL)
-0.4 -1.3
VEE+1.0 VEE+0.3
-0.4 -1.3
VEE+1.0 VEE+0.3
-0.4 -1.3
Clock input pair CLK1, CLK1 HSTL differential signals VDIF Differential input voltagee (peak-to-peak) CLK1 fCLK Differential cross point voltagef CLK1 Input Frequency (HSTL) 0.68
0.68
0.68
PECL/ECL clock outputs (Q0-19, Q0-19) Propagation Delay CLK0 CLK1 Differential output voltage (peak-to-peak)fO Output-to-output skew (within device) Output-to-output skew (part-to-part) Output cycle-to-cycle jitter (RMS) Output duty cycle Output Rise/Fall Time 49.5 50.0 50.5 49.5 50.0 50.5 49.5 50.0 50.5 DCfref= Diff. Diff. Diff. Diff.
VO(P-P)
tsk(O) tsk(PP) tJIT(CC)
characteristics apply parallel output termination VTT. input pairs CLK0, CLK1 compatible differential signaling standards such ECL. difference between CLK0 CLK1 differential input threshold voltage (VCMR). (AC) minimum differential input voltage swing required maintain characteristics including device-to-device skew. VCMR (AC) crosspoint differential input signal. operation obtained when crosspoint within VCMR range input swing lies within (AC) specification. Violation VCMR (AC) (AC) impacts device propagation delay part-to-part skew. VDIF (AC) minimum differential HSTL input voltage swing required maintain characteristics. Only applicable CLK1. (AC) crosspoint differential HSTL input signal. operation obtained when crosspoint within (AC) range input swing lies within VDIF (AC) specification. Violation (AC) VDIF (AC) impacts device propagation delay part-to-part skew.
TIMING SOLUTIONS
MC100EP221
Differential Pulse Generator
MC100EP221
Figure MC100EP221 test reference
CLKN CLKN (CLKN
VPP=0.8V
VCMR=VCC-1.3V
Figure MC100EP221 reference measurement waveform
TIMING SOLUTIONS
MC100EP221
APPLICATIONS INFORMATION
Using thermally enhanced package MC100EP221 MC100EP221 uses thermally enhanced exposed (EP) lead LQFP package. package molded that leadframe exposed surface package bottom side. exposed metal will provide thermal impedance that supports power consumption MC100EP221 high-speed bipolar integrated circuit eases power management task system design. thermal land pattern printed circuit board thermal vias recommended order take advantage enhanced thermal capabilities MC100EP221. Direct soldering exposed thermal land will provide efficient thermal path. multilayer board designs, thermal vias thermally connect exposed internal copper planes. Number vias, spacing, diameters land pattern design depend application amount heat removed from package. nine thermal array, arranged array using pitch center thermal land absolute minimum requirement MC100EP221 applications multi-layer boards. recommended thermal land design comprises "Recommended thermal land pattern", providing efficient heat removal path.
units
recommended thermal array. Because large solder mask opening result poor release, opening should subdivided shown Figure nominal package standoff stencil thickness mils should considered.
units
Thermal array (5x5), pitch, diameter
Figure Recommended solder mask openings thermal system analysis junction temperature calculation thermal resistance parameters package provided. thermal system analysis junction temperature calculation thermal resistance parameters package provided: Table Thermal Resistancea
ConvectionLFPM Natural RTHJAb °C/W 57.1 50.0 46.9 43.4 38.6 RTHJAc °C/W 24.9 21.3 20.0 18.7 16.9 15.8 RTHJCd °C/W RTHJBe °C/W
Thermal array (5x5), pitch, diameter
Exposed land pattern
Figure Recommended thermal land pattern diameter should approx. with copper barrel plating. Solder wicking inside resulting voids during solder process must avoided. copper plating does plug vias, stencil print solder paste onto printed circuit pad. This will supply enough solder paste fill those vias starve solder joints. attachment process exposed package equivalent standard surface mount packages. Figure "Recommended solder mask openings" shows recommend solder mask opening with respect
Thermal data pattern with thermal array 2S2P boards (based empirical results) Junction ambient, single layer test board, JESD51-6 Junction ambient, four conductor layer test board (2S2P), JES51-6 Junction case, MIL-SPEC 883E, method 1012.1 Junction board, four conductor layer test board (2S2P) JESD 51-8 recommended that users employ thermal modeling analysis assist applying general recommendations their particular application. exposed MC100EP221 package does have electrical impedance path substrate integrated circuit terminals. thermal land should connected through connection internal board layers.
Exposed land pattern
TIMING SOLUTIONS
MC100EP221
OUTLINE DIMENSIONS
SUFFIX PLASTIC LQFP PACKAGE CASE 1336-01 ISSUE
0.20
TIPS
0.20
X=A,
VIEW
VIEW
BASE METAL
PLATING
E1/2
D1/2
ROTATED CLOCKWISE NOTES: DIMENSIONS MILLIMETERS. INTERPRET DIMENSIONS TOLERANCES ASME Y14.5M, 1994. DATUMS DETERMINED DATUM PLANE DIMENSIONS DETERMINED SEATING PLANE DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE LEAD WIDTH EXCEED MAXIMUM DIMENSION MORE THAN 0.08 DAMBAR CANNOT LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSION ADJACENT LEAD PROTRUSION 0.07 DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25mm SIDE. MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. EXACT SHAPE EACH CORNER OPTIONAL. THESE DIMENSIONS APPLY FLAT SECTION LEAD BETWEEN 0.25 FROM LEAD TIP. MILLIMETERS 1.70 0.05 0.20 1.30 1.50 0.271 0.334 0.27 0.33 0.123 0.136 0.122 0.132 12.00 10.00 0.65 12.00 10.00 0.45 0.75 1.00 0.08 0.08 0.20 0.20 6.50 7.50 6.50 7.50
SECTION AB-AB
0.08
SEATING PLANE
0.08
VIEW
VIEW
EXPOSED
VIEW
TIMING SOLUTIONS
MC100EP221
NOTES
TIMING SOLUTIONS
MC100EP221
NOTES
TIMING SOLUTIONS
MC100EP221
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. 2001.
reach EUROPE Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
TIMING SOLUTIONS MC100EP221/D

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