QuickScan9-Bit Universal JTAG Access Port with Output Enable QS3J

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QuickScan9-Bit Universal JTAG Access Port with Output Enable QS3J

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QS3J309
QuickScan9-Bit Universal JTAG Access Port with Output Enable
QS3J309
FEATURES/BENEFITS
IEEE 1149.1a-1993 (JTAG) compliant JTAG access data, control address lines Capture observe embedded node QuickSwitch® fast switch technology TTL-compatible Direct connection when switches Balanced drive JTAG Mode power QCMOStechnology Zero added signal skew non-JTAG mode Zero propagation delay non-JTAG mode Includes CLAMP HIGH-Z instructions Bidirectional data paths non-scan mode Available 28-pin QSOP
QS3J309 JTAG QuickScan device designed provide JTAG access data, address, control lines internal signals), while being transparent system during normal (non-JTAG) operation. This achieved combining "like-a-wire" characteristics QSI's QuickSwitch devices with JTAG boundary scan access port. QS3J309 provide scan coverage system functional blocks without cost overhead performance penalties individual scan components. When boundary scan mode, QS3J309 QuickSwitch pass gates turned allowing transparent, bidirectional data propagation. When boundary scan mode, scan data captured from loaded onto data bus. serial access port also used monitor data while device remains electrically transparent. This feature useful debugging monitoring. QS3J309 IEEE1149.1a-1993 compliant, with complete instruction register functionality, bypass 32-bit device register.
Figure Functional Block Diagram
TRST
Test Access Port (TAP) Switch Control Logic Instruction Register Bypass Register Device Register
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
QuickSwitch
QuickSwitch
Quick- Quick- QuickSwitch Switch Switch
QuickSwitch
QuickSwitch
Quick- QuickSwitch Switch
Input Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
Scan Cell
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QUALITY SEMICONDUCTOR, INC.
QS3J309 Figure Scan Cell
Next Cell Output Enable
Control Cell
HIGH-Z Logic
MODE Shift-DR Clock-DR Update-DR Data
Cell System
DOUT
Input Cell
From Last Cell
Figure Instruction Register Cell
Next Instruction Cell
Parallel Data Input From Previous Instruction Cell
Shift-IR Clock-IR Update-IR
Instruction
QUALITY SEMICONDUCTOR, INC.
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QS3J309 Figure Bypass Register Figure Device Register
Code From Last Cell Shift-DR Clock-DR Next Cell
Shift-DR Clock-DR
Figure Scan Chain Definition
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL INPUT
CONTROL
CONTROL
CONTROL
CONTROL
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QUALITY SEMICONDUCTOR, INC.
QS3J309 Figure Configuration
(All Pins View) QSOP TRST
Table Function Table
(Non-scan Mode: Controller RESET mode) Inputs Output
Table Instruction Register Definitions
Instruction Code 00000000 others 00000001 00000010 00000100 00000101 00000110 Instruction EXTEST BYPASS SAMPLE/PRELOAD IDCODE HIGH-Z CLAMP BOUNDARY READ Switch State
Table Definitions
Name A8-A0 B8-B0 TRST Description Normal function data inputs outputs. Normal function data inputs outputs. Asynchronously resets controller. Normal function enable input. Table Function Table normal function. Test Clock. four terminals required IEEE Standard 1149.1a-1993. Test operations device synchronous TCK. Test Mode Select. four terminals required IEEE Standard 1149.1a-1993. signal received decoded controller control test operations. Test Data Input. four terminals required IEEE Standard 1149.1a-1993. Serial test instructions data received test logic TDI. Test Data Output. four terminals required IEEE Standard 1149.1a-1993. serial output test instructions data from test logic.
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QS3J309 Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Switch Voltage -0.5V 0.5V Input Voltage -0.5V +7.0V Input Voltage (for pulse width -3.0V Input Diode Current with Output Current Max. Sink Current/Pin Maximum Power Dissipation. watts TSTG Storage Temperature -50° +125°C
Note: Absolute Maximum Ratings those conditions beyond which damage device occur. Exposure these conditions beyond those indicated adversely affect device reliability. Functional operation under absolute maximum rating conditions implied.
Table Electrical Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage (Scan mode) Output Voltage (Scan mode) Input Leakage Current Off-State Current (Hi-Z) Switch Resistance(2) Switch Resistance(2) Switch Resistance(2) Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min, 4.5V, -100 Min, 4.5V, Vcc, Min., 0.0V Min., 2.4V Min., =4.0V Typ(1) Unit
Notes: Typical values indicate 5.0V 25°C. Measured voltage drop between indicated current through switch. resistance determined lower voltages (A,B) pins.
Table Capacitance
25°C, MHz, VOUT Pins Control/JTAG Pins QuickSwitch Channels (OFF) Unit
Figure Typical Switch Resistance Characteristics 4.75
(ohms)
Note: Capacitance characterized tested.
(Volts)
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QUALITY SEMICONDUCTOR, INC.
QS3J309 Table Power Supply Characteristics
Symbol ICCQ Parameter Quiescent Power Supply Current Test Conditions Max., TRST Max., TRST GND, Max., TRST QCCD
Notes: conditions shown Min. Max., appropriate values specified under specifications. driven input (VIN 3.4V, control inputs only). pins contribute Icc. This current applies control inputs only represents current required switch internal capacitance specified frequency. inputs generate significant currents they transition. This parameter guaranteed design, tested. TRST, TMS, have resistor pull-up Vcc.
0.25
Unit
Power Supply Current Input HIGH(2) Dynamic Power Supply Current MHz(3)
Max., 3.4V, Max., Pins Open, Controls Toggling Duty Cycle
Table Switching Characteristics Non-scan (Normal) Operation
Industrial: -40°C 85°C, 5.0V CLOAD RLOAD unless otherwise noted. Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Description Data Propagation Switch Delay(2,3)
QS3J309 0.25
Unit
Switch Turn-on Delay(1) Switch Switch Turn-off Delay(1,2) Switch HIGH-Z Charge Injection, Typical(4,5)
Notes: Test Circuit Waveforms. Minimums guaranteed tested. This parameter guaranteed design tested. switch contributes propagation delay other than time constant delay switch resistance load capacitance. propagation delay specified assumes standard external load. Since this time constant much smaller than rise/fall times typical driving signals, adds negligible propagation circuit driving side switch interaction with load driven side. Measured switch turn off, load parallel with scope probe, 0.0V. Characterized parameter 100% tested.
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QS3J309 Table Switching Characteristics Scan Mode
Industrial: -40°C 85°C, 5.0V CLOAD RLOAD unless otherwise noted. Industrial Symbol tPLH tPHL tPLZ tPHZ tPZL tPZH tPLH tPHL tPLZ tPHZ tPZL tPZH Description(1) Data Propagation Delay Disable Time(2) Enable Time Data Propagation Delay Data Disable Delay(2) Data Enable Delay Data Setup Time, Hold Time, Setup Time, Hold Time, Setup Time, Data Hold Time, Data Pulse Width, HIGH fMAX Maximum Frequency Power-Up Power-Down Time Update-DR Update-DR Update-IR Test Reset Update-DR Update-IR State Unit
Note: propagation delays measured from falling edge TCK. This parameter guaranteed design tested.
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QUALITY SEMICONDUCTOR, INC.
QS3J309 WAVEFORMS Figure Propagation Delay Non-scan Operation
3.0V CONTROL INPUT 1.5V
Figure Pulse Width
LOW-HIGH-LOW PULSE 1.5V
HIGH-LOW-HIGH PULSE 1.5V
tPLH tPZH
OUTPUT SAME PHASE
tPHL tPZL
1.5V
tPHL tPZL
OUTPUT OPPOSITE PHASE
tPLH tPZH
Figure Setup Time, Hold Time
TMS, TDI, Data
1.5V
Figure Propagation Delay Scan Test Operation
tPHL
TDO, Data
1.5V
tPLH
TDO, Data
1.5V
Figure Tri-state Output Low, Enable Disable Times
tPZL
TDO, Data
tPLZ
0.3V
Figure Tri-state Output High, Enable Disable Times
tPZH
TDO, Data
tPHZ
0.3V
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QS3J309 DESCRIPTION BOUNDARY-SCAN ARCHITECTURE
Serial test information conveyed means test access port (TAP) that conforms IEEE Standard 1149.1a-1993. Test instructions, data, control signals passed along this 4-wire serial test bus. test architecture consists test access port (TAP), serial output circuit, instruction register, bypass register, boundary-scan register, optional identification register. state machine that responds test clock (TCK) test mode select (TMS) inputs shift data from test data input (TDI) through either instruction register selected data register test data output (TDO). output circuit multiplexes serial stream from instruction selected data register TDO. instruction register holds current test command. boundary-scan register refers IC's inputs outputs provides test circuitry required testing internal functionality device well wiring interconnects between board boundary scan cell refers individual input output). bypass register provides single scan path through when boundary-scan testing being performed. optional identification register provides information about (i.e., manufacturer, device type version codes). Although there reset capability TAP, hardware reset performed optional test reset (TRST). Figure shows boundary-scan architecture.
Figure Boundary-Scan Architecture
SYSTEM DATA INPUT
APPLICATION LOGIC
SYSTEM DATA OUTPUT
IDENTIFICATION
BYPASS
INSTRUCTION
OUTPUT
TRST
(Optional)
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QS3J309
state machine controls boundary-scan activity five modes operation: Reset, Run/ Test, Idle, Data scan, Instruction scan modes. diagram shown Figure diagram illustrates polarity signal (with TCK) dictates control direction through operation modes. instruction register loaded during instruction scan mode, data registers (i.e., pins) loaded/ retrieved during data scan mode. guaranteed reset performed holding HIGH five clock cycles. There three required instructions indicated boundary-scan standard. These EXTEST, SAMPLE/PRELOAD, BYPASS. EXTEST instruction will drive device external according data contained each boundary scan cell. This instruction commonly used stimulate signal nets during board interconnection testing. SAMPLE/PRELOAD instruction used read data from device boundary register. This instruction also used load data into boundary register prior selection another test instruction. BYPASS instruction automatically selects bypass register provide minimum-length serial scan path. This instruction used when device being tested.
Figure Controller State Diagram
TEST-LOGIC-RESET RUN-TEST/IDLE VALUE DURING RISING EDGE LOCATED NEXT EACH TRANSITION.
SEL-DR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR
SEL-IR-SCAN CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR EXIT2-IR UPDATE-IR
function block diagram illustrates IEEE Standard 1149.1a-1993 4-wire test boundaryscan architecture relationship between test bus, test registers, controller. QS3J309 QuickScan device provides JTAG access databus, while being transparent system
during normal (non-scan) operation. This achieved combining "like-a-wire" characteristics QSI's QuickSwitch® devices with JTAG boundary-scan access port. This device consists 8-bit instruction register, 32-bit register, 1-bit bypass register, boundary-scan registers.
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QS3J309
TEST ACCESS PORT (TAP) DESCRIPTION Test Access Port (TAP) consists four pins dedicated solely operation test logic. four pins include (Test Mode Select), (Test Data In), (Test Data Out), (Test Clock). These pins required IEEE1149.1a. TCK: (TEST CLOCK) This input provides test clock test circuits. Data (TDI TMS) captured rising edge outputs change falling edge. TMS: (TEST MODE SELECT) This input controls test logic operation modes directing device through controller states. This input pullup resistor which guarantees that undriven input controller into Test Logic Reset state. requirement that unforced input produce logic high ensures that normal operation design continue without interference from test logic. TDI: (TEST DATA This input serial data input instructions data test logic. Test data will arrive without inversion after appropriate number clock cycles determined length register currently connected between TDO. This input pull-up resistor implement logic high undriven input. requirement that unforced input produce logic high assist determination manufacturing defects test scan chain interconnect. repeating field indicate where break scan chain interconnect occurred. TDO: (TEST DATA OUT) This output provides serial data output test instructions data from test logic. Changes logic state drive activity this output occur upon falling edge TCK. This avoid race condition when connected next chip scan chain which sampled rising edge. This output shall remain inactive except when scanning data progress. This permit ability multiplex scan chains board without causing signal contention between multiple outputs connected together form parallel scan chains. TRST: TRST (RESET) This resets controller asynchronously clock dependent upon other signal. (Bus Enable) This overriding enable signal that when HIGH will disable switches non-scan mode.
STATE main feature controller state machine which defined IEEE 1149.1a JTAG specification. These states change response value (upon rising edge TCK), upon power-up. given state, actions test logic occur falling rising edge following rising edge which caused controller enter state initially. NOTE: happen that actions occur state happen same rising edge that causes controller enter next state. TEST LOGIC RESET: test logic disabled during this state that normal operation system logic proceed uninhibited. Following entry into Test Logic Reset state, IDCODE instruction latched onto instruction register output falling edge TCK. features state diagram realized this state. First noted that independent what state controller currently QS3J309 will enter Test Logic Reset state after, most, five cycles with input high. Secondly, temporary glitch should occur input during rising edge TCK, Controller will enter Run-Test/Idle state then return Test Logic Reset state Select-DR state Select-IR state provided that returns logic high value rising edge clocks following glitch. QS3J309 controller will also forced into Test Logic Reset state upon power-up. RUN-TEST/IDLE: controller must pass through Run-Test/Idle state before executing test operations. Once entered, controller will remain this state long held low. When high rising edge applied TCK, controller moves Select-DR-Scan state. instruction does change while controller this state. SELECT-DR SCAN: This temporary state which test data registers retain their previous values.
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QS3J309
CAPTURE-DR: this controller state, data parallel loaded into data register selected current instruction; otherwise, retains previous values. SHIFT-DR: this state test data register selected between current instruction will shift stage each rising edge TCK. active during this state. Test data registers selected current instruction maintain their previous values. PAUSE-DR: This temporary state which data registers retain their previous values. This state intended temporarily halt shifting test data into data register selected while retaining ability keep running; free-running clock. EXIT1-DR: This temporary state which test data registers retain their previous values. EXIT2-DR: This temporary state which test data registers retain their previous values. UPDATE-DR: parallel output register selected test data register updated falling edge this state, provided test data register such parallel output register. intent parallel output register provide ability apply contents test data. SELECT-IR SCAN: This temporary state which instruction register retains previous value. CAPTURE-IR: this controller state data parallel loaded into instruction register. only restriction what data that least significant must logic high, second least significant must logic low, These opposite state bits used check correct operation scan chain board forcing toggle when instructions shifted. SHIFT-IR: this state instruction register selected between will shift stage each rising edge TCK. active during this state. EXIT1-IR: This temporary state which instruction registers retains previous values. PAUSE-IR: This temporary state which instruction register retains previous value. This state intended temporarily halt shifting test data into instruction register while retaining ability keep running. EXIT2-IR: This temporary state which instruction register retains previous value. UPDATE-IR: current instruction updated falling edge following entry into Update-IR state.
FEATURES CONTROLLER
controller will initialized operation system such system reset. controller will initialized into Test Logic Reset state upon power-up grounding TRST pin. This requirement intended avoid signal contention upon power-up disabling test logic which allows system logic operate normally hence controlled avoid contention. (The controller will return Test Logic Reset state after, most, five clock cycles with high; time required enact that operation sufficient avoid contention). Note that controller been defined such that sixteen states have ability maintain their state provided that remains same value when entering state: Test Logic Reset hold test logic during normal system operation, Test/Idle undertake multicycle self tests, Shift-DR Shift-IR maintain data shifting process extended period, Pause-DR Pause-IR halt shifting process while some other activity performed such retrieving test data from additional memory. This feature available any/all states where multiple clock cycles required achieve desired outcome where activity halted still provide ability make free-running clock.
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QS3J309 REGISTER OVERVIEW
With exception Bypass register, test register thought serial shift register with parallel latch each bit. bypass register only contains single shift register. detailed above, there three main instructions controlling these registers: Capture: causes shift register parallel loaded from specific source. Shift: causes shift register contents shift from TDO. Update: causes shift register data latch into parallel register falling edge TCK. incorporated into this QuickScan device. following descriptions, each instruction will identify test data register connected between during Shift-DR state, restrictions binary codes used implement instruction, what test data registers used undertaking actions instruction. EXTEST. This instruction allows circuitry external component package, typically board interconnect, tested. Boundary Scan register cells QuickSwitch pins used apply test capture stimuli. When this instruction selected, states signals system input pins will loaded into Boundary Scan register upon rising edge Capture-DR state contents Boundary Scan register will solely define state system outputs upon falling edge Update-DR state. 00000000 instruction binary code invokes EXTEST instruction. During this instruction Boundary Scan register connected between Shift-DR state. Additional binary codes this instruction permitted. EXTEST instruction shall select only boundary-scan register connected serial access between Shift-DR controller state (i.e., other test data register connected series with boundary-scan register). SAMPLE/PRELOAD. This instruction allows "snapshot" normal operation component taken examined. also allows data values loaded onto latched parallel outputs Boundary Scan shift register prior selection another boundary scan test instruction. During this instruction Boundary Scan register connected between Shift-DR state. When this instruction selected, states signals system pins will loaded into Boundary Scan register upon rising edge Capture-DR state contents Boundary Scan register will loaded into parallel output register included with Boundary Scan register bits upon falling edge Update-DR state. Note that interfacing these actions through Exit1-DR state, current state system pins captured into Boundary Scan register stored into parallel output registers later application back onto those same pins.
INSTRUCTION REGISTER
Instruction register permits 8-bit instructions serially loaded which select particular test data register and/or specific test function. Each instruction will identify particular test data register connected between when Shift-DR state along with defining particular test actions occur that test data register and/or others. order scan through instruction register must least-to-most; that least significant closest loaded instruction. During Shift-IR state instruction shifts between upon each rising edge appears without inversion TDO. During Capture-IR, Instruction registers LSB's "01". value "01" least significant locations used check connectivity scan chain forcing toggle each instruction during scan instruction registers. technique only assists determining correct connectivity scan chain about board, also assists pinpointing location break scan chain. During Update-IR, value data that been shifted into Instruction register loaded into parallel latches. this time, current instruction updated relevant mode changes initiated.
INSTRUCTION DEFINITIONS
instructions required IEEE1149.1a include BYPASS, EXTEST SAMPLE/PRELOAD instructions. additional IDCODE, CLAMP, HIGH-Z, BOUNDARY READ also been
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QS3J309
When SAMPLE/PRELOAD instruction selected, test logic shall have impact upon system logic performing system function. binary code device specific. BYPASS. This instruction allows rapid movement test data from other components board that required perform test operations selecting Bypass register, single-bit shiftregister stage, between ShiftDR state provide minimum-length serial scan path. "all others" opcode, along with requirement that undriven input produce logic high value, loads BYPASS instruction scan chain broken. such case instructions following break scan chain will loaded with BYPASS instruction hence have impact upon system's normal functional operation. During Capture-DR, bypass register captures logic IDCODE. IDCODE instruction instructs device output internal code from device Identification register. This code locked into device Identification register rising edge following entry into capture-DR state. device Identification register contains encoded part number, well Quality Semiconductor's manufacturer identity defined JEDEC. full code QS3J309 listed below. Note that fixed "1". This allows differentiation from Bypass register output that would begin with logic Each defined instructions Table fully indicate which data registers operate interact with system logic while instruction current. Test data registers that selected current instruction interfere with system logic operation test data registers currently selected. HIGH-Z. This instruction places cells (A8-A0 B8-B0) high-impedance state selects bypass register connected serial access between Shift-DR state. When leaving HIGH-Z instruction selecting EXTEST instruction example data held boundary scan register prior selection HIGH-Z instruction will applied device output pins. CLAMP. This instruction allows state signals driven from component pins determined from boundary scan register while bypass register selected serial path between TDO. signals driven from device pins will change while CLAMP instruction selected. BOUNDARY READ. boundary scan register selected scan path. value boundary scan register remains unchanged during Capture-DR. When boundary read instruction input device, contents boundary register shifted out. This instruction differs from EXTEST SAMPLE instruction that capture operation that normally occurs Capture-DR state replaced with data register hold operation.
BOUNDARY-SCAN REGISTER
Boundary Scan register permits testing printed circuit board interconnects such opens shorts while also providing access components inputs outputs when testing monitoring system logic. QS3J309, Boundary Scan register bits long, with boundary scan cell each QuickSwitch I/O. BoundaryScan cells facilitate both observation control QuickSwitch gate I/Os'.
Each boundary scan cell configured input, output tri-state depending input data TDI.
Table IDCODE Instructions
Version (bits 31-28) 0000 Part Number (27-12) 1011111010101101 (BEADH) I.D. (11-1) 00011101001 (E9h) LSB(0)
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QS3J309
Data applied input appears without inversion during Shift-DR state following cycles. Capture-DR state, data will parallel loaded into Boundary Scan register upon rising edge TCK. Contents Boundary Scan register will latched into shadow register upon falling edge UpdateDR state provided that selected current instruction.
TIMING operations QS3J309 device synchronous TCK. controller changes state only response rising edge transition logic TRST input power-up. state transitions controller shown Figure occur based value rising edge TCK. Data TDI, TMS, normal function inputs captured falling edge TCK. Data appears normal function output pins falling edge TCK. simple timing example Bypass mode shown Figure controller starts Test-Logic-Reset state advanced through states necessary perform IR-Scan DR-Scan. Shift-IR Shift-DR states, used input serial data, used output serial data. Table describes operation device during each cycle. Another simple timing example Scan mode shown Figure very similar previous example, except data available after cycles. Table describes operation device during each cycle.
BYPASS REGISTER
Bypass register provides minimum length serial path movement test data between TDO. this register speeds access test data registers other components board-level test data path. Bypass register consists single shift register. Bypass register must logic value upon rising edge Shift-DR state provided that selected current instruction. Upon initial scan data registers connected across board, devices will connect device Identification register while Shift-DR state. This condition result power-up assertion optional instruction) initialize each JTAG device board. first logic high will framing device Identification register which would then indicate that following bits identifiers specific device that location scan chain.
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QS3J309 Table Explanation Timing Example Bypass Mode. (See Figure
Cycle(s) State After Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR captures 8-bit binary value 00000001 rising edge controller exits Capture-IR state. becomes active made valid falling edge TCK. first shifted into rising edge controller advances next state. shifted into each rising edge. With held logic value, 8-bit binary value 00000011 serially scanned into same time, 8-bit binary value 00000001 serially scanned TDO. cycle changed logic value scan next cycle. last instruction shifted controller advances from Shift-IR Exit1-IR. becomes inactive (goes high-impedance state) falling edge TCK. updated with instruction (Bypass) falling edge TCK. Bypass register captures logic value rising edge controller exits Capture-DR state. becomes active made valid falling edge TCK. first shifted into rising edge controller advances next state. binary value shifted TDI, while binary value shifted TDO. becomes inactive (goes high-impedance state) falling edge TCK. general, selected data register updated with data falling edge TCK. Description changed logic value falling edge begin advancing controller toward desired state.
7-13
Shift-IR
Exit1-IR Update-IR Select-DR-Scan Capture-DR Shift-DR
19-20
Shift-DR Exit1-DR Update-DR Select-DR-Scan Select-IR-Scan Test-Logic-Reset
Test operation completed.
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QS3J309 Table Explanation Timing Example Scan Mode. (See Figure
Cycle(s) State After Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR captures 8-bit binary value 00000001 rising edge controller exits Capture-IR state. becomes active made valid falling edge TCK. first shifted into rising edge controller advances next state. shifted into each rising edge. With held logic value, 8-bit binary value 00000001 serially scanned into same time, 8-bit binary value 00000001 serially scanned TDO. cycle changed logic value scan next cycle. last instruction shifted controller advances from Shift-IR Exit1-IR. becomes inactive (goes high-impedance state) falling edge TCK. updated with instruction (Sample/Preload) falling edge TCK. Scan register captures rising edge controller exits Capture-DR state. becomes active made valid falling edge TCK. first shifted into rising edge controller advances next state. binary value shifted available after cycles. valid data 101. becomes inactive (goes high-impedance state) falling edge TCK. general, selected data register updated with data falling edge TCK. Description changed logic value falling edge begin advancing controller toward desired state.
7-13
Shift-IR
Exit1-IR Update-IR Select-DR-Scan Capture-DR Shift-DR
19-72 73-75
Shift-DR Shift-DR Exit1-DR Update-DR Select-DR-Scan Select-IR-Scan Test-Logic-Reset
Test operation completed.
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QS3J309 Figure Timing Example Bypass Mode
Test-Logic-Reset Test-Logic-Reset Select-DR-Scan Select-DR-Scan Select-DR-Scan
Select-DR-Scan
Select-IR-Scan
Tri-state Don't Care
Figure Timing Example Scan Mode
Test-Logic-Reset
Exit1-IR
Shift-IR
Controller State
Tri-state Don't Care
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Exit1-IR
Shift-IR
Controller State
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Test-Logic-Reset
Select-DR-Scan
Select-DR-Scan
Select-IR-Scan
Select-IR-Scan
Run-Test/Idle
Capture-DR
Update-DR
Capture-IR
Update-IR
Exit1-DR
Shift-DR
Select-IR-Scan
Run-Test/Idle
Capture-DR
Update-DR
Capture-IR
Update-IR
Exit1-DR
Shift-DR

QuickScan9-Bit Universal JTAG Access Port with Output Enable QS3J

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