Programmable Logic Device 44-pin, CPLD 100% connected Maximum Pin-to-p

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Programmable Logic Device 44-pin, CPLD 100% connected Maximum Pin-to-p

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Operates between 2.7V 5.5V High-density, High-performance Electrically-erasable Complex
Programmable Logic Device 44-pin, CPLD 100% connected Maximum Pin-to-pin Delay Registered Operation 90.9 Fully Connected Input Feedback Logic Array Flexible Logic Macrocell D/T/Latch Configurable Flip-flops Global Individual Register Control Signals Global Individual Output Enable Programmable Output Slew Rate Advanced Power Management Features Pin-controlled Standby Mode (Typical) Programmable Pin-keeper Inputs I/Os Available Commercial Industrial Temperature Ranges Available 44-lead PLCC TQFP Packages Advanced EEPROM Technology 100% Tested Completely Reprogrammable 10,000 Program/Erase Cycles 20-year Data Retention 2000V Protection Latchup Immunity Supported Popular Third-party Tools Security Fuse Feature
Highperformance ATF1500ABV
Description
ATF1500ABV high-performance, high-density complex PLD. Built advanced EEPROM technology, maximum pin-to-pin delays supports sequential logic operation speeds 90.9 MHz. With logic macrocells inputs, easily integrates logic from several TTL, SSI, classic PLDs.
Configurations
Name GCLR OE1, Function Clock Logic Inputs Bi-directional Buffers Register Reset (active low) Output Enable (active low) (+3V 5.25V) Supply Power-down (active high)
PLCC View
I/O/PD OE2/I GCLR/I OE1/I CLK/I
TQFP View
I/O/PD OE2/I GCLR/I OE1/I CLK/I
Rev. 0723I-08/01
Functional Logic Diagram(1)
Note:
Arrows connecting macrocells indicate direction groupings CASIN/CASOUT data flow.
ATF1500ABV
0723I-08/01
ATF1500ABV
ATF1500ABV's 100% connected global input feedback architecture simplifies logic placement eliminates pinout changes design changes. Macrocell connected pin. ATF1500ABV bi-directional pins four dedicated input pins. Each dedicated input also serve global control signal: register clock, register reset output enable. Each these control signals selected individually within each macrocell. Each logic macrocells generates buried feedback, which goes global bus. Each input also feeds into global bus. Because this global busing, each these signals always available macrocells device. Each macrocell also generates foldback logic term, which goes regional bus. signals within regional connected macrocells within region. Cascade logic between macrocells ATF1500ABV allows fast, efficient generation complex logic functions. ATF1500ABV contains four such logic chains, each capable creating term logic with fan-in product terms.
Bus-friendly Pin-keeper Input I/Os
input pins ATF1500ABV have programmable "data-keeper" circuits. activated, when driven high then subsequently left floating, will stay that previous high level. This circuitry prevents unused input lines from floating intermediate voltage levels that cause unnecessary power consumption system noise. keeper circuits eliminate need external pull-up resistors eliminate their power consumption. Pin-keeper circuits disabled. Programming controlled logic design file. Once pin-keeper circuits disabled, normal termination procedures required unused inputs I/Os.
Speed/Power Management
ATF1500ABV several built-in speed power management features. ATF1500ABV contains circuitry that automatically puts device into low-power standby mode when logic transitions occurring. This only reduces power consumption during inactive periods, also provides proportional power savings most applications running system speeds below MHz. ATF1500ABVs also have optional pin-controlled power-down mode. this mode, current drops typically When power-down option selected, used power-down part. power-down option selected design source file. When enabled, device goes into power-down when high. power-down mode, internal logic signals latched held, enabled outputs. transitions ignored until brought low. When power-down feature enabled, cannot used logic input output. However, pin's macrocell still used generate buried foldback cascade logic signals. Each output also individual slew rate control. This used reduce system noise slowing down outputs that need operate maximum speed. Outputs default slow switching, specified fast switching design file.
0723I-08/01
Input Diagram
INPUT 100K
PROTECTION CIRCUIT
PROGRAMMABLE OPTION
Diagram
DATA
100K
PROGRAMMABLE OPTION
Design Software Support
ATF1500ABV designs supported several third-party tools. Automated fitters allow logic synthesis using variety high level description languages formats.
ATF1500ABV
0723I-08/01
ATF1500ABV
ATF1500ABV Macrocell
ATF1500ABV Macrocell
ATF1500ABV macrocell flexible enough support highly complex logic functions operating high speed. macrocell consists five sections: product terms product term select multiplexer; OR/XOR/CASCADE logic; flip-flop; output select enable; logic array inputs. Each ATF1500ABV macrocell five product terms. Each product term receives inputs signals from both global regional bus. product term select multiplexer (PTMUX) allocates five product terms needed macrocell logic gates control signals. PTMUX programming determined design compiler, which selects optimum macrocell configuration.
Product Terms Select
OR/XOR/ CASCADE Logic
ATF1500ABV macrocell's OR/XOR/CASCADE logic structure designed efficiently support types logic. Within single macrocell, product terms routed gate, creating five-input AND/OR term. With addition CASIN from neighboring macrocells, this expanded many product terms with little small additional delay. macrocell's gate allows efficient implementation compare arithmetic functions. input comes from term. other input product term fixed high level. combinatorial outputs, fixed-level input allows output polarity selection. registered functions, fixed levels allow Morgan minimization product terms. gate also used emulate JK-type flip-flops.
0723I-08/01
Flip-flop
ATF1500ABV's flip-flop very flexible data control functions. data input come from either gate from separate product term. Selecting separate product term allows creation buried registered feedback within combinatorial output macrocell. addition operation, flip-flop also configured flow-through latch. this mode, data passes through when clock high latched when clock low. clock itself either global individual product term. flip-flop changes state clock's rising edge. When used clock, macrocell product terms selected clock enable. When clock enable function active enable signal (product term) low, clock edges ignored. flip-flop's asynchronous reset signal (AR) either global clear (GCLR), product term, always off. also logic GCLR with product term. asynchronous preset (AP) product term always off.
Output Select Enable
ATF1500ABV macrocell output selected registered combinatorial. When output registered, same registered signal back internally global bus. When output combinatorial, buried feedback either same combinatorial signal register output separate product term chosen flip-flop input. output enable multiplexer (MOE) controls output enable signals. buffer permanently enabled simple output operation. Buffers also permanently disabled allow input. this configuration macrocell resources still available, including buried feedback, expander CASCADE logic. output enable each macrocell also selected either pins individual product term.
Global/Regional Buses
global contains input signals well buried feedback signal from macrocells. Together with complement each signal, this provides 68-bit input every product term. Having entire global available each macrocell eliminates potential routing problems. With this architecture designs modified without requiring pinout changes. Each macrocell also generates foldback product term. This signal goes regional bus, available macrocells. foldback inverse polarity macrocell's product terms. foldback terms each region allow generation high fan-in terms product terms) with little additional delay.
ATF1500ABV
0723I-08/01
ATF1500ABV
Absolute Maximum Ratings*
Temperature Under Bias. -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-2.0V +5.25V(1) Voltage Input Pins with Respect Ground During Programming.-2.0V +14.0V(1) Programming Voltage with Respect Ground .-2.0V +14.0V(1) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Note:
Minimum voltage -0.6V which undershoot -2.0V pulses less than Maximum voltage 0.75V which overshoot 5.25V pulses less than
Operating Conditions
Commercial Operating Temperature (Ambient) Power Supply 70°C 2.7V 5.5V Industrial -40°C 85°C 2.7V 5.5V
Characteristics
Symbol ICC1(1) Parameter Input Leakage Current Input High Leakage Current Power Supply Current, Standby Condition VIL(max) VIH,min MAX, ATF1500ABV Com. Ind. ATF1500ABVL Com. Ind. ICC2 Note: Power Supply Current, Power Down Mode Output Short Circuit Current Input Voltage Input High Voltage Output Voltage MAX, VOUT 0.5V VCC, VCC, -0.5 -130 0.45 Units
Output High Voltage -0.1 parameters measured with outputs open, 16-bit loadable, up/down counter programmed into each region.
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Waveforms
Register Characteristics, Input Clock(1)
Symbol tCOS tCFS tSIS tSFS fMAXS
58.8 76.9 76.9 52.6 71.4 71.4 Units
Parameter Clock Output Clock Feedback Setup Time Feedback Setup Time Input, I/O, Feedback Hold Time Clock Period Clock Width External Feedback 1/(tSIS tCOS) Internal Feedback 1/(tSFS tCFS) Feedback 1/(tPS)
2.7-volt Adder -5.5 -5.5
tRPRS tRTRS Notes:
Reset Recovery Time
Reset Term Recovery Time Characteristics volts. volts, "2.7-volt adder." slow slew outputs, tSSO.
Preliminary Information
ATF1500ABV
0723I-08/01
ATF1500ABV
Register Characteristics, Product Term Clock(1)
Symbol tCOA tCFA tSIA tSFA fMAXA Parameter Clock Output Clock Feedback Setup Time Feedback Setup Time Input, I/O, Feedback Hold Time Clock Period Clock Width External Feedback 1/(tSIA tCOA) Internal Feedback 1/(tSFA tCFA) Feedback 1/(tPA) tRPRA tRTRA Notes: Reset Recovery Time 2.7-volt Adder -6.4 -6.4 62.5 83.3 83.3 52.6 71.4 71.4 Units
Reset/Preset Term Recovery Time Characteristics volts. volts, "2.7-volt Adder." slow slew outputs, tSSO.
Characteristics(1)
Symbol tPD(2) tPD2 tPD3 tPD4
Units
Parameter Non-Registered Output Feedback Feedback Non-Registered Output Feedback Feedback Term Output Enable Term Output Disable
2.7-volt Adder
tPZX tPXZ
Output Enable Output Disable Preset Feedback Preset Registered Output Reset Feedback Reset Registered Output Reset Term Feedback
tRPF tRPO(2) tRTF tRTO tCAS tSSO tFLD Notes:
Reset Term Registered Output Cascade Logic Delay Slow Slew Output Adder Foldback Term Delay
Characteristics volts. volts, "2.7-volt Adder." slow slew outputs, tSSO.
Preliminary Information
0723I-08/01
Power-down Characteristics(1)
Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes:
Units
Parameter Valid before High Valid
2.7-volt Adder
before High
Valid Clock
before High
Input Don't Care after High Don't Care after High Clock Don't Care after High Valid Valid OE(3) Valid Clock(3)
Valid Output Characteristics volts. volts, "2.7-volt Adder." slow slew outputs, tSSO. Product Term.
Preliminary Information
Input Test Waveforms Measurement Levels
Output Test Load
Capacitance
MHz, 25°C)(1)
COUT Note: Units Conditions VOUT
Typical values nominal supply voltage. This parameter only sampled 100% tested.
ATF1500ABV
0723I-08/01
ATF1500ABV
Power-up Reset
ATF1500ABV's registers designed reset during power-up. point delayed slightly from crossing VRST, registers will reset state. result, registered output state will always power-up. This feature critical state machine initialization. However, asynchronous nature reset uncertainty actually rises system, following conditions required: rise must monotonic, from below volts. Signals from which clocks derived must remain stable during TPR. After occurs, input feedback setup times must before driving clock signal high.
Power-down Mode
ATF1500ABV includes optional pin-controlled power-down feature. When this mode enabled, acts power-down pin. When high, device supply current reduced less than During power-down, output data internal logic states latched held. Therefore, registered combinatorial output data remain valid. outputs that were High-Z state onset power-down will remain High-Z. During power-down, input signals except power-down blocked. Input hold latches remain active ensure that pins float indeterminate levels, further reducing system power. power-down feature enabled logic design file. Designs using power-down logic array input. However, other macrocell resources still used, including buried feedback foldback product term array inputs. ATF1500ABV's registers provided with circuitry allow loading each register with either high low. This feature will simplify testing since state forced into registers control test sequencing. JEDEC file with preload generated when source file with preload vectors compiled. Once downloaded, JEDEC file preload sequence will done automatically when vectors approved programmers. preload mode enabled raising input high voltage level. Contact Atmel Applications PRELOAD assignments, timing voltage requirements.
Register Preload
Parameter
Description Power-up Reset Time Power-up Reset Voltage
Units
VRST
0723I-08/01
Output Slew Rate Control
Each ATF1500ABV macrocell contains configuration each control output slew rate. This allows selected data paths operate maximum throughput while reducing system noise from outputs that speed-critical. Outputs default slow edges, individually fast design file. Output transition times outputs configured "slow" have tSSO delay adder. single fuse provided prevent unauthorized copying ATF1500ABV fuse patterns. Once programmed, fuse verify preload prohibited. However, 160-bit User Signature remains accessible. security fuse should programmed last, effect immediate.
Security Fuse Usage
ATF1500ABV
0723I-08/01
ATF1500ABV
Ordering Information
(ns) tCOS (ns) FMAXS (MHz) 62.5 52.6 Ordering Code ATF1500ABV-12AC ATF1500ABV-12JC ATF1500ABV-15AC ATF1500ABV-15JC ATF1500ABV-15AI ATF1500ABV-15JI Package Operation Range Commercial (0°C 70°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Using Product Industrial
commercial product Industrial temperature ranges, down-grade speed grade from device "I") de-rate power 30%.
Package Type 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
0723I-08/01
Packaging Information
44A, 44-lead, Thin (1.0 Plastic Gull Wing Quad Flat Package (TQFP) Dimensions Millimeters (Inches)* 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions Inches (Millimeters)
12.21(0.478) 11.75(0.458)
.045(1.14)
IDENTIFY
.045(1.14)
.012(.305) .008(.203)
.656(16.7) .650(16.5)
.630(16.0) .590(15.0) .021(.533) .013(.330)
0.80(0.031)
0.45(0.018) 0.30(0.012)
.032(.813) .026(.660)
.695(17.7) .685(17.4)
.050(1.27) .500(12.7)
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
10.10(0.394) 9.90(0.386) 1.20(0.047)
.022(.559) (3X)
0.20(.008) 0.09(.003)
0.75(0.030) 0.15(0.006) 0.45(0.018) 0.05(0.002)
*Controlling dimension: millimeters
ATF1500ABV
0723I-08/01
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0723I-08/01/xM

Programmable Logic Device 44-pin, CPLD 100% connected Maximum Pin-to-p

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