LC2MOS 12-Bit DACPORTs AD7245A/AD7248A AD7245A FUNCTIONAL BLOCK D

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LC2MOS 12-Bit DACPORTs AD7245A/AD7248A AD7245A FUNCTIONAL BLOCK D

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FEATURES 12-Bit CMOS with Output Amplifier Reference Improved AD7245/AD7248: Operation Linearity Grade Faster Interface-30 Data Setup Time Extended Plastic Temperature Range (-40 Single Dual Supply Operation Power-65 Single Supply Parallel Loading Structure: AD7245A (8+4) Loading Structure: AD7248A GENERAL DESCRIPTION
LC2MOS 12-Bit DACPORTs AD7245A/AD7248A
AD7245A FUNCTIONAL BLOCK DIAGRAM
ROFS VOUT VREF AGND
LDAC CONTROL LOGIC
LATCH
AD7245A
INPUT LATCH
AD7245A/AD7248A enhanced version industry standard AD7245/AD7248. Improvements include operation from supplies, linearity grade, faster interface times better full scale reference variations with VDD. Additional features include extended temperature range operation commercial industrial grades. AD7245A/AD7248A complete, 12-bit, voltage output, digital-to-analog converter with output amplifier Zener voltage reference monolithic CMOS chip. external user trims required achieve full specified performance. Both parts microprocessor compatible, with high speed data latches double-buffered interface logic. AD7245A accepts 12-bit parallel data that loaded into input latch rising edge AD7248A 8-bit-wide data with data loaded input latch write operations. both parts, asynchronous LDAC signal transfers data from input latch latch updates analog output. AD7245A also signal latch which allows features such power-on reset implemented. on-chip buried Zener diode provides noise, temperature compensated reference DAC. single supply operation, output ranges available, while these ranges plus additional range available with dual supplies. output amplifiers capable developing across load GND. AD7245A/AD7248A fabricated linear compatible CMOS (LC2MOS), advanced, mixed technology process that combines precision bipolar circuits with power CMOS logic. AD7245A available small, 0.3" wide, 24-lead SOIC 28-terminal surface mount packages. AD7248A packaged small, 0.3" wide, 20-lead SOIC 20-terminal surface mount packages.
DB11
DGND
AD7248A FUNCTIONAL BLOCK DIAGRAM
ROFS VOUT VREF AGND
LDAC CSLSB CSMSB CONTROL LOGIC
LATCH
AD7248A
4-BIT INPUT LATCH 8-BIT INPUT LATCH
DGND
PRODUCT HIGHLIGHTS
AD7245A/AD7248A 12-bit DACPORT® single chip. This single chip design small package size offer considerable space saving increased reliability over multichip designs. improved interface times part allows easy, direct interfacing most modern microprocessors. AD7245A/AD7248A features wide power supply range allowing operation from supplies.
DACPORT registered trademark Analog Devices, Inc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2001
AD7245A/AD7248A-SPECIFICATIONS AGND DGND specifications unless otherwise noted.)
Parameter STATIC PERFORMANCE Resolution Relative Accuracy 25°C3 TMIN TMAX TMIN TMAX Differential Nonlinearity3 Unipolar Offset Error 25°C3 TMIN TMAX Bipolar Zero Error 25°C3 TMIN TMAX Gain Error3, Full-Scale Output Voltage Error7 25°C Full Scale/VDD Full Scale/VSS Full-Scale Temperature Coefficient8 REFERENCE OUTPUT 25°C OUT/VDD Reference Temperature Coefficient Reference Load Change (REF DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance9 ANALOG OUTPUTS Output Range Resistors Output Voltage Ranges10
Version 0.06 0.01
Version 0.06 0.01
Version 0.06 0.01
Unit Bits FSR/V FSR/V FSR/°C
Test Conditions/Comments
Guaranteed Monotonic Typical Tempco FSR5/°C. ROFS connected OUT; Typical Tempco FSR5/°C. Reference Load Current Change (0-100
4.99/5.01 4.99/5.01 15/30 15/30
4.99/5.01 min/V mV/V ppm/°C 15/30 min/k
Strappable Strappable
Output Impedance CHARACTERISTICS9 Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Output Voltage Slew Rate Digital Feedthrough3 Digital-to-Analog Glitch Impulse POWER REQUIREMENTS 25°C TMlN TMAX (Dual Supplies)
+10.8/ +16.5 -10.8/ -16.5
+10.8/ +16.5 -10.8/ -16.5
+10.8/ +16.5 -10.8/ -16.5
V/µs nV-s nV-s min/ min/
Settling Time Within Final Value Latch Latch
Specified Performance Unless Otherwise Stated Specified Performance Unless Otherwise Stated Output Unloaded; Typically Output Unloaded Output Unloaded; Typically
NOTES Power supply tolerance 10%. Temperature ranges follows: Versions; -40°C +85°C; Version; -55°C +125°C. Terminology. With appropriate power supply tolerances. means Full-Scale Range output range both output ranges. This error calculated with respect reference voltage measured after offset error been allowed for. This error calculated with respect ideal 4.9988 ranges; calculated with respect ideal 9.9976 range. includes effects internal voltage reference, gain offset errors. Full-Scale FS/T, where full-scale change from 25°C TMIN TMAX. Guaranteed design characterization, production tested. output range available only when +14.25 Specifications subject change without notice.
REV.
AD7245A/AD7248A SWITCHING CHARACTERISTICS1
Parameter 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX 25°C TMIN TMAX (AD7245A Only) 25°C TMIN TMAX
NOTES Sample tested 25°C ensure compliance. Power supply tolerance 10%.
Figures
Version Unit Conditions Chip Select Pulsewidth
Versions
Write Pulsewidth
Chip Select Write Setup Time
Chip Select Write Hold Time
Data Valid Write Setup Time
Data Valid Write Hold Time
Load Pulsewidth
Clear Pulsewidth
ABSOLUTE MAXIMUM RATINGS
AGND -0.3 DGND -0.3 -0.3 AGND DGND -0.3 Digital Input Voltage DGND -0.3 VOUT AGND2 VSS, VOUT VSS2 VOUT VDD2 OUT2 AGND Power Dissipation (Any Package) 75°C Derates above 75°C mW/°C
Operating Temperature Commercial Versions) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, secs) 300°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. output shorted voltages this range provided power dissipation package exceeded. short circuit current typically
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7245A/AD7248A features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7245A/AD7248A
AD7245A ORDERING GUIDE GAIN ERROR
Model1 AD7245AAN AD7245ABN AD7245AAQ AD7245ATQ3 AD7245AAP AD7245AAR AD7245ABR AD7245ATE3
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Relative Accuracy
Package Option2 N-24 N-24 Q-24 Q-24 P-28A R-24 R-24 E-28A
Gain Error measure output error between ideal actual device output with loaded after offset error been allowed for. therefore defined Measured Value-Offset-Ideal Value where ideal value calculated relative actual reference value.
UNIPOLAR OFFSET ERROR
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data sheet availability. Leadless Ceramic Chip Carrier; Plastic DIP; Plastic Leaded Chip Carrier; Cerdip; SOIC. This grade will available /883B processing only.
Unipolar Offset Error combination offset errors voltage mode output amplifier measured when part configured unipolar outputs. present codes measured with register.
BIPOLAR ZERO OFFSET ERROR
Bipolar Zero Offset Error measured when part configured bipolar output combination errors from output amplifier. present codes measured with code 2048 (decimal) register.
SINGLE SUPPLY LINEARITY GAIN ERROR
AD7248A ORDERING GUIDE
Model
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C
Relative Accuracy
Package Option2 N-20 N-20 Q-20 Q-20 P-20A R-20 R-20
AD7248AAN AD7248ABN AD7248AAQ AD7248ATQ3 AD7248AAP AD7248AAR AD7248ABR
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data sheet availability. Plastic DIP; Plastic Leaded Chip Carrier; Cerdip; SOIC. This grade will available /883B processing only.
TERMINOLOGY
RELATIVE ACCURACY
Relative Accuracy, endpoint nonlinearity, measure actual deviation from straight line passing through endpoints transfer function. measured after allowing zero full scale normally expressed LSBs percentage full-scale reading.
DIFFERENTIAL NONLINEARITY
output amplifier AD7245A/AD7248A have true negative offset even when part operated from single positive power supply. However, because lower supply rail part output voltage cannot actually negative. Instead output voltage sits lower rail this results transfer function shown. This offset effect transfer function would have followed dotted line output voltage could have gone negative. Normally, linearity measured after offset full scale have been adjusted allowed for. AD7245A/AD7248A negative offset allowed calculating linearity from code which amplifier comes lower rail. This code given negative offset specification. example, single supply linearity specification applies between Code Code 4095 25°C specification between Code Code 4095 over TMIN TMAX temperature range. Since gain error also measured after offset been allowed for, calculated between same codes linearity error. Bipolar linearity gain error measured between Code Code 4095.
OUTPUT VOLTAGE
Differential Nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity over operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGH
Digital Feedthrough glitch impulse injected from digital inputs analog output when inputs change state. measured with LDAC high specified nV-s.
NEGATIVE OFFSET
CODE
REV.
AD7245A/AD7248A
AD7245A FUNCTION DESCRIPTIONS (DIP NUMBERS)
Mnemonic Description ROFS Negative Supply Voltage single supply operation). Bipolar Offset Resistor. This provides access on-chip application resistors allows different output voltage ranges. Reference Output. on-chip reference provided this used when configuring part bipolar outputs. Analog Ground. Data Most Significant (MSB). Digital Ground. Data Data Data Least Significant (LSB). Chip Select Input (Active LOW). device selected when this input active.
Mnemonic
Description Write Input (Active LOW). This used conjunction with write data into input latch AD7245A. Load Input (Active LOW). This asynchronous input which when active transfers data from input latch latch. Clear Input (Active LOW). When this input active contents latch reset Positive Supply Voltage. Feedback Resistor. This allows access amplifier's feedback loop. Output Voltage. Three different output voltage ranges chosen:
LDAC
6-11
AGND DB11 DGND
DB10-DB5 Data Data
VOUT
13-16 DB4-DB1
AD7245A CONFIGURATIONS
SOIC
ROFS
ROFS AGND (MSB) DB11 DB10 DGND VOUT
PLCC
VOUT
LCCC
ROFS VOUT
LDAC
AD7245A
VIEW (NOT SCALE)
AGND DB11 DB10
LDAC
AGND DB11 DB10
LDAC (LSB)
AD7245A
VIEW (NOT SCALE)
AD7245A
VIEW (NOT SCALE)
DGND
DGND
CONNECT
CONNECT
REV.
AD7245A/AD7248A
AD7248A FUNCTION DESCRIPTIONS (ANY PACKAGE)
Mnemonic ROFS
Description Negative Supply Voltage single supply operation). Bipolar Offset Resistor. This provides access on-chip application resistors allows different output voltage ranges. Reference Output. on-chip reference provided this used when configuring part bipolar outputs. Analog Ground. Data Data Data Data Data Digital Ground. Data 2/Data Data 1/Data Data (LSB)/Data
Mnemonic CSMSB
Description Chip Select Input Nibble. (Active LOW). This selects upper bits input latch. Input data right justified. Chip Select Input byte. (Active LOW). This selects lower bits input latch. Write Input. This used conjunction with CSMSB CSLSB load data into input latch AD7248A. Load Input (Active LOW). This asynchronous input which when active transfers data from input latch latch. Positive Supply Voltage. Feedback Resistor. This allows access amplifier's feedback loop. Output Voltage. Three different output voltage ranges chosen:
CSLSB
AGND DGND
LDAC
VOUT
AD7248A CONFIGURATIONS SOIC
PLCC
LCCC
ROFS
VOUT
ROFS
VOUT
ROFS AGND (MSB) DGND
LDAC VIEW (NOT SCALE) CSLSB CSMSB (LSB)
LDAC CSLSB CSMSB
AGND (MSB)
IDENTIFIER
AGND (MSB)
VOUT
AD7248A
AD7248A
VIEW (NOT SCALE)
AD7248A
VIEW (NOT SCALE)
LDAC
CSLSB CSMSB
(LSB)
(LSB)
DGND
DGND
REV.
Typical Performance Characteristics- AD7245A/AD7248A
(VSS -15V, INH) POWER SUPPLY CURRENT (VSS VDD) (VSS -15V, +15V 4.995
REFERENCE VOLTAGE Volts
5.000
5.005
(VSS -15V)
TEMPERATURE
5.010
TEMPERATURE
Power Supply Current Temperature
Reference Voltage Temperature
REFERENCE DECOUPLING)
PSRR
OUTPUT WITH
DECOUPLING*
DECOUPLING OUTPUT WITH DECOUPLING
REFERENCE (DECOUPLED*)
DECOUPLING
OUTPUT WITH FREQUENCY
WITH 100mV SIGNAL 100k FREQUENCY *POWER SUPPLY DECOUPLING CAPACITORS
*REFERENCE DECOUPLING COMPONENTS FIGURE
Noise Spectral Density Frequency
Power Supply Rejection Ration Frequency
Positive-Going Settling Time (VDD
Negative Going Settling Time (VDD
REV.
AD7245A/AD7248A
CIRCUIT INFORMATION SECTION
AD7245A/AD7248A contains 12-bit voltage mode digital-to-analog converter. output voltage from converter same positive polarity reference voltage allowing single supply operation. reference voltage provided on-chip buried Zener diode. consists highly stable, thin-film, R-2R ladder twelve high-speed NMOS single-pole, double-throw switches. simplified circuit diagram this shown Figure
ROFS
small signal (200 p-p) bandwidth output buffer amplifier typically MHz. output noise from amplifier with figure nV/Hz frequency kHz. broadband noise from amplifier typical peak-topeak figure output bandwidth. There significant difference output noise between single dual supply operation.
VOLTAGE REFERENCE
VREF AGND
DB10 DB11
VOUT
SHOWN
Figure Simplified Circuit Diagram
input impedance code dependent vary from infinity. input capacitance also varies with code, typically from
SECTION
AD7245A/AD7248A contains internal noise buried Zener diode reference which trimmed absolute accuracy temperature coefficient. reference internally connected DAC. Since variable input impedance reference input Zener diode reference buffered. This buffered reference available user drive circuitry required bipolar output ranges. used reference other parts system provided externally buffered. reference will give long-term stability comparable with best discrete Zener reference diodes. performance AD7245A/AD7248A specified with internal reference, testing trimming done with this reference. reference should decoupled recommended decoupling components capacitors series with resistor. simplified schematic reference circuitry shown Figure
output voltage mode converter buffered noninverting CMOS amplifier. user access gain setting resistors which connected allow different output voltage ranges (discussed later). buffer amplifier capable developing across load GND. output amplifier operated from single positive power supply tying AGND amplifier also operated from dual supplies allow bipolar output range advantages having dual supplies unipolar output ranges faster settling time voltages near full sink capability maintained over entire output range elimination effects negative offset transfer characteristic (outlined previously). Figure shows sink capability amplifier single supply operation.
V-TO-I
AGND
TEMPERATURE COMPENSATION CURRENT
Figure Internal Reference
DIGITAL SECTION
AD7245A/AD7248A digital inputs compatible with either CMOS levels. data inputs static protected gates with typical input currents less than control inputs sink higher currents (150 max) result fast digital interfacing. Internal input protection logic inputs achieved on-chip distributed diodes. AD7245A/AD7248A features very digital feedthrough figure nV-s output range. This voltage mode configuration DAC. Most impulse actually result feedthrough across package.
INTERFACE LOGIC INFORMATION-AD7245A
ISINK
OUTPUT VOLTAGE Volts
Figure Typical Single Supply Sink Current Output Voltage
Table shows truth table AD7245A operation. part contains 12-bit latches, input latch latch. control loading input latch while LDAC controls transfer information from input latch latch. control signals level triggered; therefore, either both latches made transparent, input latch keeping "LOW", latch keeping LDAC "LOW." Input data latched rising edge
REV.
AD7245A/AD7248A
data held latch determines analog output converter. Data latched into latch rising edge LDAC. This LDAC signal asynchronous signal independent This useful many applications. However, systems where asynchronous LDAC occur during write cycle vice versa) care must taken ensure that incorrect data latched through output. example, LDAC goes while "LOW," then LDAC signal must stay longer after goes high ensure correct data latched through output.
Table AD7245A Truth Table
LDAC
HIGH IMPEDANCE
DATA
VALID DATA
LDAC
Function Both Latches Transparent Both Latches Latched Both Latches Latched Input Latches Transparent Input Latches Latched Latches Transparent Latches Latched Latches Loaded with Latches Latched with Output Remains Both Latches Transparent Output Follows Input
NOTES TIMING SPECIFICATIONS. INPUT RISE FALL TIMES MEASURES FROM 5ns. TIMING MEASUREMENT REFERENCE LEVEL VINH LDAC ACTIVATED WHILE LOW, LDAC MUST STAY LONGER AFTER GOES HIGH.
Figure AD7245A Write Cycle Timing Diagram
INTERFACE LOGIC INFORMATION-AD7248A
input loading structure AD7248A configured interfacing microprocessors with 8-bit wide data bus. part contains 12-bit latches-an input latch latch. Only data held latch determines analog output from converter. truth table AD7248A operation shown Table while input control logic diagram shown Figure
LDAC LATCH CSMSB UPPER BITS INPUT LATCH
High State, State, Don't Care contents latch reset level line. With both latches transparent, line functions like zero override with output brought unipolar mode bipolar mode duration pulse. both latches latched, "LOW" pulse input latches into latch output remains after line returned "HIGH." line used ensure power-up AD7245A output unipolar operation also useful, when used zero override, system calibration cycles. Figure shows input control logic AD7245A write cycle timing part shown Figure
LDAC INPUT LATCH
LOWER BITS INPUT LATCH
CSLSB
Figure AD7248A Input Control Logic
LATCH
INPUT DATA
Figure AD7245A Input Control Logic
CSMSB, CSLSB control loading data from external data input latch. eight data inputs AD7248A accept right justified data. This data loaded input latch separate write operations. CSLSB control loading lower 8-bits into 12-bit wide latch. loading upper 4-bit nibble controlled CSMSB control inputs level triggered, input data either lower byte upper 4-bit nibble latched into input latches rising edge either CSMSB CSLSB). order which data loaded input latch (i.e., lower byte upper 4-bit nibble first) important.
REV.
AD7245A/AD7248A
LDAC input controls transfer 12-bit data from input latch latch. This LDAC signal also level triggered, data latched into latch rising edge LDAC. LDAC input asynchronous independent This useful many applications especially simultaneous updating multiple AD7248A outputs. However, systems where asynchronous LDAC occur during write cycle vice versa) care must taken ensure that incorrect data latched through output. other words, LDAC goes while either input either while LDAC low), then LDAC signal must stay longer after returns high ensure correct data latched through output. write cycle timing diagram AD7248A shown Figure
CSLSB
APPLYING AD7245A/AD7248A
internal scaling resistors provided AD7245A/ AD7248A allow several output voltage ranges. part produce unipolar output ranges bipolar output range Connections various ranges outlined below.
UNIPOLAR CONFIGURATION
first configurations provides output voltage range This achieved connecting bipolar offset resistor, ROFS, AGND connecting VOUT. this configuration AD7245A/AD7248A operated single supply (VSS AGND). dual supply performance required, should applied. Figure shows connection diagram unipolar operation while table output voltage versus digital code latch shown Table III.
ROFS
CSMSB
VALID DATA
LDAC
VREF
VOUT
AD7245A/AD7248A*
DGND *DIGITAL CIRCUITRY OMITTED CLARITY AGND
DATA
VALID DATA
Figure AD7248A Write Cycle Timing Diagram
alternate scheme writing data AD7248A CSMSB LDAC inputs together. this case exercising CSLSB latches lower bits into input latch. second write, which exercises CSMSB, LDAC loads upper 4-bit nibble input latch same time transfers 12-bit data latch. This automatic transfer mode updates output AD7248A write operations. This scheme works equally well CSLSB LDAC tied together provided upper 4-bit nibble loaded input latch followed write lower bits input latch.
Table AD7248A Truth Table
CSLSB CSMSB LDAC Function Load Byte into Input Latch Latches Byte into Input Latch Latches Byte into Input Latch Loads Nibble into Input Latch Latches Nibble into Input Latch Latches Nibble into Input Latch Loads Input Latch into Latch Latches Input Latch into Latch Loads Nibble into Input Latch Loads Input Latch into Latch Data Transfer Operation
Figure Unipolar Configuration
Table III. Unipolar Code Table Range)
Latch Contents 1111 1111 1111
Analog Output, VOUT VREF VREF VREF VREF VREF
4095 4096 2049 4096 2048 +VREF 4096
2047 4096
1000
0000
0001
1000
0000
0000
0111
1111
1111
0000 0000
0000 0000
0001 0000
4096
NOTE:
VREF(2-12) VREF 2048
High State, State
-10-
REV.
AD7245A/AD7248A
UNIPOLAR CONFIGURATION
output voltage range achieved tying ROFS, VOUT together. this output range AD7245A/ AD7248A operated single supply (VSS dual supply. table output voltage versus digital code Table III, with VREF replaced VREF. Note that this range VREF(2-12) VREF
BIPOLAR CONFIGURATION
4096
this case care must taken ensure that maximum output voltage greater than VDD-VOUT overhead must greater than ensure correct operation part. Note that AD7245A/AD7248A must referenced DGND (system GND). entire circuit operated single supply with AD7245A/AD7248A connected system GND.
bipolar configuration AD7245A/AD7248A, which gives output voltage range from achieved connecting ROFS input connecting VOUT. AD7245A/AD7248A must operated from dual supplies achieve this output voltage range. code table bipolar operation shown Table
Table Bipolar Code Table
ROFS
AGND VBIAS
VREF
VOUT
Latch Contents 1111 1111 1111
AD7245A/AD7248A*
AD589 DGND
Analog Output, VOUT +VREF 2048
+VREF 2048 2047
*DIGITAL CIRCUITRY OMITTED CLARITY.
SYSTEM
Figure AGND Bias Circuit
PROGRAMMABLE CURRENT SINK
1000 1000 0111
0000 0000 1111
0001 0000 1111
-VREF 2048 -VREF 2048 -VREF -VREF 2048 VREF
2048
0000
0000
0001
2047 2048
Figure shows AD7245A/AD7248A configured with power MOSFET transistor, VN0300M, provide programmable current sink from VSOURCE. VN0300M placed feedback AD7245A/ AD7248A amplifier. entire circuit operated single supply tying AD7245A/AD7248A AGND. sink current, ISINK, expressed ISINK
0000
0000
0000
VSOURCE
NOTE: VREF(2
AGND BIAS
ROFS
LOAD
AD7245A/AD7248A AGND biased above system (AD7245A/AD7248A DGND) provide offset "zero" analog output voltage level. With unity gain amplifier (ROFS VOUT output voltage, VOUT expressed VOUT VBIAS VREF where fractional representation digital word latch VBIAS voltage applied AD7245A/ AD7248A AGND pin. Because current flowing AGND varies with digital code, AGND should driven from impedance source. circuit configuration outlined AGND bias Figure using AD589, +1.23 bandgap reference. gain used buffer amplifier output voltage, VOUT expressed VOUT 2(VBIAS VREF)
ISINK
VN0300M VREF VOUT
AD7245A/AD7248A*
*DIGITAL CIRCUITRY OMITTED CLARITY. DGND AGND
Figure Programmable Current Sink
Using VN0300M, voltage drop across load typically large VSOURCE with VOUT Therefore, current flowing (with register) maximum load with VSOURCE VN0300M actually handle currents still function correctly circuit, practice circuit must used with larger values VSOURCE otherwise requires very small load. -11-
REV.
AD7245A/AD7248A
Since tolerance value reference voltage AD7245A/ AD7248A 0.2%, then absolute value ISINK vary 0.2% from device device fixed value Because input bias current AD7245A/AD7248A's only order picoamps, effect sink current negligible. Tying ROFS input input reduces this effect even further prevents noise pickup which could occur ROFS left unconnected. circuit Figure modified provide programmable current source AGND -VSINK (for -VSINK, dual supplies required AD7245A/AD7248A). AD7245A/AD7248A configured before. current through mirrored with current mirror circuit provide programmable source current (see CMOS Application Guide, Publication G872-30-10/84, suitable current mirror circuit). before absolute value source current will affected ±0.2% tolerance VREF. this case performance current mirror will also affect value source current.
FUNCTION GENERATOR WITH PROGRAMMABLE FREQUENCY
Adjusting triwave applied AD639 adjust distortion performance sine wave output, configuration shown). Amplitude, offset symmetry triwave affect distortion. adjusting these, VR2, output sine wave with harmonic distortion better than achieved intermediate frequencies. Using capacitor value shown Figure (i.e., output frequency range over digital input code range. step size frequency increments accuracy output frequency limited bits AD537, guaranteed monotonic bits.
MICROPROCESSOR INTERFACING-AD7245
AD7245A-8086 INTERFACE
Figure shows 8086 16-bit processor interfacing AD7245A. setup shown Figure double buffering feature used LDAC input tied LOW. AD0-AD11 16-bit data connected AD7245A data (DB0-DB11). 12-bit word written AD7245A instruction analog output responds immediately. this example address D000. software routine Figure given Table
Figure shows AD7245A/AD7248A with AD537, voltage-to-frequency converter AD639, trigonometric function generator provide complete function generator with programmable frequency. circuit provides square wave, triwave sine wave outputs, each output amplitude. AD7245A/AD7248A provides programmable voltage AD537 input. Since both AD7245A/AD7248A AD537 guaranteed monotonic, output frequency will always increase with increasing digital code. AD537 provides square wave output which conditioned amplifier AD537 also provides differential triwave output. This conditioned amplifiers provide ±1.8 triwave required input AD639. triwave further scaled amplifier provide output.
+15V SQUARE WAVE +15V
ADDRESS 8086 16-BIT LATCH ADDRESS DECODE LDAC
AD7245A*
DB11
AD15
ADDRESS/DATA *LINEAR CIRCUITRY OMITTED CLARITY
Figure AD7245A 8086 Interface
+15V +15V 4.7k 5.6k
4.12k 3.9k 3.9k 4.12k +15V SINE WAVE WAVE
AD7245A/ AD7248A
VOUT ROFS DGND AGND
AD537
680pF
AD712
AD639
-15V -15V
Figure Programmable Function Generator
-12-
REV.
AD7245A/AD7248A
Table Sample Program Loading AD7245A from 8086
ASSUME DACLOAD, DACLOAD DACLOAD SEGMENT 8CC9 8ED9 BF00D0 0MOV #D000 DEFINE DATA SEGMENT REGISTER EQUAL CODE SEGMENT REGISTER LOAD WITH D000
MC68000 DTACK
ADDRESS
ADDRESS DECODE
LDAC
AD7245A*
DB11
C705 MEM, LOADED WITH WXYZ "YZWX" #YZWX EA00 CONTROL RETURNED MONITOR PROGRAM 01000
D0-D15
DATA *LINEAR CIRCUITRY OMITTED CLARITY
Figure AD7245A MC68000 Interface
Table Sample Routine Loading AD7245A from 68000
multiple system double buffering AD7245A allows user simultaneously update DACs. Figure 12-bit word loaded input latches each DACs sequence. Then, with instruction appropriate address, (i.e., LDAC) brought LOW, updating DACs simultaneously.
ADDRESS 8086 16-BIT LATCH AD15 DATA ADDRESS DECODE
MOVE.W
#X,D0
desired data, loaded into Data Register value between 4094 (decimal) OFFF (hexadecimal). Data transferred between Latch. Control returned System Monitor Program using these instructions.
MOVE.W
LDAC DB11
D0,$E000
AD7245A*
MOVE.B
#228,D7
TRAP
AD7245A*
LDAC DB11
MICROPROCESSOR INTERFACE-AD7248A
LDAC DB11
AD7245A*
*LINEAR CIRCUITRY OMITTED CLARITY
Figure AD7245A 8086 Multiple Interface
AD7245A-MC68000 INTERFACE
Figure shows connection diagram interfacing AD7248A both 8085A 8088 microprocessors. This scheme also suited microprocessor, address/data does have demultiplexed. Data loaded AD7248A right justified. AD7248A memory mapped with separate memory address input latch high byte, input latch byte latch. Data first written AD7248A input latch write operations. Either high byte byte data written first AD7248A input latch. write AD7248A latch address transfers input latch data latch updates output voltage. Alternatively, LDAC input asynchronous common number AD7248As simultaneous updating number voltage channels.
A8-A15 OCTAL LATCH ADDRESS CSLSB CSMSB LDAC
Interfacing between MC68000 AD7245A accomplished using circuit Figure Once again AD7245A used single buffered mode. software routine loading data AD7245A given Table this example AD7245A located address E000, 12-bit word written MOVE instruction.
8085A/8088
ADDRESS DECODE
AD7248A*
DB0-DB7
AD0-AD7
ADDRESS/DATA *LINEAR CIRCUITRY OMITTED CLARITY.
Figure AD7248A 8085A/8088 Interface
REV.
-13-
AD7245A/AD7248A
connection diagram interface between AD7248A 68008 microprocessor shown Figure Once again AD7248A acts memory mapped device data right justified. this case AD7248A configured automatic transfer mode which means that high byte input latch same address latch. Data written AD7248A first writing data AD7248A byte. Writing data high byte input latch also transfers input latch contents latch updates output. Figure shows connection diagram between AD7248A 8051 microprocessor. AD7248A port mapped this interface configured automatic transfer mode. Data loaded input latch byte output Port Output Line P3.0, which connected CSLSB AD7248A, pulsed load data into byte input latch. Pulsing P3.1 line, after high byte data been Port updates output AD7248A. input AD7248A hardwired this application because spurious address strobes CSLSB CSMSB occur.
P3.0
ADDRESS DECODE CSLSB CSMSB LDAC
A0-A19
ADDRESS
CSLSB CSMSB LDAC
P3.1
68008
DTACK
8051
P1.0 P1.1
AD7248A*
AD7248A*
DB0-DB7
P1.2 P1.3
D0-D7
DATA *LINEAR CIRCUITRY OMITTED CLARITY
P1.4 P1.5 P1.6 P1.7
Figure AD7248A 68008 Interface
interface circuit connections 6502 6809 microprocessors shown Figure Once again, AD7248A memory mapped data right justified. procedure writing data AD7248A outlined 8085A/8088. 6502 microprocessor clock used generate while 6809 signal used.
*ADDITIONAL PINS OMITTED CLARITY.
Figure AD7248A MCS-51 Interface
A0-A15
ADDRESS CSLSB CSMSB LDAC
ADDRESS DECODE
6502/6809
AD7248A*
DB0-DB7
D0-D7
DATA *LINEAR CIRCUITRY OMITTED CLARITY.
Figure AD7248A 6502/6809 Interface
-14-
REV.
AD7245A/AD7248A
MECHANICAL INFORMATION-AD7245A OUTLINE DIMENSIONS
Dimensions shown inches (mm).
24-Lead Plastic (N-24)
1.228 (31.19) 1.126 (31.14)
0.260 (6.61
0.001 0.03) 0.32 (8.128) 0.30 (7.62) 0.130 (3.30) 0.128 (3.25) 0.015 (0.381) 0.008 (0.204)
0.11 (2.79) 0.09 (2.28) 0.060 (1.52) 0.015 (0.38)
0.02 (0.5) 0.09 (2.28)
0.07 (1.78) 0.05 (1.27)
SEATING PLANE
LEAD IDENTIFIED NOTCH. PLASTIC LEADS WILL EITHER SOLDER DIPPED LEAD PLATED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
24-Lead SOIC (R-24)
0.614 (15.6) 0.598 (15.2)
24-Lead Cerdip (Q-24)
0.295 (7.493)
0.299 (7.6) 0.291 (7.4)
0.070 (1.78) 0.030 (0.76) 1.290 (32.77)
0.419 (10.65) 0.394 (10.00)
0.320 (8.128) 0.290 (7.366)
0.104 (2.65) 0.093 (2.35)
0.012 (0.30) 0.050 0.004 (0.10) (1.27)
0.019 (0.49) 0.014 (0.35)
SEATING 0.013 (0.32) PLANE 0.009 (0.23)
0.005 (0.13) 0.016 (0.40)
0.180 0.225 (4.572) (5.715) SEATING PLANE 0.125 0.070 (1.778) (3.175) 0.012 (0.305) 0.021 (0.533) 0.110 (2.794) 0.020 (0.508) 0.008 (0.203) 0.090 (2.286) 0.015 (0.381) LEAD IDENTIFIED NOTCH. CERDIP LEADS WILL EITHER PLATED SOLDER DIPPED ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
28-Terminal Leadless Ceramic Chip Carrier (E-28A)
0.100 (2.54)1 0.064 (1.63) 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) 0.075 (1.91) 0.088 (2.24) 0.054 (1.37)
28-Terminal Plastic Leaded Chip Carrier (P-28A)
0.032 (0.812) 0.026 (0.661) 0.180 (4.51) 0.165 (4.20)
0.075 (1.91)
0.300 (7.62)2 0.150 (3.51)
0.458 (11.63) 0.442 (11.23) 0.458 (11.63)
0.028 (0.71) 0.022 (0.56) 0.050 (1.27)
IDENTIFIER
0.021 (0.533) 0.013 (0.331) 0.050 (1.27 0.430 (10.5) 0.005 0.390 (9.9) 0.13)
BOTTOM VIEW
VIEW
(PINS DOWN)
0.055 (1.40) 0.045 (1.14)
0.200 (5.08)
NOTES 1THIS DIMENSION CONTROLS OVERALL PACKAGE THICKNESS. 2APPLIES FOUR SIDES. TERMINALS GOLD PLATED
0.456 (11.58) 0.450 (11.43) 0.495 (12.57) 0.485 (12.32)
0.110 (2.79) 0.085 (2.16)
REV.
-15-
AD7245A/AD7248A
MECHANICAL INFORMATION -AD7248A OUTLINE DIMENSIONS
Dimensions shown inches (mm).
1.07 (27.18)
0.11 (2.79) 0.09 (2.28)
0.255 (6.477) 0.245 (6.223) 0.32 (8.128) 0.29 (7.366) 0.145 (3.683) 0.18 (4.57) 0.125 (3.18)
0.310 (7.87) 0.220 (5.59) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81)
0.021 (0.533) 0.015 (0.381)
0.20 (5.0) 0.14 (3.18) 0.15 (3.8) 0.125 (3.18)
0.97 (24.64) 0.935 (23.75)
0.125 (3.175)
0.011 (0.28) 0.009 (0.23) LEAD IDENTIFIED NOTCH. LEADS SOLDER TIN-PLATED KOVAR ALLOY 0.021 (0.533) 0.015 (0.381) 0.070 (1.77) 0.045 (1.15)
0.02 (0.5) 0.016 (0.41)
0.070 (1.78) 0.030 (0.76)
SEATING PLANE
0.015 (0.38) 0.008 (0.20)
LEAD IDENTIFIED NOTCH. LEADS SOLDER TIN-PLATED KOVAR ALLOY
20-Lead SOIC (R-20)
0.5118 (13.00) 0.4961 (12.60)
20-Terminal Plastic Leaded Chip Carrier (P-20A)
0.105 (2.665 0.045 (1.143 0.003 0.076)
0.299 (7.60) 0.291 (7.40)
0.015 0.375)
0.173 (4.385
0.008 0.185) 0.020 (0.51)
0.419 (10.65) 0.404 (10.00)
IDENTIFIER
VIEW
(PINS DOWN)
0.050 (1.27)
0.017 (0.432 0.029 (0.737
0.004 0.101) 0.003 0.076)
0.0500 (1.27)
0.107 (2.72) 0.089 (2.26)
0.020 (0.51)
0.390 (9.905
0.005 0.125)
0.025 (0.64) 0.105 (2.665 0.015 0.375)
0.011 (0.275) 0.005 (0.125)
0.022 (0.56) 0.014 (0.36)
SEATING PLANE
0.015 (0.38) 0.007 (0.18)
0.034 (0.86) 0.018 (0.46)
Revision History
Location Page
PRINTED U.S.A.
Data Sheet changed from REV. REV. Changed Static Performance section Test Conditions/Comments column Changed Version Full-Scale Temperature Coefficient from Changed Versions Power Requirements from +11.4/+15.75 +10.8/+16.5 min. Changed Versions Power Requirements from -11.4/-15.75 -10.8/-16.5 Change Note Note Specifications table Change Note Switching Characteristics Changes R-24 Package Outline
-16-
REV.
C00996-0-3/01
20-Lead Plastic (N-20)
20-Lead Cerdip (Q-20)

LC2MOS 12-Bit DACPORTs AD7245A/AD7248A AD7245A FUNCTIONAL BLOCK D

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