Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel O

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Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel O

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19-2094; 7/01
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
MAX1182 +3V, dual 10-bit analog-to-digital converter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving pipelined, 9stage ADCs. MAX1182 optimized low-power, high-dynamic performance applications imaging, instrumentation digital communication applications. This operates from single +2.7V +3.6V supply, consuming only 195mW while delivering typical signal-to-noise ratio (SNR) 59dB input frequency 20MHz sampling rate 65Msps. driven input stages incorporate 400MHz (-3dB) input amplifiers. converters also operated with single-ended inputs. addition operating power, MAX1182 features 2.8mA sleep mode well power-down mode conserve power during idle periods. internal +2.048V precision bandgap reference sets full-scale range ADC. flexible reference structure allows internal externally derived reference, desired applications requiring increased accuracy different input voltage range. MAX1182 features parallel, CMOS-compatible three-state outputs. digital output format two's complement straight offset binary through single control pin. device provides separate output power supply +1.7V +3.6V flexible interfacing. MAX1182 available 7mm, 48pin TQFP package, specified extended industrial (-40°C +85°C) temperature range. Pin-compatible higher lower speed versions MAX1182 also available. Please refer MAX1180 datasheet 105Msps, MAX1181 datasheet 80Msps, MAX1183 datasheet 40Msps, MAX1184 datasheet 20Msps. addition these speed grades, this family includes 20Msps multiplexed output version (MAX1185), which digital data presented time-interleaved single, parallel 10-bit output port.
Features
Single Operation Excellent Dynamic Performance: 59dB 20MHz 77dB SFDR 20MHz Power: 65mA (Normal Operation) 2.8mA (Sleep Mode) (Shutdown Mode) 0.02dB Gain 0.25° Phase Matching (typ) Wide ±1VP-P Differential Analog Input Voltage Range 400MHz -3dB Input Bandwidth On-Chip +2.048V Precision Bandgap Reference User-Selectable Output Format-Two's Complement Offset Binary 48-Pin TQFP Package with Exposed Improved Thermal Dissipation Evaluation Available
MAX1182
Ordering Information
PART MAX1182ECM TEMP. RANGE -40°C +85°C PIN-PACKAGE TQFP-EP
Configuration
REFOUT REFP REFIN REFN
INA+ INAVDD INBINB+
OGND OVDD OVDD OGND
Applications
High Resolution Imaging Channel Digitization Multchannel Undersampling Instrumentation Video Application
MAX1182
SLEEP
TQFP-EP
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD GND.-0.3V +3.6V OGND GND.-0.3V +0.3V INA+, INA-, INB+, INB- .-0.3V REFIN, REFOUT, REFP, REFN, CLK, .-0.3V (VDD 0.3V) SLEEP, T/B, D9A-D0A, D9B-D0B OGND .-0.3V (OVDD 0.3V) Continuous Power Dissipation +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C).1000mW Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-60°C +150°C Lead temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD +3V, OVDD +2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2Vp-p (differential w.r.t. COM), 10pF digital outputs (Note fCLK 65MHz (50% duty cycle), TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK 65MHz, 4096-point FFT) fINA 7.47MHz, +25°C Signal-to-Noise Ratio fINA 20MHz, +25°C fINA 39.9MHz (Note Signal-to-Noise Distortion harmonic) fINA 7.47MHz, +25°C SINAD fINA 20MHz, +25°C fINA 39.9MHz (Note fINA 7.47MHz, +25°C Spurious-Free Dynamic Range SFDR fINA 20MHz, +25°C fINA 39.9MHz, (Note 56.5 56.8 56.5 59.5 58.5 58.5 fCLK Clock Cycles VDIFF Switched capacitor load Differential single-ended inputs ±1.0 VDD/2 7.47MHz 7.47MHz, missing codes guaranteed ±0.6 ±0.4 ±1.9 ±1.0 ±1.7 Bits SYMBOL CONDITIONS UNITS
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3V, OVDD +2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2Vp-p (differential w.r.t. COM), 10pF digital outputs (Note fCLK 65MHz (50% duty cycle), TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Third-Harmonic Distortion Intermodulation Distortion (first odd-order IMDs) Total Harmonic Distortion (first harmonics) Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN +2.048V) REFIN Input Voltage Positive Reference Output Voltage Negative Reference Output Voltage Differential Reference Output Voltage Range REFIN Resistance VREFIN VREFP VREFN VREF RREFIN VREF VREFP VREFN 0.98 2.048 2.012 0.988 1.024 1.07 REFOUT TCREF 2.048 1.25 ppm/°C mV/mA INA+ INA- INB+ INB- FPBW full-scale input SYMBOL CONDITIONS fINA 7.47MHz fINA 20MHz fINA 39.9MHz (Note fINA 19.13042MHz -6.5dB fINA 21.2886MHz -6.5dB (Note fINA 7.47MHz, +25°C fINA 20MHz, +25°C fINA 39.9MHz, (Note Input -20dB differential inputs Input -0.5dB differential inputs -75.5 ±0.25 psRMS degrees LSBRMS UNITS
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3V, OVDD +2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2Vp-p (differential w.r.t. COM), 10pF digital outputs (Note fCLK 65MHz (50% duty cycle), TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Maximum REFP, Source Current Maximum REFP, Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL ISOURCE ISINK ISOURCE ISINK RREFP, RREFN VREF VCOM VREFP VREFN Measured between REFP COM, REFN VREF VREFP VREFN CONDITIONS UNITS
UNBUFFERED EXTERNAL REFERENCE (VREFIN AGND, reference voltage applied REFP, REFN, COM) REFP, REFN Input Resistance Differential Reference Input Voltage Input Voltage REFP Input Voltage REFN Input Voltage 1.024 ±10% VDD/2 VCOM VREF VCOM VREF SLEEP, SLEEP, OVDD (CLK) ISINK 200µA ISOURCE 200µA OVDD OVDD OVDD OVDD OVDD
DIGITAL INPUTS (CLK, SLEEP, T/B) Input High Threshold Input Threshold Input Hysteresis Input Leakage Input Capacitance VHYST
DIGITAL OUTPUTS (D9A-D0A, D9B-D0B) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance ILEAK COUT
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3V, OVDD +2.5V; 0.1µF 1.0µF capacitors from REFP, REFN, GND; REFOUT connected REFIN through resistor, 2Vp-p (differential w.r.t. COM), 10pF digital outputs (Note fCLK 65MHz (50% duty cycle), TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER POWER REQUIREMENTS Analog Supply Voltage Range Output Supply Voltage Range Analog Supply Current OVDD Operating, fINA 20MHz -0.5dB IVDD Sleep mode Shutdown, clock idle, OVDD Operating, 15pF, fINA 20MHz -0.5dB Output Supply Current IOVDD Sleep mode Shutdown, clock idle, OVDD Operating, fINA 20MHz -0.5dB Power Dissipation PDISS Sleep mode Shutdown, clock idle, OVDD Power-Supply Rejection Ratio TIMING CHARACTERISTICS Rise Output Data Valid Output Enable Time Output Disable Time Pulse Width High Pulse Width Wake-Up Time tENABLE tDISABLE tWAKE Figure (Note Figure Figure Figure clock period: 15.4ns Figure clock period: 15.4ns Wakeup from Sleep mode (Note Wakeup from Shutdown (Note fINA 20MHz -0.5dB fINA 20MHz -0.5dB fINA 20MHz -0.5dB 0.42 0.02 0.25 ±0.2 PSRR Offset Gain ±0.2 ±0.1 mV/V SYMBOL CONDITIONS UNITS
CHANNEL-TO-CHANNEL MATCHING Crosstalk Gain Matching Phase Matching degrees
Note SNR, SINAD, THD, SFDR, based analog input voltage -0.5dB referenced +1.024V full-scale input voltage range. Note Intermodulation distortion total power intermodulation products relative individual carrier. This number better, referenced two-tone envelope. Note Digital outputs settle VIH, VIL. Parameter guaranteed design. Note With REFIN driven externally, REFP, COM, REFN left floating while powered down. Note Equivalent dynamic performance obtainable over full OVDD range with reduced
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
Typical Operating Characteristics
(VDD +3V, OVDD +2.5V, internal reference, differential input -0.5dB fCLK 65MHz, 10pF, +25°C, unless otherwise noted.)
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1182 toc01
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 fINA 6.0065MHz fINB 7.51410MHz fCLK 65.00057MHz AINB -0.56dB
MAX1182 toc02
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 fINA 20.08257MHz fINB 25.09727MHz fCLK 65.00057MHz AINB -0.52dB
MAX1182 toc03
AMPLITUDE (dB) -100 fINA 6.0065MHz fINB 7.51410MHz fCLK 65.00057MHz AINA -0.55dB
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1182 toc04
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1182 toc05
PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 fINA 37.31661MHz fINB 46.99687MHz fCLK 65.00057MHz AINB -0.49dB
MAX1182 toc06
AMPLITUDE (dB) -100 fINA 20.08257MHz fINB 25.09727MHz fCLK 65.00057MHz AINB -0.52dB
AMPLITUDE (dB) -100 fINA 37.31661MHz fINB 46.99687MHz fCLK 65.00057MHz AINB -0.52dB
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT)
MAX1182 toc07
SIGNAL-TO-NOISE RATIO ANALOG INPUT FREQUENCY
MAX1182 toc08
SIGNAL-TO-NOISE DISTORTION ANALOG INPUT FREQUENCY
DIFFERENTIAL INPUT CONFIGURATION
MAX1182 toc09
AMPLITUDE (dB) -100 ORDER fIN1 19.13042MHz fIN2 21.28864MHz fCLK 65.00057MHz -6.5dB TWO-TONE ENVELOPE -0.47dB fIN1
(dB)
DIFFERENTIAL INPUT CONFIGURATION
fIN2 ORDER
SINAD (dB)
ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
Typical Operating Characteristics (continued)
(VDD +3V, OVDD +2.5V, internal reference, differential input -0.5dB fCLK 65MHz, 10pF, +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION ANALOG INPUT FREQUENCY
MAX1182 toc10
MAX1182
SPURIOUS-FREE DYNAMIC RANGE ANALOG INPUT FREQUENCY
DIFFERENTIAL INPUT CONFIGURATION
MAX1182 toc11
FULL-POWER INPUT BANDWIDTH ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1182 toc12
DIFFERENTIAL INPUT CONFIGURATION
SFDR (dB)
GAIN (dB)
(dB)
ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)
1000
ANALOG INPUT FREQUENCY (MHz)
SMALL-SIGNAL INPUT BANDWIDTH ANALOG INPUT FREQUENCY, SINGLE-ENDED
MAX1182 toc13
SIGNAL-TO-NOISE RATIO INPUT POWER (fIN 20.085279MHz)
MAX1182 toc14
SIGNAL-TO-NOISE DISTORTION INPUT POWER (fIN 20.085279MHz)
MAX1182 toc15
100mVP-P GAIN (dB)
SINAD (dB)
(dB)
1000
ANALOG INPUT FREQUENCY (MHz)
INPUT POWER
INPUT POWER
TOTAL HARMONIC DISTORTION INPUT POWER (fIN 20.085279MHz)
MAX1182 toc16
SPURIOUS-FREE DYNAMIC RANGE INPUT POWER (fIN 20.085279MHz)
MAX1182 toc17
INTEGRAL NONLINEARITY (BEST-ENDPOINT FIT)
MAX1182 toc18
(LSB)
SFDR (dB)
(dB)
-0.5
INPUT POWER
INPUT POWER
-1.0 1024 DIGITAL OUTPUT CODE
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
Typical Operating Characteristics (continued)
(VDD +3V, OVDD +2.5V, internal reference, differential input -0.5dB fCLK 65MHz, 10pF, +25°C, unless otherwise noted.)
GAIN ERROR TEMPERATURE, EXTERNAL REFERENCE (VREFIN +2.048V)
MAX1182 toc19 MAX1182 toc20
DIFFERENTIAL NONLINEARITY
(LSB) -0.1 -0.2 -0.3 -0.4 -0.5 1024 DIGITAL OUTPUT CODE
OFFSET ERROR TEMPERATURE, EXTERNAL REFERENCE (VREFIN +2.048V)
MAX1182 toc21
0.15 0.10 OFFSET ERROR 0.05 -0.05 -0.10 -0.15
GAIN ERROR -0.5 -1.0 -1.5 -2.0 -2.5 -3.0
TEMPERATURE (°C)
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT ANALOG SUPPLY VOLTAGE
MAX1182 toc22
ANALOG SUPPLY CURRENT TEMPERATURE
MAX1182 toc23
ANALOG POWER-DOWN CURRENT ANALOG POWER SUPPLY
OVDD 0.24
MAX1182 toc24
0.30
IVDD (mA) IVDD (mA)
IVDD (µA)
0.18
0.12
0.06
2.70 2.85 3.00 3.15 3.30 3.45 3.60
TEMPERATURE (°C)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
SFDR, SNR, THD, SINAD CLOCK DUTY CYCLE
25.097265MHz SFDR, SNR, THD, SINAD (dB) SFDR
MAX1182 toc25
INTERNAL REFERENCE VOLTAGE ANALOG POWER VOLTAGE
MAX1182 toc26
2.045
2.040 VREFOUT
SINAD
2.035
2.030
2.025
CLOCK DUTY CYCLE
2.020 2.70 2.85 3.00 3.15 3.30 3.45 3.60
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
Typical Operating Characteristics (continued)
(VDD +3V, OVDD +2.5V, internal reference, differential input -0.5dB fCLK 65MHz, 10pF, +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE TEMPERATURE
MAX1182 toc27
MAX1182
OUTPUT NOISE HISTOGRAM INPUT)
140000 120000
MAX1182 toc28
2.06 2.05 2.04
160000 129421
VREFOUT
COUNTS
100000 80000 60000 40000
2.03 2.02 2.01 2.00 TEMPERATURE (°C)
20000
DIGITAL OUTPUT CODE
Description
NAME INA+ INAINBINB+ FUNCTION Common-Mode Voltage Input/Output. Bypass with 0.1µF capacitor. Analog Supply Voltage. Bypass with capacitor combination 2.2µF parallel with 0.1µF. Analog Ground Channel Positive Analog Input. single-ended operation, connect signal source INA+. Channel Negative Analog Input. single-ended operation, connect INA- COM. Channel Negative Analog Input. single-ended operation, connect INB- COM. Channel Positive Analog Input. single-ended operation, connect signal source INB+. Converter Clock Input selects digital output format. High: Two's complement. Low: Straight offset binary. Sleep Mode Input. High: Deactivates ADCs, leaves reference bias circuit active. Low: Normal operation. Power-Down Input. High: Power-down mode Low: Normal operation Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled
SLEEP
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
Description (continued)
NAME OGND OVDD REFOUT REFIN REFP REFN FUNCTION Three-State Digital Output, (MSB), Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, (LSB), Channel Output Driver Ground Output Driver Supply Voltage. Bypass OGND with capacitor combination 2.2µF parallel with 0.1µF. Three-State Digital Output, (LSB), Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, Channel Three-State Digital Output, (MSB), Channel Internal Reference Voltage Output. connected REFIN through resistor resistor divider. Reference Input. VREFIN (VREFP VREFN). Bypass with >1nF capacitor. Positive Reference Input/Output. Conversion range (VREFP VREFN). Bypass with 0.1µF capacitor. Negative Reference Input/Output. Conversion range (VREFP VREFN). Bypass with 0.1µF capacitor.
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
Detailed Description
MAX1182 uses 9-stage, fully-differential pipelined architecture (Figure that allows highspeed conversion while minimizing power consumption. Samples taken inputs move progressively through pipeline stages every half clock cycle. Counting delay through output latch, clockcycle latency five clock cycles. 1.5-bit (2-comparator) flash ADCs convert heldinput voltages into digital code. digital-to-analog converters (DACs) convert digitized results back into analog voltages, which then subtracted from original held input signals. resulting error signals then multiplied residues passed along next pipeline stages where process repeated until signals have been processed nine stages. Digital error correction compensates comparator offsets each these pipeline stages ensures missing codes. hold mode. track mode, switches S2a, S2b, S4a, S4b, closed. fully-differential circuits sample input signals onto capacitors (C2a C2b) through switches S4b. common mode amplifier input, open simultaneously with sampling input waveform. Switches then opened before switches S3b, connect capacitors output amplifier, switch closed. resulting differential voltages held capacitors C2b. amplifiers used charge capacitors same values originally held C2b. These values then presented first-stage quantizers isolate pipelines from fast-changing inputs. wide input bandwidth amplifiers allow MAX1182 trackand-sample/hold analog inputs high frequencies Nyquist). inputs (INA+, INB+, INA-, INB-) driven either differentially single-ended. Match impedance INA+ INA- well INB+ INB- common-mode voltage mid-supply (VDD/2) optimum performance.
MAX1182
Input Track-and-Hold (T/H) Circuits
Figure displays simplified functional diagram input track-and-hold (T/H) circuits both track
VOUT
VOUT
FLASH BITS
FLASH BITS
2-BIT FLASH STAGE STAGE STAGE STAGE STAGE STAGE STAGE
2-BIT FLASH STAGE
DIGITAL CORRECTION LOGIC D9A-D0A
DIGITAL CORRECTION LOGIC D9B-D0B
VINA
VINB
VINA INPUT VOLTAGE BETWEEN INA+ INA- (DIFFERENTIAL SINGLE-ENDED) VINB INPUT VOLTAGE BETWEEN INB+ INB- (DIFFERENTIAL SINGLE-ENDED)
Figure Pipelined Architecture-Stage Blocks
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
INTERNAL BIAS INA+ INTERNAL BIAS HOLD INTERNAL BIAS INB+ INTERNAL BIAS TRACK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS
INA-
INB-
MAX1182
Figure MAX1182 Amplifiers
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
Analog Inputs Reference Configurations
full-scale range MAX1182 determined internally generated voltage difference between REFP (VDD/2 VREFIN/4) REFN (VDD/2 VREFIN/4). full-scale range both on-chip ADCs adjustable through REFIN pin, which provided this purpose. REFOUT, REFP, (VDD/2), REFN internally buffered low-impedance outputs. MAX1182 provides three modes reference operation: Internal reference mode Buffered external reference mode Unbuffered external reference mode internal reference mode, connect internal reference output REFOUT REFIN through resistor (e.g., 10k) resistor divider, application requires reduced full-scale range. stability noise filtering purposes bypass REFIN with >10nF capacitor GND. internal reference mode, REFOUT, COM, REFP, REFN become low-impedance outputs. buffered external reference mode, adjust reference voltage levels externally applying stable accurate voltage REFIN. this mode, COM, REFP, REFN become outputs. REFOUT left open connected REFIN through >10k resistor. unbuffered external reference mode, connect REFIN GND. This deactivates on-chip reference buffers REFP, COM, REFN. With their buffers shut down, these nodes become high impedance driven through separate external reference sources. ered analog input routed away from analog input other digital signal lines. MAX1182 clock input operates with voltage threshold VDD/2. Clock inputs with duty cycle other than 50%, must meet specifications high periods stated Electrical Characteristics.
MAX1182
System Timing Requirements
Figure depicts relationship between clock input, analog input, data output. MAX1182 samples rising edge input clock. Output data channels valid next rising edge input clock. output data internal latency five clock cycles. Figure also determines relationship between input clock parameters valid output data channels
Digital Output Data, Output Data Format Selection (T/B), Output Enable (/OE)
digital outputs, D0A-D9A (Channel D0B-D9B (Channel TTL/CMOS logic-compatible. There 5-clock-cycle latency between particular sample corresponding output data. output coding chosen either straight offset binary two's complement (Table controlled single (T/B). Pull select offset binary high activate two's complement output coding. capacitive load digital outputs D0A-D9A D0B-D9B should kept possible (<15pF), avoid large digital currents that could feed back into analog portion MAX1182, thereby degrading dynamic performance. Using buffers digital outputs ADCs further isolate digital outputs from heavy capacitive loads. further improve dynamic performance MAX1182 small-series resistors (e.g., 100) maybe added digital output paths, close MAX1182. Figure displays timing relationship between output enable data output valid well power down/wake-up data output valid.
Clock Input (CLK)
MAX1182's input accepts CMOS-compatible clock signals. Since interstage conversion device depends repeatability rising falling edges external clock, clock with jitter fast rise fall times 2ns). particular, sampling occurs rising edge clock signal, requiring this edge provide lowest possible jitter. significant aperture jitter would limit performance on-chip ADCs follows: SNRdB log10 tAJ]), where represents analog input frequency time aperture jitter. Clock jitter especially critical undersampling applications. clock input should always consid-
Power-Down (PD) Sleep (SLEEP) Modes
MAX1182 offers power-save modes-sleep full power-down mode. sleep mode (SLEEP only reference bias circuit active (both ADCs disabled), current consumption reduced 2.8mA. enter full power-down mode, pull high. With simultaneously low, outputs latched last value prior power down. Pulling high forces digital outputs into high impedance state.
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT DATA OUTPUT D9A-D0A
DATA OUTPUT D9B-D0B
Figure System Timing Diagram
tENABLE OUTPUT D9A-D0A HIGH-Z
tDISABLE HIGH-Z
amplifiers. user select RISO values optimize filter performance, suit particular application. application Figure RISO placed before capacitive load prevent ringing oscillation. 22pF capacitor acts small bypassing capacitor.
VALID DATA
Using Transformer Coupling
transformer (Figure provides excellent solution convert single-ended source signal fully differential signal, required MAX1182 optimum performance. Connecting center transformer provides VDD/2 level shift input. Although transformer shown, stepup transformer selected reduce drive requirements. reduced signal swing from input driver, such amp, also improve overall distortion. general, MAX1182 provides better SFDR with fully-differential input signals than singleended drive, especially very high input frequencies. differential input mode, even-order harmonics lower both inputs (INA+, INA- and/or INB+, INB-) balanced, each inputs only requires half signal swing compared single-ended mode.
OUTPUT D9B-D0B
HIGH-Z
VALID DATA
HIGH-Z
Figure Output Timing Diagram
Applications Information
Figure depicts typical application circuit containing single-ended differential converters. internal reference provides DD/2 output voltage level shifting purposes. input buffered then split voltage follower inverter. lowpass filter suppresses some wideband noise associated with high-speed operational amplifiers, follows
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
Table MAX1182 Output Codes Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF 511/512 VREF 1/512 VREF 1/512 -VREF 511/512 -VREF 512/512 *VREF VREFP VREFN DIFFERENTIAL INPUT +FULL SCALE 1LSB Bipolar Zero FULL SCALE FULL SCALE STRAIGHT OFFSET BINARY 1111 1111 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000 TWO'S COMPLEMENT 1111 1111 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000
Single-Ended AC-Coupled Input Signal
Figure shows AC-coupled, single-ended application. Amplifiers like MAX4108 provide high-speed, high-bandwidth, noise, distortion maintain integrity input signal.
Grounding, Bypassing, Board Layout
MAX1182 requires high-speed board layout design techniques. Locate bypass capacitors close device possible, preferably same side ADC, using surface-mount devices minimum inductance. Bypass VDD, REFP, REFN, with parallel 0.1µF ceramic capacitors 2.2µF bipolar capacitor GND. Follow same rules bypass digital supply (OVDD) OGND. Multilayer boards with separated ground power planes produce highest level signal integrity. Consider split ground plane arranged match physical location analog ground (GND) digital output driver ground (OGND) ADCs package. ground planes should joined single point such that noisy digital ground currents interfere with analog ground plane. ideal location this connection determined experimentally point along between ground planes, which produces optimum results. Make this connection with low-value, surface-mount resistor ferrite bead direct short. Alternatively, ground pins could share same ground plane, ground plane sufficiently isolated from noisy, digital systems ground plane (e.g., downstream output buffer ground plane). Route high-speed digital signal traces away from sensitive analog traces either channel. Make sure isolate analog input lines each respective converter minimize channelto-channel crosstalk. Keep signal lines short free degree turns.
Typical Demodulation Application
most frequently used modulation technique digital communications applications probably Quadrature Amplitude Modulation (QAM). Typically found spread-spectrum based systems, signal represents carrier frequency modulated both amplitude phase. transmitter, modulating baseband signal with quadrature outputs, local oscillator followed subsequent up-conversion generate signal. result in-phase quadrature carrier component, where component degree phase-shifted with respect inphase component. receiver, signal divided down into it's components, essentially representing modulation process reversed. Figure displays demodulation process performed analog domain, using dual matched +3V, 10-bit MAX1182 MAX2451 quadrature demodulator recover digitize baseband signals. Before being digitized MAX1182, mixed-down signal components filtered matched analog filters, such Nyquist pulse-shaping filters which remove unwanted images from mixing process, thereby enhancing overall signalto-noise (SNR) performance minimizing inter-symbol interference.
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
0.1µF LOWPASS FILTER MAX4108 0.1µF INA+ RIS0 22pF
0.1µF
0.1µF 0.1µF INPUT 0.1µF MAX4108 0.1µF MAX4108 INARIS0 0.1µF 22pF LOWPASS FILTER
MAX1182
0.1µF LOWPASS FILTER MAX4108 0.1µF INB+ RIS0 22pF
0.1µF
0.1µF 0.1µF 0.1µF LOWPASS FILTER INBRIS0 0.1µF 22pF
INPUT MAX4108 0.1µF MAX4108
Figure Typical Application Single-Ended Differential Conversion
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
INA+ 22pF 0.1µF N.C. 2.2µF 0.1µF
MINICIRCUITS TT1-6 INA22pF MAX1182 INB+ 22pF 0.1µF N.C. 2.2µF 0.1µF
MINICIRCUITS TT1-6 INB22pF
Figure Transformer-Coupled Input Drive
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity deviation values actual transfer function from straight line. This straight line either best straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1182 measured using best straight-line method.
error specification less than 1LSB guarantees missing codes monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure depicts aperture jitter (tAJ), which sample-to-sample variation aperture delay.
Aperture Delay
Aperture delay (tAD) time defined between falling edge sampling clock instant when actual sample taken (Figure
Differential Nonlinearity (DNL)
Differential nonlinearity difference between actual step-width ideal value 1LSB.
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
REFP
MAX4108
0.1µF
RISO INA+ 22pF REFN 0.1µF RISO INACIN 22pF REFP
MAX1182
MAX4108
0.1µF
RISO INB+ 22pF
REFN
0.1µF
RISO INBCIN 22pF
Figure Using Single-Ended, AC-Coupled Input Drive
Signal-to-Noise Ratio (SNR)
waveform perfectly reconstructed from digital samples, theoretical maximum ratio full-scale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution (N-Bits): SNRdB[max] 6.02dB 1.76dB reality, there other noise sources besides quantization noise e.g. thermal noise, reference noise, clock jitter, etc. computed taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD computed taking ratio signal spectral components minus fundamental offset.
Effective Number Bits (ENOB)
ENOB specifies dynamic performance specific input frequency sampling rate. ideal ADC's error consists quantization noise only. ENOB computed from: ENOB SINADdB 1.76dB 6.02dB
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
MAX2451
INA+ INA0°
MAX1182 INB+ INB-
POST PROCESSING
DOWNCONVERTER
Figure Typical Application, Using MAX1182
Total Harmonic Distortion (THD)
typically ratio first four harmonics input signal fundamental itself. This expressed
ANALOG INPUT SAMPLED DATA (T/H)
log10 where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range (SFDR)
TRACK HOLD TRACK
SFDR ratio expressed decibels amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset.
Intermodulation Distortion (IMD)
Figure Aperture Timing
two-tone ratio expressed decibels either input tone worst 3rd-order higher) intermodulation products. individual input tone levels -6.5dB full scale their envelope -0.5dB full scale.
Chip Information
TRANSISTOR COUNT: 10,811 PROCESS: CMOS
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs MAX1182
Functional Diagram
INA+ INAPIPELINE OUTPUT DRIVERS D9A-D0A OGND OVDD
CONTROL
INB+ INB-
PIPELINE
OUTPUT DRIVERS
D9B-D0B
REFERENCE
MAX1182
REFOUT REFN REFP REFIN
SLEEP
Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel Outputs
Package Information
48L,TQFP.EPS
MAX1182
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2001 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Dual 10-Bit, 65Msps, +3V, Low-Power with Internal Reference Parallel O

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