Ethernet Bridge Controller with Integrated Interface Ethernet Bri
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USB97C196
Ethernet Bridge Controller with Integrated
Interface Ethernet Bridge Device Integrated Provides Downstream Port High Performance Peripheral Controller Engine Integrated Transceiver Serial Interface Engine (SIE) Compliant Core Specification Supports dedicated Isochronous, Bulk, Interrupt, Control Data Endpoints Dynamic Hardware Allocation Packet Buffer Virtual Endpoints Dynamic Endpoint Buffer Length Allocation (0-1280 Byte Packets) Device Supports Self Powered Powered Designs System Level Interface Embedded 8051 Micro controller (MCU) Standard 8051 "Stop Clock" Modes Additional Ethernet Suspend /Resume Events Internal 8MHz Ring Oscillator Immediate Power Code Execution taps Clock Shared USB/Ethernet Memory Management Unit (MMU) 4096 Byte Board USB/Ethernet Packet Buffer Snooping Capabilities Byte Min. Page Size Pages Maximum Ethernet Packet Bulk Assembled Buffer Deep Receive Packet Queue Ethernet Deep Transmit Packet Queue, Endpoint Hardware Generated Packet Descriptor FIFO, Records Each Logical Packet Status Automatically Simultaneous Buffer Arbitration Between MCU, SIE, CSMA/CD Accesses Extended Power Management Independent Clock/Power Management SIE, MMU, CSMA/CD Blocks External Memory Interface 128k Byte Code Data Storage Flash, SRAM, EPROM Downloadable Code USB, Serial Port
Network Interface Integrates 10BASE-T Transceiver Functions: Driver Receiver
Link Integrity Test Receive Polarity Detection Correction Integrates Interface Supports Standard 10Mbps 1Mbps Data Rates Implements Mbps Manchester Encoding/Decoding Clock Recovery Input tolerant support Device able Transmit Receive Data Down 1Mbps Home Networking Applications 7-Wire Serial ENDEC Interface Allows Connection Home Networking Phys
Automatic Retransmission, Packet Rejection, Transmit Padding External Internal Loopback Modes Three Direct Driven LEDs Status/ Diagnostics Supports OnNow Technology Packet Filtering Power Management Technology High Performance Chained ("Back-toBack") Transmit Receive Operations Volt, Power Operation TQFP Package
tolerant pins "Pin Descriptions" section
GENERAL DESCRIPTION
SMSC USB97C196 Ethernet bridge device. device allows simple fullfeatured link allowing connectivity Ethernet connection. unique dynamic buffer architecture overcomes throughput disadvantages existing fixed FIFO buffer schemes allowing maximum utilization connection's overall bandwidth. This architecture minimizes integrated micro-controller's participation data flow, allowing back-to-back packet transfers oriented devices. efficiency this architecture allows high data throughput "store forward" architecture. SMSC USB97C196 allows external program code downloaded over allow easy implementation varied peripheral Device Classes combinations. This also provides method convenient field upgrades modifications.
Standard Microsystems registered trademark SMSC trademark Standard Microsystems Corporation. other product company names listed trademarks trade names their respective companies.
TABLE CONTENTS FEATURES GENERAL DESCRIPTION CONFIGURATION. DESCRIPTION FUNCTIONS BUFFER TYPE DESCRIPTIONS FIGURE USB97C196 BLOCK DIAGRAM FUNCTIONAL DESCRIPTION SERIAL INTERFACE ENGINE (SIE) MICRO CONTROLLER UNIT (MCU). SIEDMA MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION SPECIFIC SUPPORT BASED DEFINED SPECIFICATION. DATA TRANSFER MANAGEMENT BULK ENDPOINT PAIR ASSEMBLY MULTIPLE BULK PACKETS INTO ETHERNET FRAME SEGMENTATION ETHERNET FRAME INTO MULTIPLE BULK PACKETS ETHERNET PACKET RECEPTION APPLICATIONS TYPICAL SYSTEM IMPLEMENTATION DEVICE CLASS REQUIREMENTS SMSC USB97C196. ETHERNET DEVICE CLASS ENDPOINT ALLOCATION MEMORY CODE SPACE DATA SPACE DATA SPACE CODE SPACE MAPPINGS. BLOCK REGISTER SUMMARY BLOCK REGISTER SUMMARY BLOCK REGISTER SUMMARY (ETHERNET) BLOCK REGISTER SUMMARY REGISTER DESCRIPTIONS.
RUNTIME REGISTERS GENERAL PURPOSE REGISTER DEFINITIONS GPIO DIRECTION REGISTER GPIO OUTPUT REGISTER GPIO INPUT REGISTER UTILITY CONFIGURATION REGISTER GPIO MUXING BLOCK DIAGRAM. Function NETWORK DEVICE POWER CONSERVATION TRANSITION TABLE (SYSTEMS ENGINEERING NOTE). POWER MANAGEMENT UTILITY REGISTERS CODE FLASH BANK SELECT REGISTER WAKEUP SOURCE REGISTER WAKEUP MASK REGISTER RUNTIME REGISTERS ETHERNET TRANSMIT CONTROL REGISTER1 ETHERNET TRANSMIT CONTROL REGISTER2 STATUS REGISTER1. STATUS REGISTER2. ETHERNET RECEIVE CONTROL REGISTER ETHERNET RECEIVE CONTROL REGISTER ETHERNET COUNTER REGISTER1. ETHERNET COUNTER REGISTER2. ETHERNET CONFIGURATION REGISTER ETHERNET CONFIGURATION REGISTER INDIVIDUAL ADDRESS REGISTER MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTIONS ETHERNET DATA WINDOW REGISTER ETHERNET POINTER REGISTER (LOW). ETHERNET POINTER REGISTER (HIGH) TRANSMIT FIFO SELECT REGISTER COMMAND REGISTER. COMMAND SEQUENCING. ALLOCATION RESULT REGISTER PACKET NUMBER BYTE COUNT REGISTERS Packet Number Register. Byte Count Register High. Byte Count Register Low. BYTE COUNT CONVERSION REGISTERS. Byte Count Conversion Register High Byte Count Conversion Register ETHERNET REGISTERS
FIFO Register DONE FIFO REGISTER ETHERNET AWAITING FIFO REGISTER ETHERNET DONE FIFO REGISTER MEMORY INFORMATION REGISTER. RECEIVE DATA PACKET NUMBER LENGTH FIFO REGISTERS Receive Packet Number FIFO Register Receive FIFO Packet Length Register Receive FIFO Packet Length Register High. ETHERNET RECEIVE DATA PACKET NUMBER LENGTH FIFO REGISTERS ETHERNET Receive Packet Number FIFO Register. ETHERNET Receive FIFO Packet Length Register Low. ETHERNET Receive FIFO Packet Length Register High. TRANSMIT FIFO STATUS REGISTERS Transmit FIFO Status Register Transmit FIFO Status Register MANAGEMENT REGISTER PACKET HEADER DEFINITION. SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION. PACKET HEADER DEFINITION ETHERNET TRANSMIT RECEIVE PACKET STATUS DEFINITION Ethernet RECEIVE FRAME STATUS WORD. Ethernet Transmit FRAME STATUS WORD Status RAM) ETHERNET TRANSMIT RECEIVE PACKET DATA DEFINITION SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION. ENDPOINT CONTROL REGISTERS NONCONTROL ENDPOINT REGISTER ENDPOINT COMMAND REGISTER. FRAME COUNT REGISTER FRAME COUNT REGISTER. LOCAL ADDRESS REGISTER ALTERNATE ADDRESS REGISTER STATUS REGISTER CONTROL REGISTER CONTROL REGISTER CONFIGURATION REGISTER BLOCK SYSTEM INTERFACE UNIT. INTERFACE UNIT.
BLOCK REGISTER SUMMARY CONTROL REGISTER CONTROL REGISTER PARAMETERS. INPUT CLOCK TIMING. INPUT CLOCK TIMING. 8051 FLASH MEMORY READ TIMING 8051 FLASH MEMORY WRITE TIMING
CONFIGURATION
RESETIN FALE NFRD NFWR NFCE AVSST TPETXDP TPETXN TPETXDN TPETXP TXN/nCRS TXP/nCOL AVDDT AVDDR COLN COLP RECN RECP TPERXN TPERXP AVSSR AVSSP RBIAS AVDDP FRD0 FRD1 FRD2 FRD3 FRD4 FRD5 FRD6 FRD7 XTAL1/Clock XTAL2 nTEST PWRGOOD CLKOUT TESTOUT XTAL3/Clock XTAL4 FRA0 FRA1 FRA2 FRA3 FRA4
USB97C196 TQFP
FRA5 FRA6 FRA7 FRA8 FRA9 FRA10 FRA11 FRA12 FRA13 FRA14 FRA15 FRA16 EXSUP2 EXSPEED2 EXVPO2 EXVMO2 EXTXEN2B EXRCVD2 EXVPI2 EXVMI2 USB_OC PWREN2B
TEST2 XTXCLK XENDECX LNKLED/TXD TXLEDX/TXEN RXLEDX/ERXCLK ERXD GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 BUSPWRD VSSA USBP USBM VDDA PD2P PD2M VDDA
DESCRIPTION FUNCTIONS
Table SMSC USB97C196 Configuration TQFP PINS SYMBOL XTAL1/ Clock XTAL2 XTAL3/ Clock XTAL4 DESCRIPTION Crystal INTERFACE Crystal Clock Input: This connected terminal crystal connected external clock when crystal used. Crystal: This other terminal crystal. Ethernet Crystal Clock Input: This connected terminal crystal connected external clock when crystal used. Ethernet Crystal: This other terminal crystal. INTERFACE Downstream Connection signals These pointto-point signals driven differentially PD2P, PD2M used standard "Walk Port. Power Enable signal this applies power downstream port. This output signal active Low. Over-Current Sense. Input indicate over-current condition powered device downstream port. This input signal active Low. Upstream Connection Signals These point-to-point signals driven differentially. transceiver Output Enable This which active low, enable external transceiver transmit data bus. When this signal active (1), transceiver receive mode. suspend- Enables power state external transceiver while suspended. BUFFER TYPE ICLKx
OCLKx ICLKx
OCLKx
52,53
PD2M, PD2P
IOUSB
PWREN2B USB_OC
55,56
USBM,USBP EXTXEN2B
IOUSB
EXSPEED2
TQFP PINS 42,43
SYMBOL EXVPO2, EXVMO2
46,47
EXRCVD2 EXVPI2, EXVMI2
EXSUP2
88,89
TXP/nCOLL TXN/nCRS
DESCRIPTION Outputs External Differential Driver This output from associated port external transceiver Result Logic Logic Undefined Receive Data from Transceiver differential input Inputs from External Differential Driver These signals used detect single ended zero (SE0, error conditions interconnect speed from associated port external transceiver. (Inputs internal block) Result Speed High (Full) Speed ERROR Suspend This input signal when active high will force power state associated port logic. 10BASE-T interface INTERNAL ENDEC (nXENDEC open). this mode transmit differential outputs. They must externally pulled using resistors. EXTERNAL ENDEC (nXENDEC tied low). this mode pins inputs used collision carrier sense functions. 10BASE-T receive differential inputs. INTERNAL ENDEC 10BASE-T transmit differential outputs. 10BASE-T delayed transmit differential outputs. Used combination with TPETXP TPETXN generate 10BASE-T transmit pre-distortion. INTERNAL ENDEC Link output. EXTERNAL ENDEC Transmit Data output. receive differential inputs. collision differential inputs. collision indicated 10MHz signal this input pair. INTERNAL ENDEC Transmit output. EXTERNAL ENDEC Active Transmit Enable output.
BUFFER TYPE
Differential Output
80,81 90,92 93,91
TPERXP TPERXN TPETXP TPETXN TPETXDP TPETXDN nLNKLED/ RECP,RECN COLP,COLN nTXLED/ nTXEN
Differential Input Differential Output Differential Output OD16/ O162 Differential Input Differential Input OD16/ O162
82,83 84,85
TQFP PINS
SYMBOL ERXD
XTXCLK nRXLED/ RXCLK
DESCRIPTION INTERNAL ENDEC This used when Internal ENDEC enabled. EXTERNAL ENDEC receive data input. tolerant. Transmit clock input from external ENDEC. Used, only when External ENDEC used. INTERNAL ENDEC Receive output. EXTERNAL ENDEC Receive clock input. Note: RXCLK tolerant. Ethernet Misc. LEDs 22kohm resistor should connected between this analog ground. When tied SMSC USB97C196 configured EXTERNAL ENDEC. When tied high left open SMSC USB97C196 will Internal ENDEC FLASH INTERFACE Flash Data These signals used transfer data between 8051 external FLASH. 128K Flash Address These signals address memory locations within FLASH.
BUFFER TYPE with pullup
OD16/ with pullup
RBIAS NXENDEC
10,9, 8,7,5, 4,3,2 38,37 ,36,3 5,34, 33,32 ,31,3 0,28, 27,26 ,25,2 4,23, 22,21 6,29, 75,99 51,54
FRD[7:0]
FRA[16:0]
NFRD NFWR NFCE FALE VDDA AVDDT AVDDR AVDDP AVSST AVSSR AVSSP
Flash Read; active Flash Write; active Flash Chip Select; active Flash address latch enable POWER SIGNALS +3.3 Power Digital 3.3V Power Reference Ports Analog power Ethernet Transmitter Analog power Ethernet Receiver Analog power Circuit Ethernet Analog Ground Reference Ethernet Transmitter Analog Ground Reference Ethernet Receiver Analog Ground Reference Circuit
TQFP PINS 39,48 59,60 ,,61,6 2,63, 64,65
SYMBOL
DESCRIPTION Digital Ground Reference
BUFFER TYPE
VSSA GPIO[7:0]
Digital Ground Reference Ports MISCELLANEOUS General Purpose I/O. These pins configured inputs outputs under software control.
I/O16
USB_Bus_ Pwrd RESET_IN
TST_OUT
TEST2 NTEST
PWRGOOD CLKOUT
Power Selection This used select device implement Power Self Powered mode. Power reset; active high This signal used system reset chip. also generates internal POR. XNOR chain output This signal used testing chip internal XNOR Chain. Output only when PWRGOOD low, otherwise Tri-state. Reserved TEST Test input This signal manufacturing test pin. User pull high leave unconnected. Power good input. keeps SMSC USB97C196 power down mode when low. Must high normal operation. Clock output clock frequency same 8051 running clock. This clock stopped when 8051 stopped. Peripherals should this clock when they expected when 8051 stopped. This clock used synchronize other devices 8051.
Note:
input pins tolerant 3.3V with exception when otherwise specified Description table above. Pins RXCLK tolerant.
BUFFER TYPE DESCRIPTIONS
Table SMSC USB97C196 Buffer Type Description BUFFER DESCRIPTION Input pull-up) Input 90µA with internal pull-up Output with drive I/O8 Input/output with drive I/O16 Input/output with 16mA drive Output, 24mA sink, 12mA source. ICLKx XTAL clock input OCLKx XTAL clock output ICLK Clock input (TTL levels) IOUSB Defined specification; uses VDD3.3
Stream Port
Dual Speed XCVR
Dual Speed XCVR
Down Stream Port
Block
Control
CSMA/CD
Control
PKT#/ Control Length FIFO PKT#+Length FIFO
Length FIFO
ENDEC
Coax
8051 Embedded Controller
Address/Data Access
PKT#+Length FIFO PKT#+Length Completion FIFO
Address Data
Arbiter
(4096Bytes)
FIGURE USB97C196 BLOCK DIAGRAM
Address Data
PKT#+Length Completion FIFO
Address/Data Access
10B-T Tranceiver
RJ-45
FUNCTIONAL DESCRIPTION
SMSC USB97C196 incorporates Serial Interface Engine (SIE), 8051 Micro-controller Unit (MCU), Serial Interface Engine (SIEDMA), Ethernet engine Embedded port (One Stream down stream) Hub. device 4096 bytes internal SRAM data stream buffering, (Memory Management Unit) dynamically manage buffer allocation. semi-automatic nature SIEDMA, CSMA/CD engine blocks frees provide enumeration, protocol power management. arbiter integrated into assures that transparent access between SIEDMA, CSMA/CD, SRAM occurs. Serial Interface Engine (SIE) low-level protocol interpreter. controls protocol, packet generation extraction, parallel-to-serial serial-to-parallel conversion, coding decoding, stuffing, NRZI coding decoding. dynamically configured having combination five transmit, five receive endpoints (EP2 transmit only, receive only), independent addresses. also "Receive Addresses" snooping. Micro Controller Unit (MCU) 8051 embedded controller static CMOS MCU, which fully software compatible with industry standard Intel 80C51 micro-controller. internal registers SMSC USB97C196 blocks mapped into external memory space MCU. detailed description micro-controller's internal registers instruction found "SMSC USB97C196 Programmer's Reference Guide". SIEDMA This simplified engine, which automatically transfers data between SRAM control. SIEDMA places status block containing frame number, endpoint, byte count each incoming logical packet Ethernet packet consists multiple packets) before notifying arrival. This block operation transparent firmware. Memory Management Unit (MMU) Register Description This consists 4096 buffer that consists pages bytes. Allocations done with pages each (1536 bytes). buffer therefore concurrently hold packets with 64-byte payload. isochronous pipes, hold packets with 1023-byte payload each, still have room more 64-byte packets. This block supports independent transmit FIFO queues (one each endpoint), receive queue. Each endpoint have five transmit packets queued. receive queue accept packets size combination before forcing host back off. Specific Support Based Defined Specification This section will describe additional Device class requirements associated with specific features needed implement Ethernet Bridge.
Data Transfer Management Bulk Endpoint Pair Shown figures FIGURE DATA FLOW through FIGURE SEGMENT DELINEATION, shows data flow that would required implement Ethernet bridge device. implementation based Communications Device Class Specification (USB CDC) that currently under development Device Working Group, there number methods that need implemented. case when device receiving sequence bulk transactions, data flow shown FIGURE DATA FLOW, depicted below. receive FIFO's required store sequence packets/transactions upon completion, queue this buffer onto FIFO allow embedded 8051 eventually queue send over Ethernet LAN. requirements device this class defined Device class specification are: transactions received order bulk endpoint pipe will only receive bulk data transactions data that will sent over Ethernet. bulk packets transactions transmitted successfully host, host will retry eventually clear endpoint reset false condition. runs memory while bulk endpoint receiving, Bulk packets will de-allocated (Lost).
Data Flow
PKTn-1
PKTn
Receive FIFO
Number transactions required assemble Ethernet Packet (packetlen/64bytes
Handle
Queue
Handle Handle
CSMA Transmit Block
FIGURE DATA FLOW
Data Flow
Host
PKTn-1
PKTn
Transmit FIFO
Number Transactions required segment Ethernet Packet (packetlen/64 bytes
Handle
IN2USB Queue
Handle Handle
CSMA Receive Block
FIGURE DATA FLOW
From
USB-based Networking devices will BULK transfers (Isochronous also possible) exchange data between host device. Ethernet connection between host computer Ethernet media will "tunneled" through channel. this, host must formulate Ethernet packet provide driver. driver must then segment Ethernet packet into multiple packets transport bus. receive block conjunction with engine must assemble Ethernet packet send onto LAN. When Ethernet packet from arrives device must segmented into multiple packets device transport over host. driver executing host must then reconstruct original Ethernet packet from these fragments. Both driver device must capable segmenting Ethernet packets into packets well re-combining packets into Ethernet packets.
Assembly Multiple Bulk Packets into Ethernet Frame
Data Flow
HOST
PKT1
PKT2
PKTn-1
PKTn
Ethernet Controller
Number transactions required assemble Ethernet Packet (packetlen/64bytes nmax
Data FLow
HOST
PKT1
PKT2
PKTn-1
PKTn
Ethernet Controller
Number Transactions required segment Ethernet Packet (packetlen/64 bytes nmax
FIGURE SEGMENTATION RE-ASSEMBLY
Ethernet frames sent from host USB97C196 byte bulk packets over USB. diagram above. USB97C196 will recognize decode start ending logical Ethernet Packet receiving packet that less than bytes Zero length case Ethernet packet being exact multiple bytes. Once USB97C196 synchronized, must allocate sufficient memory buffer packets while full Ethernet frame reconstructed. possible techniques are: case that insufficient memory exists re-construct complete Ethernet frame, USB97C196 will employ flow control restrict host, ignore packet stall point, causing host re-try. Otherwise, USB97C196 will continue accumulating bulk packets until frame detected. There least methods detecting frame. Segmentation Ethernet Frame into Multiple Bulk Packets Diagram below shows method USB97C196 Ethernet Bridge controller determines start Logical Ethernet packet being transmitted over Bulk point.
Segment Delineation
PKTn PKTn
PKT0
PKT1
PKTn-2
PKT-1
PKT0
PKT1
Delineation (last) Transaction Packet bytes Zero Length
Segmented Ethernet Packet Data
Segmented Ethernet Delineation (last) Packet Data (n+1) Transaction packet bytes Zero Length
FIGURE SEGMENT DELINEATION
Ethernet Packet Reception Ethernet frames being received from must buffered. received Ethernet packet then segmented into packets described above, transported host USB. device detects arrival inbound Ethernet frame receives into buffer. contents that buffer delivered demand over host bulk endpoint. device "multiplexed" such that read written Ethernet frame buffer, packet buffer chain. Since buffer sizes different Ethernet some control status
information needs embedded into each memory buffer, additional Status Queue defined store envelope encapsulation information.
APPLICATIONS
USB97C196 allows designer implement connectivity solution based data model from/to standard 802.x Ethernet data flow medium. This USB97C196 allows designer ability utilize embedded allow additional port. This allows "Use back" paradigm, allowing user ability gain Ethernet connection while retaining current port.
TYPICAL SYSTEM IMPLEMENTATION
FLASH
FRA[16:0]
FRD[7:0]
Control
Crystal
(USB-,USB+)
USB97C196 Ethernet Controller
10B-t Signals
Magnetics
RJ-45 Connector
RBIAS Resister
PWRENP,PWROKP,PD+,PD-
Signals (Optional)
20Mhz Ethernet Crystal
Tranceiver (Optional)
Ethernet Coax
Down Stream Power Sense/ Current Limitation logic (Optional)
Down StreamPort
Device Class Requirements SMSC USB97C196
This section will describe requirements relating Communications device class specification relating Endpoint resources will allocated. next section titled "Specific Support Based Defined Specification" page Data-In/Data-Out pipe mechanism same networking device models supported specification. independent media type (e.g., Cable, xDSL, Ethernet) media data type (e.g. Ethernet frames).Typical USB-based Networking devices will support bulk transfers default configuration exchange data between host device. While each data packet bulk endpoint limited maximum packet size defined associated endpoint descriptor, should noted that host might request multiple bulk protocol packets within single frame. USB97C196 will support this requirement. maximum throughput, Networking device must prepared transfer multiple bulk packets within single frame. Some USB-based Networking device implementations support isochronous data transfers addition instead bulk transfers USB97C196. Isochronous transfers guarantee data throughput bounded latency, consistent with needs real-time streams. Isochronous data errors reported receiver, data integrity (i.e.,retransmission) provided link. Data Class Interface Descriptor protocol code Networking Control Models 00h. provides inherent flow control mechanism isochronous pipes, specification defines higher level mechanism doing Instead, assumed that host software responsible doing traffic shaping necessary match end-to-end negotiation. networking device performing traffic shaping, then either bulk endpoint should used, flow control methods should provided using vendor-specific methods. Data Class interface networking device shall have minimum interface settings. first setting (the default interface setting) includes endpoints therefore networking traffic exchanged whenever default interface setting selected. more additional interface settings used normal operation, therefore each includes pair endpoints (one OUT) exchange network traffic. Firmware will select alternate interface setting initialize network aspects device enable exchange network traffic. recover network aspects device known states, select default interface setting (with endpoints) then select appropriate alternate interface setting. This action will flush device buffers, clear filters statistics counters will cause NETWORK_CONNECTION CONNECTION_SPEED_CHANGE notifications sent host. stated previously almost type attached networking device, mechanism needed where both networking device Host delineate beginning ending segment within data stream delivered endpoint pipe. This positive delineation done using short packet mechanism. When segment spans packets, first packet through packet shall maximum packet size defined endpoint. packet less than maximum packet size transfer this short packet will identify segment. packet exactly maximum packet size, shall followed zero-length packet (which short packet) assure segment properly identified. When transmitting data networking device, assumed that client host driver takes appropriate actions cause short packet sent networking device. segments with lengths that even multiple pipe's "max packet size", ability write buffer zero length required generate this short packet.
host attached network device must negotiate establish maximum segment size. upper limit this usually function buffering capacity attached device, there other factors involved well. networking devices that exchange Ethernet frames, size segment also negotiable. Typical Ethernet frames 1514 bytes less length (not including CRC), this could longer (e.g., 802.1Q VLAN tagging). Ethernet Networking Control Model used exchanging Ethernet framed data between device host. Communication Class interface used configure manage various Ethernet functions, where "Ethernet Networking Control Model" SubClass code indicated descriptor definition Communication Class interface. Data Class interface used exchange Ethernet encapsulated frames sent over USB. These frames shall include everything from Ethernet destination address (DA) data field. checksum must included either send receive data. responsibility device hardware generate check required specific media. Receive frames that have checksum must forwarded host. This implies that device must able buffer least complete Ethernet frame. Although typical Networking device stays "always connected" state, some Networking device management requests required properly initialize both device host networking stack. There also occasional changes device configuration state, e.g., adding multicast filters.
Ethernet Device Class Endpoint Allocation
SMSC USB97C196 specialized Device sense that Endpoints have specific attributes that unique Ethernet bridge design paradigm. USB97C100 endpoints which same. Endpoints their functionality shown Table SMSC 97C196 Endpoint Attributes page Table describes USB97C196 Endpoint definition usage relative section above Specific Support Based Defined Specification defined starting page
Table SMSC 97C196 Endpoint Attributes ENDPOINT NUMBER Endpoint ENDPOINT ATTRIBUTES Control Endpoint This Endpoint corresponds Standard Common Device Class definition "Control Endpoint." requirements "Control Endpoint" defined specification must adhered too. Please refer Revision specification additional details Interrupt Endpoint This Endpoint general purpose Endpoint that conforms standard protocols defined specification. Bulk, Isochronous Interrupt options available. This Endpoint however will initialized "Interrupt Endpoint" based Ethernet implementation standard. description Firmware Driver developer Endpoint bi-directional single direction interrupt Endpoint.
Endpoint
ENDPOINT NUMBER Endpoint
ENDPOINT ATTRIBUTES Compliant (Segmentation Re-assembly) Endpoint This Endpoint corresponds Host Ethernet Bridge Bulk Data Reception Pipe. This pipe special Pipe. adheres rules defined Class specification relating rules regarding delineation logical Ethernet Packets defined previous section tilted "Specific Support Based Defined Specification" page Compliant (Segmentation Re-assembly) Endpoint This Endpoint corresponds Host Ethernet Bridge Bulk Data transmission Pipe. This pipe special Pipe. adheres rules defined Class specification relating rules regarding delineation logical Ethernet Packets defined previous section tilted "Specific Support Based Defined Specification" page Generic Pipe This Endpoint corresponds standard Pipe that ability Bulk, Isochronous, Control, Interrupt Pipe. This endpoint optional standard Compliant applications. available system developer requirement need enhance feature support. Generic Pipe This Endpoint corresponds standard Pipe that ability Bulk, Isochronous, Control, Interrupt Pipe. This endpoint optional standard Compliant applications. available system developer requirement need enhance feature support
Endpoint
Endpoint
Endpoint
Memory
memory follows from 8051's viewpoint: Code Space Table Code Memory CODE SPACE Movable page MEM_BANK reg. Select
8051 ADDRESS 0xC000-0xFFFF
ACCESS External FLASH
0x8000-0xBFFF
Fixed page 0x00000-0x03FFF FLASH
External FLASH
0x4000-0x7FFF
0x0000-0x3FFF
Movable FLASH page; pages External FLASH (0x00000-0x1FFFF) selected MEM_BANK Register Default: 0x040000x07FFF FLASH MEM_BANK reg. Select Fixed FLASH Page 0x00000-0x03FFF FLASH
External FLASH External FLASH External FLASH External FLASH External FLASH
Data Space Table Data Memory DATA SPACE Movable page Default 0x04000-0x07FFF FLASH Select MEM_BANK reg. Fixed page 0x00000-0x03FFF FLASH 0x7FD0-0x7FEF Ethernet Register Window 0x7F80-0x7F9F 0x7F70-0x7F7F 0x7F50-0x7F6F 0x7F20-0x7F2F Power 0x7F10-0x7F1F Configuration 0x7F00-0x7F0F Runtime Note
8051 ADDRESS 0xC000-0xFFFF
ACCESS External FLASH
0x8000-0xBFFF 0x7000-0x7FFF
External FLASH Internal
0x6000-0x6FFF
0x6000: Data Register 0x6000-0x6FFF: entire mapped here
Internal
0x5000-0x5FFF 0x4000-0x4FFF 0x3000-0x3FFF
used used used
8051 ADDRESS
DATA SPACE
ACCESS
0x2000-0x2FFF 0x0100-0x1FFF 0x0000-0x00FF
Registers SFR's
used used Internal
Note MCU, MMU, block registers external 8051, internal SMSC USB97C196. These addresses will appear FLASH bus, read write strobes will inhibited. Data Space Code Space mappings diagrams shown FIGURE EXTERNAL CODE SPACE DIAGRAM FIGURE EXTERNAL DATA MEMORY DIAGRAM pages respectively, describe Data Space Code Space mappings between External Flash internal 8051 memory map.
FLASH Address
8051 External Code Address Space
0xFFFF -16k Flash Page 0xC000 Fixed Flash Page 0x8000 Flash pages 0x4000 Fixed Flash Page
64Kb
Sele cted
iste
FIGURE EXTERNAL CODE SPACE DIAGRAM
Note USB97C196 presents 17-bit address flash that obtained concatenating three bits with lower bits [13:0] address presented MCU. three bits Determined follows: page movable, then upper three bits copied from MEM_BANK.
128Kb
page fixed, then upper three bits zero.
lower bits [13:0] 16-bit address represent offset into page which being referenced. upper bits [15:14] represent page being accessed MCU's address space; replacing these bits (the larger) MEM_BANK allows mappings occur. From MCU's perspective though, 64K-address space code 64K-address space data.
FLASH Address
8051 External Data Address Space
0xFFFF FLASH Page 0xC000 Fixed FLASH Page
Sele cted
64Kb
iste
FIGURE EXTERNAL DATA MEMORY DIAGRAM
128Kb
Block Register Summary Table Block Register Summary ADDRESS (HEX) 7F00 7F01 7F02 7F03 7F06 7F07 7F18 7F19 7F1A 7F1B 7F27 7F29 7F2A 7F2B 7F2C 7F2D 7F7D 7F7E 7F7F DESCRIPTION RUNTIME REGISTERS ISR_0 INT0 Source Register IMR_0 INT0 Mask Register ISR_1 INT1 Source Register IMR_1 INT1 Mask Register DEV_REV Device Revision Register DEV_ID Device Register UTILITY REGISTERS GPIOA_DIR GPIO Configuration Register GPIOA_OUT GPIO Data Output Register GPIOA_IN GPIO Data Input Register UTIL_CONFIG Miscellaneous Configuration Register POWER MANAGEMENT REGISTERS CLOCK_SEL 8051 Clock Select Register MEM_BANK Flash Bank Select WU_SRC_1 Wakeup Source WU_MSK_1 Wakeup Mask Reserved Reserved Reserved Reserved TEST REGISTERS MCU_TEST3 Reserved Test MCU_TEST2 Reserved Test MCU_TEST1 Reserved Test NAME PAGE
Block Register Summary Table Block Register Summary ADDRESS (HEX) 6000 7F50 7F51 7F52 7F53 7F54 7F55 7F56 7F57 7F58 7F59 7F5A 7F5B 7F5D 7F60 7F61 7F62 7F63 7F64 7F65 7F66 7F67 DESCRIPTION REGISTERS MMU_DATA 8051-MMU Data Window Register FIFO 8051-MMU Pointer Register (Low) 8051-MMU Pointer Register (High) MMUTX_SEL 8051-MMU FIFO Select Commands MMUCR 8051-MMU Command Register 8051-MMU Allocation Result Register 8051-MMU Packet Number Register MEMORY INFORMATION REGISTER TX/RX_MGMT TX/RX Management Register USB_RX_FIFO Receive Packet Number FIFO Register USB_RX_FIFO_Length Receive FIFO Packet _Low Length Register USB_RX_FIFO_Length Receive FIFO Packet _High Length Register High Ethernet_RX_FIFO ETHERNET Receive Packet Number FIFO Register RX_FIFO_Length_Low ETHERNET Receive FIFO Packet Length Register RX_FIFO_Length_High ETHERNET Receive FIFO Packet Length Register High USB_TXSTAT_A TRANSMIT FIFO STATUS REGISTER USB_TXSTAT_B TRANSMIT FIFO STATUS REGISTER PNBCRL PACKET NUMBER Byte Count REGISTER PNBCRH PACKET NUMBER Byte Count REGISTER High USB_POP_TX FIFO USB_POP_TX_Done FIFO Done ETH_TX Ethernet FIFO Eth_POP_TX_DONE Ethernet Transmit FIFO Done Register NAME PAGE
ADDRESS (HEX) 7F6C 7F6D 7F6E 7F6F
NAME PNCRH PNCRL MMU_TESTx MMU_TESTx
DESCRIPTION Conversion Byte Count REGISTER Conversion Byte Count REGISTER High Reserved Test Reserved Test
PAGE
Block Register Summary Table Block Register Summary ADDRESS (HEX) 7F80 7F81 7F82 7F83 7F84 7F85 7F86-7F8F 7F90 7F91 7F92 7F93 7F94 7F95 7F96 7F97 7F98 7F99 7F9A 7F9B 7F9C 7F9D 7F9E 7F9F 7FA9 7FAA 7FAC 7FA0 7FA1 7FA2 DESCRIPTION Control Registers EP_CTRL0 Endpoint Control Register EP_CTRL1 Endpoint Control Register EP_CTRL2 Endpoint Control Register EP_CTRL3 Endpoint Control Register EP_CTRL4 Endpoint Control Register EP_CTRL5 Endpoint Control Register RESERVED RESERVED FRAMEL Frame Count FRAMEH Frame Count High SIE_ADDR Local Address Register SIE_STAT Status Register SIE_CTRL Control Register SIE_TST1 Reserved Test Register SIE_TST2 Reserved Test Register SIE_EP_TEST Reserved Test Register SIE_CONFIG Configuration Register ALT_ADDR Secondary Local Address Register SIE_TST Reserved Test Register SIE_TST Reserved Test Register SIE_TST Reserved Test Register SIE_TST Reserved Test Register ALT_ADDR2 Reserved ALT_ADDR3 Reserved SIE_CTRL2 Control Register EPCMD Endpoint Command Register NONCTRL_EP NonControl Endpoint Register BLOCK CONTROL REGISTERS IdVendor-Low Byte byte Vendor IdVendor-High Byte High byte Vendor IdProduct-Low Byte byte Product NAME PAGE
ADDRESS (HEX) 7FA3 7FA4 7FA5 7FA6 7FA7
NAME IdProduct-High Byte BcdDevice Byte BcdDevice High Byte HubControl1 HubControl2
DESCRIPTION High byte Product device release number device release number Control Register Control Register
PAGE
(Ethernet) Block Register Summary Table (Ethernet) Block Register Summary ADDRESS (HEX) 7FD0 7FD1 7FD2 7FD3 7FD4 7FD5 7FD6 7FD7 7FD8 7FD9 7FDA 7FDB 7FDC 7FDD 7FDE 7FDF 7FE0 7FE1 7FE2 7FE3 7FE4 7FE5 7FE6 7FE7 NAME ETCR1 ETCR2 EPH1 EPH2 RCR1 RCR2 ECR1 ECR2 EconfigR1 EconfigR2 IAR0 IAR1 IAR2 IAR3 IAR4 IAR5 MCT0 MCT1 MCT2 MCT3 MCT4 MCT5 MCT6 MCT7 DESCRIPTION Ethernet Control Registers Ethernet Transmit Control Register1 Ethernet Transmit Control Register2 STATUS REGISTER1 STATUS REGISTER2 Ethernet Receive Control Register Ethernet Receive Control Register Ethernet counter Register Ethernet counter Register Ethernet CONFIGURATION REGISTER Ethernet CONFIGURATION REGISTER INDIVIDUAL ADDRESS REGISTER INDIVIDUAL ADDRESS REGISTER INDIVIDUAL ADDRESS REGISTER INDIVIDUAL ADDRESS REGISTER INDIVIDUAL ADDRESS REGISTER INDIVIDUAL ADDRESS REGISTER Multicast Table Register Multicast Table Register Multicast Table Register Multicast Table Register Multicast Table Register Multicast Table Register Multicast Table Register Multicast Table Register PAGE
REGISTER DESCRIPTIONS Below describes registers 8051 deals with terms handling Ethernet Bridge functions.
Runtime Registers Table Interrupt Source Register ISR_0 (0x7F00 RESET=0x00) INTERRUPT SOURCE REGISTER NAME DESCRIPTION when Ethernet Protocol Handler section indicates various possible special conditions. This merges exception type interrupt sources, whose service time critical execution speed 8051 Core firmware. exact nature interrupt obtained from Status Register (EPHSR), enabling these sources done Control Register. possible sources are: LINK_OK transition. CTR_ROL Statistics counter roll over. TXENA cleared fatal transmit error occurred forcing TXENA cleared. TX_SUC will specific reason will reflected bits: TXUNRN Transmit underrun. SQET Error. LOST CARR Lost Carrier. LATCOL Late Collision. 16COL collisions. Packet Number (PNR) been successfully queued Ethernet RXFIFO when receive interrupt generated. first packet number serviced read from FIFO PORTS register. always logic complement REMPTY FIFO PORTS register. Whenever Ethernet FIFO becomes empty. This will occur when last queued packet been successfully been transmitted Ethernet EPH. Ethernet when least packet transmission completed. first packet number serviced read from Ethernet FIFO PORTS register. Eth_TX_PKT always logic complement TEMPTY FIFO PORTS register. Packet Number (PNR) been successfully queued RXFIFO. Whenever enabled Endpoint's FIFO becomes empty. This will occur when last queued packet queues successfully transferred Host.
ETH_RX_PKT
ETH_TX_EMPTY
ETH_TX_PKT
USB_RX_PKT USB_TX_EMPTY
ISR_0 (0x7F00 RESET=0x00) NAME USB_TX_PKT Eth_RCV_OVRN
INTERRUPT SOURCE REGISTER DESCRIPTION Packet successfully transmitted. Ethernet Receive Overrun Interrupt This when Ethernet EPH, conjunction with does have enough buffer memory receive packet.
These bits automatically cleared each time this register read. Therefore, each time this register read pending interrupts must serviced before continuing normal operation. Software Note: TX_EMPTY useful warning performance degradation. This interrupt indicates that next time Host polls affected endpoint, will receive that endpoint, thus reducing effective overall bandwidth retries. Firmware must TX_STAT determine which endpoint queue empty. ETH_TX EMPTY FIFO goes empty. This used generate single interrupt sequence Ethernet packets en-queued transmission. This latches empty condition, will stay until specifically cleared writing acknowledge register with EMPTY set. real time reading FIFO empty desired, should first cleared then read. EMPTY ENABLE should only after following steps: packet enqueued transmission previous empty condition cleared (acknowledged). Firmware uses AUTO RELEASE (the default) mode then should enable EMPTY well INT. EMPTY will when complete sequence packets transmitted. will sequence stops fatal error packets sequence.
Eth_RCV_OVRN USB_TX_PKT USB_TX_EMPTY USB_RX_PKT ETH_TX_PKT ETH_TX_EMPTY ETH_RX_PKT MASK 0X7F01
Eth_RCV_OVRN USB_TX_PKT USB_TX_EMPTY USB_RX_PKT ETH_TX_PKT ETH_TX_EMPTY ETH_RX_PKT
8051
SOURCE 0x7F00
8051 Interrupt Generation
Table Interrupt Mask IMR_0 (0x7F01- RESET=0xFF) NAME INTERRUPT MASK REGISTER DESCRIPTION Ethernet Received Packet Interrupt Mask Enable Interrupt Mask Interrupt Ethernet Received Packet Interrupt Mask Enable Interrupt Mask Interrupt Ethernet Transmit Queue Empty Interrupt Enable Interrupt Mask Interrupt Ethernet Transmit Packet Interrupt Mask Enable Interrupt Mask Interrupt Received Packet Interrupt Mask Enable Interrupt Mask Interrupt Transmit Queue Empty Interrupt Enable Interrupt Mask Interrupt Transmit Packet Interrupt Mask Enable Interrupt Mask Interrupt Ethernet Receive Overrun Interrupt Mask Enable Interrupt Mask Interrupt
ETH_RX_PKT
ETH_TX_EMPTY
ETH_TX_PKT
USB_RX_PKT
USB_TX_EMPTY
USB_TX_PKT
Eth_RCV_OVRN
Table Interrupt Source Register ISR_1 (0x7F02- RESET=0x00) INTERRUPT SOURCE REGISTER NAME DESCRIPTION SIE_RDY This READY signal, directly from block. used diagnostics. RFRDY This "Not Empty" signal from FIFO. TXRDY This "Not Full" signal from FIFO. returned Idle State. Marks each transaction. When Start Frame token correctly decoded. Generated write strobe Frame Count register. ALLOC Software Allocation Request complete interrupt. This interrupt generated hardware (SIEDMA EPHDMA) allocation requests. This complement FAILED ALLOCATION RESULT register. ALLOC ENABLE should only following allocation command, cleared upon servicing interrupt. USB_RX_OVR receive error occurred within domain Core. hardware automatically recovers from this condition after cause been alleviated (e.g. partially allocated packets will released. Note RX_OVRN EPHSR will also set, packet received will cleared. RX_OVRN bit, however, latches overrun condition purpose being polled generating interrupt, will only cleared writing acknowledge register with RX_OVRN set. PWR_MNG wakeup power management event WU_SRC_1 Signature Wakeup register gone active. Note These bits cleared each time this register read Note RX_OVRN interrupt should considered firmware general Receive Overrun Core, meaning that packet destined Core could received acknowledged back Host. firmware should check Packet Number FIFO Register (RXFIFO) full. empty, there many transmit packets queued (thereby consuming memory) device receive anything, last packet have been corrupted wire, then endpoint received packet while stalled. empty, then more receive packets must de-queued before device continue receive packets. normal course operation, should respond RX_PKT interrupt often possible buffering logic job.
RESUME RESET WKUP MASK (0x7F2B) RESUME RESET WU_SRC_1 (0x7F2A)
Mask (bit
Related Events
PWR_MNG RX_OVRN ALLOC TXRDY RXRDY SIE_RDY MASK 0X7F03
PWR_MNG RX_OVRN ALLOC TXRDY RXRDY SIE_RDY
8051
SOURCE 0x7F02
8051 Interrupt Generation
Table Interrupt Mask IMR_1 (0x7F03- RESET=0xFF) NAME SIE_RDY INTERRUPT MASK REGISTER DESCRIPTION Ready Interrupt mask Enable Interrupt Mask Interrupt FIFO "Not Empty" Interrupt mask Enable Interrupt Mask Interrupt FIFO "Not Full" Interrupt mask Enable Interrupt Mask Interrupt interrupt mask Enable Interrupt Mask Interrupt Start Frame Interrupt Mask Enable Interrupt Mask Interrupt Software Allocation Complete Interrupt Mask Enable Interrupt Mask Interrupt Receive Overrun Interrupt Mask Enable Interrupt Mask Interrupt Power management Interrupt Mask Enable Interrupt Mask Interrupt
RFRDY
TXRDY
ALLOC
USB_RX_OV PWR_MNG
Table Device Revision Register DEV_REV (0x7F06- RESET=0x41) DEVICE REVISION REGISTER NAME DESCRIPTION [7:0] ASCII This register defines revision information used 0x41 SMSC. Table Device Identification Register DEV_ID (0x7F07- RESET=0x23) DEVICE IDENTIFICATION REGISTER NAME DESCRIPTION [7:0] '23' This register defines identification information used SMSC.
GENERAL PURPOSE REGISTER DEFINITIONS
registers described below allow USB97C196 ability control external logic multiple functions. Examples possible functions Power Control Power management, devices, Re-enumeration logic, etc. Additional functionality would include possibility external logic generating events system status changes that device would consider important such Link State change media change. GPIO Direction Register This register determines input/output state associated GPIO Pin. Please refer definition definition section specification. Note: Timer inputs T[1:0] configured outputs left unconnected that software write bits trigger timer. Otherwise, Timer inputs used count external events internal receptions. Table GPIO Direction Register GPIOA_DIR (0x7F18- RESET=0x00) UTILITY REGISTERS NAME DESCRIPTION GPIO7 GPIO7 Direction GPIO6 GPIO6 Direction GPIO5 GPIO5 Direction GPIO4 GPIO4 Direction GPIO3/T1 GPIO3 Direction
GPIOA_DIR (0x7F18- RESET=0x00) NAME
GPIO2/T0
GPIO1/TXD
GPIO0/RXD
UTILITY REGISTERS DESCRIPTION GPIO2 Direction GPIO1 Direction GPIO0 Direction
GPIO Output Register When associated GPIO pins configured outputs GPIO direction register defined above, writing this register sets associated high low. Note: When bits through configured 8051 UART pins defined below, state pin(s) defined 8051 block. Table GPIO Output Register GPIOA_OUT GPIO DATA OUTPUT (0x7F19- RESET=0x00) REGISTER NAME DESCRIPTION GPIO7 GPIO7 Output Buffer Data GPIO6 GPIO6 Output Buffer Data GPIO5 GPIO5 Output Buffer Data GPIO4 GPIO4 Output Buffer Data GPIO3/T1 GPIO3 Output Buffer Data GPIO2/T0 GPIO2 Output Buffer Data GPIO1/TXD GPIO1 Output Buffer Data GPIO0/RXD GPIO0 Output Buffer Data GPIO Input Register When associated GPIO pins configured inputs GPIO direction register defined above, reading this register will latch state associated input pin. Note: When bits through configured 8051 UART pins defined below, state pin(s) defined 8051 block.
Table GPIO Input Register GPIOA_IN (0x7F1A- RESET=0xXX) GPIO INPUT REGISTER NAME DESCRIPTION GPIO7 GPIO7 Input Buffer Data GP106 GPIO6 Input Buffer Data GP105 GPIO5 Input Buffer Data GP104 GPIO4 Input Buffer Data GP103/T1 GPIO3 Input Buffer Data GP102/T0 GPIO2 Input Buffer Data GP101/TXD GPIO1 Input Buffer Data GPIO0/RXD GPIO0 Input Buffer Data
Utility Configuration Register This register defines function associated GPIO pin(s) defined below. When bits through configured 8051 UART pins defined below, state pin(s) defined 8051 block. Note Counter mode, 8051 must sample T[1:0] instruction cycle, then next. 12MHz, Pulse must active least 1us. Note Missing packets reconstructed using Timer mode count number 8051 instruction cycles since last valid Frame received. Note GPIO used output nSOF pulses. This done configuring GPIO output writing GPIO register generate pulses each time packet received.
Table Utility Configuration Register UTIL_CONFIG (0x7F1B- RESET=0x00) UTILITY CONFIGURATION REGISTER NAME DESCRIPTION [7:4] Reserved Reserved GPIO3/T1 P3.5 Timer input trigger source GPIO3 FRAME write strobe GPIO2/T0 P3.4 Timer input trigger source GPIO2 FRAME write strobe GPIO1/TXD GPIO1/TXD Output Select GPIO1 P3.1 GPIO0/RXD P3.0 RXD/GPIO0 Input Select RXD<=GPIO0 RXD<='0'
GPIO MUXING BLOCK DIAGRAM diagram below describes internal logic that implemented allow pins defined below configured either input pins, output pins 8051 UART pins.
GPIO data (0x7F19[7:4]) GPIO Direction (0x7F18[7:4]) GPIO data (0x7F1A[7:4]) GPIO[7:4]
GPIO2 data (0x7F19[2]) GPIO2 (0x7F18[2]) 8051 timer P3.4"
GPIO2 data (0x7F1A[2]) Internal 0X7F1B[2] GPIO3 data (0x7F19[3]) GPIO3 (0x7F18[3])
8051 timer P3.5"
GPIO3 data (0x7F1A[3]) Internal 0X7F1B[3]
GPIO0 data (0x7F19[0]) GPIO0 (0x7F18[0]) GPIO0 data (0x7F1A[0]) "Uart P3.0" 0X7F1B[0]
GPIO1 data (0x7F19[1]) "Uart P3.1" 0X7F1B[1]
GPIO1 (0x7F18[1])
GPIO1 data (0x7F1A[1])
FIGURE GPIO MUXING BLOCK DIAGRAM
Function USB97C196 will initially default, Reset, low-power Function mode. Low-power devices limited 500uA suspend current. USB97C196 device, after configured MCU, will configured High-power device will enabled remote wakeup source. USB97C196 will: USB97C196 will initially default, Reset, low-power Function mode. device will limited 100ua (500uA External System Power requirements) suspend current. Once Device configured, USB97C196 limited draw (2.5mA External logic) during suspend. Bus-Powered mode, USB97C196 internal configured bus-powered also consume maximum 2.5mA, with 500uA allocated single external port. While Suspend state, amplitude current spike will exceed device power allocation budget 100mA. maximum second allowed averaging interval. average current cannot exceed average suspend current limit (500uA) during 1.0s interval. Network Device Power Conservation transition table (Systems Engineering Note) software firmware place SMSC USB97C196 Network function into operational mode power modes Power management registers. SMSC USB97C196 powers state effect reset assertion controller power states select-able.
Power Management Utility Registers Table Clock Source Select CLOCK_SEL (0x7F27 RESET=0x40) MCU/ISADMA CLOCK SOURCE SELECT NAME DESCRIPTION SLEEP When PCON. SLEEP been ring oscillator will gated off, then oscillators will turned maximum power savings. (These signals used generate nFCE) ROSC_EN Ring Oscillator Disable. Ring Oscillator Enable. ROSC_EN must before switched internal Ring Oscillator Clock source. MCUCLK_SRC MCUCLK_SRC overrides MCUCLK_x clock select switches Ring Oscillator. Ring Oscillator. ROSC_EN must enabled first. clock specified MCU_CLK_[1:0]
[4:3]
CLOCK_SEL (0x7F27 RESET=0x40) NAME MCU_CLK[1:0]
[2:0]
Reserved
MCU/ISADMA CLOCK SOURCE SELECT DESCRIPTION [4:3] 8MHz [4:3] 12MHz [4:3] 16MHz [4:3] 24MHz Reserved
Note 8051 program itself internal Ring Oscillator having frequency range between 12MHz. This precise clock, meant provide 8051 with clock source, without running 24MHz crystal oscillator Note Switching between fast slow clocks recommended save power. Note Clock switching done long both clocks running. When switching, takes total clocks clocks original clock plus clocks switching clock) guarantee switching. Note Time required from ROSC_EN=1 MCUCLK_SRC=0. Code FLASH Bank Select Register Table FLASH Bank Select Register CMEM_BANK (0x7F29 RESET=0x01) NAME [7:3] Reserved [2:0] A[16:14] CODE FLASH BANK SELECT REGISTER DESCRIPTION Reserved These bits selects which page resides 0x4000-0x7FFF Code Space. These bits also mirror selection page 0xC000 0xFFFF code space well. 0x0000-0x3FFF page will always reflect FLASH page (0x00000-0x03FFF). fixed page also mirrored 0x8000 through 0xBFFF. Wakeup Source Register Table Wakeup Source Register WU_SRC_1 (0x7F2A RESET=0x00) NAME [7:3] Reserved USB_Reset WAKEUP SOURCE DESCRIPTION
Reserved This when detects simultaneous logic lows (Single-Ended full speed times, speed times 2.5<t<5.5us). Resume This detection Global Resume state (when there transition from state while Global Suspend). Reserved Reserved Note Only high transitions associated inputs sets these bits. Note These bits cleared each time this register read Note Unmasked Wakeup Source bits generate INT1 PWR_MNG interrupt, restart 8051 when clock stopped. This restarts Ring Oscillator crystal oscillator resume from <500µA operation.
Wakeup Mask Register Table Wakeup Mask Register WU_MSK_1 (Note (0x7F2B RESET=0x07 NAME [7:3] Reserved USB_Reset WAKEUP MASK DESCRIPTION Reserved External wakeup event. Enabled Masked External wakeup event. Enabled Masked Reserved
Resume
Reserved
Note Interrupt events enabled these bits routed PWR_MNG ISR_1 register. Note Only high transitions associated inputs sets these bits. Note These bits cleared each time this register read Note Unmasked Wakeup Source bits generate INT1 PWR_MNG interrupt, restart 8051 when clock stopped. This restarts Ring Oscillator crystal oscillator resume from <500µA operation.
RUNTIME REGISTERS
Ethernet Transmit Control Register1 Table Ethernet Transmit Control Register1 ETCR1 (0x7FD0 RESET=0x00) Ethernet Transmit Control Register NAME DESCRIPTION PAD_EN When set, USB97C196 will transmit frames shorter than bytes with Does frames when reset. [6:4] Reserved Reserved PHY_SPEED This configures SMSC USB97C196 operate 1Mbps Ethernet rate 1Mbps 10Mbps FORCOL When USB97C196 monitors carrier while transmitting. must carrier preamble. seen, carrier lost during transmission, transmitter aborts frame without turns itself off. When this clear transmitter ignores carrier. Defaults low. LOOP Local Loopback. When set, transmit frames internally looped receiver after encoder/decoder. Collision Carrier Sense ignored. data sent out. Defaults normal
ETCR1 (0x7FD0 RESET=0x00) NAME TXENA
Ethernet Transmit Control Register DESCRIPTION mode. Transmit enabled when set. Transmit disabled clear. When cleared USB97C196 will complete current transmission before stopping. When stopping error, this automatically cleared.
Ethernet Transmit Control Register2 Table Ethernet Transmit Control Register2 ETCR2 (0x7FD1 RESET=0x00) Ethernet Transmit Control Register NAME DESCRIPTION [7:6] Reserved Reserved LOOP Internal loopback block. Does exercise encoder decoder. Serial data looped back when set. Defaults low. Note: After exiting loopback test, SRESET ECOR SOFT_RST must before returning normal operation. Stop transmission SQET error. set, stops disables SQET transmitter test error. Does stop SQET error transmits next frame clear. Defaults low. Reserved Reserved MON_ When USB97C196 monitors carrier while transmitting. must carrier preamble. seen, carrier lost during transmission, transmitter aborts frame without turns itself off. When this clear transmitter ignores carrier. Defaults low. Reserved Reserved NOCRC Does append transmitted frames when set, allows software insert desired CRC. Defaults zero, namely inserted.
STATUS REGISTER1 Table STATUS REGISTER1 EPH1 (0x7FD2 RESET=0x00) NAME TX_DEFR STATUS REGISTER1 DESCRIPTION Transmit Deferred. When set, carrier detected during first usec inter frame gap. Cleared every packet sent.
EPH1 (0x7FD2 RESET=0x00) NAME LTX_BRD SQET
16COL
LTX_MULT MUL_COL
SNGL_COL
TX_SUC
STATUS REGISTER1 DESCRIPTION Last transmit frame broadcast. frame broadcast. Cleared start every transmit frame. Signal Quality Error Test. transmitter opens window after transmission completed receiver returns inactive. During this window, transmitter expects SQET signal from transceiver. absence this signal 'Signal Quality Error' reported this status bit. Transmission stops STP_SQET also when SQET set. This cleared setting TXENA high. collisions reached. when collisions detected transmit frame. TXENA reset. Cleared when TXENA high. Last transmit frame multicast. frame multicast. Cleared start every transmit frame. More than collision occurred while transmitting current Ethernet Packet. Cleared start every transmit frame. Single collision detected last transmit frame. when collision detected. Cleared when TX_SUC high packet being sent. Last transmit successful. transmit completes without fatal error. This cleared start frame transmission when TXENA high. Fatal errors are: collisions SQET fail STP_SQET FIFO Underrun Carrier lost MON_CSN Late collision
STATUS REGISTER2 Table STATUS REGISTER2 EPH2 (0x7FD3 RESET=0x00) STATUS REGISTER2 NAME DESCRIPTION Transmit Under run. Under occurs, also clears UNRN TXENA TCR. Cleared setting TXENA high. This should never under normal operation. LINK_ State 10BASE-T Link Integrity Test. transition value this generates interrupt when ENABLE Control Register set.
EPH2 (0x7FD3 RESET=0x00) NAME OVRN
_ROL _DEF LOST CARR
LATCOL
Reserved
STATUS REGISTER2 DESCRIPTION Upon FIFO overrun, receiver asserts this clears FIFO. receiver stays enabled. After valid preamble been detected subsequent frame, RX_OVRN deasserted. RX_OVRN Interrupt Status Register will also stay until cleared CPU. Note that receive overruns could occur only receive memory allocations fail. Counter Roll over. When more counters have reached maximum count (15). Cleared reading register. Excessive deferral. When last/current transmit deferred more than 1518 byte times. Cleared every packet sent. Lost carrier sense. When indicates that Carrier Sense present preamble. Valid only MON_CSN enabled. This condition causes TXENA reset. Cleared setting TXENA TCR. Late collision detected last transmit frame. late collision detected (later than byte times into frame). When detected transmitter JAMs turns itself clearing TXENA ETCR. Cleared setting TXENA ETCR. Reserved Read
Ethernet Receive Control Register Table Ethernet Receive Control Register RCR1 (0x7FD4 RESET=0x00) RECEIVE CONTROL REGISTER1 NAME DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ALMUL When set, accepts multicast frames (frames which first '1'). When clear accepts only multicast frames that match multicast table setting. Defaults low. PRMS Promiscuous mode. When receives frames. This receive frame aborted length longer ABORT than 1532 bytes. frame will received. cleared RESET 8051 embedded controller writing low.
Ethernet Receive Control Register Table Ethernet Receive Control Register RCR2 (0x7FD5 RESET=0x00) RECEIVE CONTROL REGISTER2 NAME DESCRIPTION SOFT Software activated CSMA/CD Block Reset. Active high. Initiated writing this high terminated writing low. USB97C196 configuration preserved, except Configuration Registers. FILT Filter Carrier. When filters leading edge carrier sense times. Otherwise recognizes receive frame soon carrier sense active. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved STRIP When strips received frames. When clear stored memory following packet. Defaults low. RXEN Enables receiver when set. cleared, completes receiving current frame then goes idle. Defaults reset.
Ethernet Counter Register1 Table Ethernet Counter Register1 ECR1 (0x7FD6 RESET=0x00) Ethernet Counter Register1 NAME DESCRIPTION Four counter number multiple collisions. [7:4] MULTIPLE COLLISION COUNT Four counter number Single Collisions [3:0] SINGLE COLLISION COUNT Each four counter incremented every time corresponding event, defined STATUS REGISTER description, occurs. Note that counters only increment once enqueued transmit packet, never faster, limiting rate interrupts that generated counters. example packet successfully transmitted after collision SINGLE COLLISION COUNT field incremented one. packet experiences between collisions, MULTIPLE COLLISION COUNT field incremented one. packet experiences deferral NUMBER DEFERRED field incremented one, even packet experienced multiple deferrals during collision retries. COUNTER REGISTER facilitates maintaining statistics AUTO RELEASE mode where transmit interrupts generated successful transmissions. Reading register transmit service routine will enough maintain statistics.
Ethernet Counter Register2 Table Ethernet Counter Register2 ECR2 (0x7FD7 RESET=0x00) Ethernet Counter Register2 NAME DESCRIPTION Four counter number excessive deferred transmit [7:4] NUMBER packets EXC. DEFERRED [3:0] NUMBER Four counter number deferred transmit packets DEFERRED
Ethernet Configuration Register Table Ethernet Configuration Register EConfigR1 (0x7FD8 RESET=0x00) Ethernet Configuration Register NAME DESCRIPTION ENABLE Link Error Enable. When enables ENABLE LINK_OK transition interrupts merged into bit. Defaults (disabled). Writing this also serves acknowledge clearing previous LINK interrupt conditions. ENABLE Counter Roll over Enable. When enables ENABLE CTR_ROL interrupts merged into bit. Defaults (disabled). ENABLE Transmit Error Enable. When enables ENABLE Transmit Error interrupts merged into bit. Defaults (disabled). Transmit Error condition that clears TXENA with TX_SUC staying described EPHSR register. RCV_BAD RCV_BAD When (1), packets received. When clear packets generate interrupts their memory released. LINK DISABLE LINK This used disable 10BASE-T link test functions. When this high USB97C196 disables link test functions generating monitoring network link pulses. this mode USB97C196 will transmit packets regardless link test, EPHSR LINK_OK will LINK will stay When link test functions enabled. link status indicates FAIL, EPHSR LINK_OK will low, while transmit packets enqueued will processed USB97C196, transmit data will sent cable.
EConfigR1 (0x7FD8 RESET=0x00) NAME FULL STEP
SQLCH SELECT
Ethernet Configuration Register DESCRIPTION FULL STEP This used select signaling mode port. When port uses full step signaling. Defaults half step signaling. This only meaningful when SELECT high. SQLCH When set, squelch level used 10BASET receive signal 240mV. When clear receive squelch level 400mV. Defaults low. SELECT When interface used, when clear 10BASE-T interface used. Defaults low.
Ethernet Configuration Register Table Ethernet Configuration Register EConfigR2 (0x7FD9 RESET=0x00) Ethernet Configuration Register NAME DESCRIPTION [7:2] Reserved Reserved CLK_DISABLE When suspend mode, stop 20MHz clock Ethernet disable ENDEC Ethernet AUTO AUTO RELEASE When cleared (0), transmit pages RELEASE released transmit completion transmission successful (when TX_SUC set). that case there status word associated with packet number, successful packet numbers even written into COMPLETION FIFO. sequence transmit packets will only generate interrupt when sequence completely transmitted EMPTY will set), when packet sequence experiences fatal error will set). Upon fatal error TXENA cleared transmission sequence stops. packet number that failed present FIFO PORTS register, pages released, allowing restart sequence after corrective action taken.
INDIVIDUAL ADDRESS REGISTER These registers should initialized 8051 firmware upon hardware reset. values these registers must unique each system this device designed into. result, data stored FLASH downloaded from Host Device Class descriptor. option application specific. Table INDIVIDUAL ADDRESS REGISTER IAR0 INDIVIDUAL ADDRESS REGISTER (0x7FDA RESET=0x00) NAME DESCRIPTION [7:0] IAR[0] byte value byte Ethernet Address Individual Address register corresponds first address cable. Table INDIVIDUAL ADDRESS REGISTER IAR1 INDIVIDUAL ADDRESS REGISTER (0x7FDB RESET=0x00) NAME DESCRIPTION [7:0] IAR[1] byte value byte Ethernet Address Table INDIVIDUAL ADDRESS REGISTER IAR2 (0x7FDC RESET=0x00) INDIVIDUAL ADDRESS REGISTER NAME DESCRIPTION [7:0] IAR[2] byte value byte Ethernet Address Table INDIVIDUAL ADDRESS REGISTER IAR3 (0x7FDD RESET=0x00) INDIVIDUAL ADDRESS REGISTER NAME DESCRIPTION [7:0] IAR[3] byte value byte Ethernet Address Table INDIVIDUAL ADDRESS REGISTER IAR4 (0x7FDE RESET=0x00) NDIVIDUAL ADDRESS REGISTER NAME DESCRIPTION [7:0] IAR[4] byte value byte Ethernet Address Table INDIVIDUAL ADDRESS REGISTER IAR5 (0x7FDF RESET=0x00) INDIVIDUAL ADDRESS REGISTER NAME DESCRIPTION [7:0] IAR[5] byte value byte Ethernet Address
Table MULTICAST TABLE REGISTER MCT0 (0x7FE0 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[0] Multicast Table Register Table MULTICAST TABLE REGISTER MCT1 (0x7FE1 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[1] Multicast Table Register Table MULTICAST TABLE REGISTER MCT2 (0x7FE2 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[2] Multicast Table Register Table MULTICAST TABLE REGISTER MCT3 (0x7FE3 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[3] Multicast Table Register Table MULTICAST TABLE REGISTER MCT4 (0x7FE4 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[4] Multicast Table Register Table MULTICAST TABLE REGISTER MCT5 (0x7FE5 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[5] Multicast Table Register Table MULTICAST TABLE REGISTER MCT6 (0x7FE6 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[6] Multicast Table Register
Table MULTICAST TABLE REGISTER MCT7 (0x7FE7 RESET=0x00) MULTICAST TABLE REGISTER NAME DESCRIPTION [7:0] MCT[7] Multicast Table Register multicast table used group address filtering. hash value defined most significant bits destination addresses. three msb's hash value determine register used (MCT0-7), while three lsb's determine within register. appropriate table set, packet received. ALMUL RCR1 register set, multicast addresses received regardless multicast table values. Hashing only partial group addressing filtering scheme, being hash value available part receive status word, receive routine reduce search time significantly. With proper memory structure, search limited comparing only multicast addresses that have actual hash value question.
MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTIONS
embedded 8051 processor support both Ethernet transmission reception packets will access registers described below. Following Diagrams describe register control blocks Ethernet Transmission reception. registers described defined next section.
8051
USB_RX_FIFO
USB_RX_FIFO_Len
ETH_RX_FIFO
ETH_RX_FIFO_Low ETH_RX_FIFO High
USB_RX_FIFO_Length High
FIFO Deep)
Packet Number Packet Number Address
Ethernet FIFO Deep)
CSMA/CD
Auto Inc. Address
MMU_DATA
Address
Addr Counter
Pointer (PRL, PRH)
Latch
PNR/RX MCU/LAN/SIE
Arbiter
Logical Address
Packet
Latch
Status/Data
Ethernet Receive FIFO Control Logic
Status/Data Select
Logical Packet Address Logical Address Packet
Status
Data
8051
USB_POP_TX_Don Reg.
USB_POP_TX Reg.
PNBCR
(SIE/ETH)
ETH_POP_TX Reg.
ETH_POP_TX_Done Reg.
USB_TXSTAT
MMUTX_SEL
FIFO SELECT
wide FIFO's
FIFO Deep)
Completion (Done) FIFO Deep)
Ethernet Data Window Register This register used allow embedded processor (8051 CORE) read write access data buffers presently addressed pointer register Packet Number Register. This register mapped into uni-directional FIFOs that allow moving bytes from regardless whether pointer address even odd. Data goes through write FIFO into memory, pre-fetched from memory into read FIFO. Table Data Window Register MMU_DATA (0x6000) NAME [D7:D0] DATA WINDOW REGISTER DESCRIPTION Data Packet Window. When register '1', this byte pointed packet number RXFIFO selected MMUCR register, packet offset PRH:PRL. When register '0', this byte pointed packet number register, packet offset PRH:PRL.
FIFO
Ethernet Transmit FIFO Control Logic
FIFO
FIFO Control
FIFO
FIFO
FIFO
FIFO
Ethernet FIFO Control
Ethernet Completion (Done) FIFO Deep)
[7:0]
Ethernet Pointer Register (Low) Table Pointer Register (Low) (0x7F50) NAME A[7:0] POINTER REGISTER (LOW) DESCRIPTION (0-1536 Max) offset allocated Packet Pointed PNR. byte(s) pointed this register read written 0x6000.
[7:0]
Ethernet Pointer Register (High) This High byte portion Pointer Register. Under normal operation, embedded 8051 should load byte first high byte last. When set, address refers receive area uses output either Ethernet FIFO packet number. When cleared, address refers transmit area either Ethernet FIFO uses packet number (Packet Number Register). READ determines type access follow. READ high, operation intended read. READ operation write. Loading pointer value, with READ high, generates pre-fetch into Data Register read purposes. Reading back pointer will indicate value address last accessed 8051 (rather than last pre-fetched). This allows interrupt routine that uses pointer, save restore without affecting process being interrupted. Pointer Register should loaded until 400ns after last write operation Data Register ensure that Data Register FIFO empty. Table Pointer Register (High) (0x7F51) NAME POINTER REGISTER (HIGH) DESCRIPTION packet 0x6000 packet pointed register. packet 0x6000 packet pointed packet number Packet Number FIFO selected MMUCR register. Auto-increment disabled Causes PRH:PRL register automatically incremented each time 0x6000 data window accessed.
AUTO_INCR
(0x7F51) NAME READ
POINTER REGISTER (HIGH) DESCRIPTION Data register direction. This required MMU/Arbiter provide transparent interface buffer MCU. When first set, immediately fills read FIFO. must wait 2.5us Arbiter clocks) after writing MMU_DATA register before changing this from '1'. WRITE READ STATUS/DATA Control Select This selects whether 8051 accessing STATUS HEADER DATA area MMU's allocated buffer pointer (Packet Number Register). Status Buffer Data Buffer Reserved (0-1277 Max) offset allocated Packet Pointed PNR. byte(s) pointed this register read written 0x6000.
STATUS/DATA
[2:0]
Reserved A[10:8]
Transmit FIFO Select Register This register selects which FIFO's (one FIFO each associated Endpoint) selected when embedded 8051 processor enqueueing packet into FIFO's transmission Host.
Table Transmit FIFO Select Register MMUTX_SEL (0x7F52) NAME Reserved EP[2:0] TRANSMIT FIFO SELECT REGISTER DESCRIPTION Reserved This register selects which Endpoint Control Block terms Command Register (0x7F53) Commands "110" "111" will affect when issued MMU. Command Register details.
[7:3] [2:0]
Command Register This register used embedded 8051 controller control memory allocation, de-allocation, FIFO FIFO control MMU. three command bits determine command issued described below: Table Command Register MMUCR (0x7F53) NAME MMU_CMD SIE/EPH COMMAND REGISTER DESCRIPTION MMUCR COMMAND SIE/Ethernet Control Select This bit, when will allow execute Command, defined above targeted SIE. When this cleared (0), will allow execute command targeted Ethernet EPH. When these bits read, number byte Pages allocated following formula (N(3:0) bytes. example, value N[3.0]=0000, indicates page, value N[3.0]=1011 indicates pages, 1536 bytes. When this read, this indicates that either busy allocating memory completed command. Busy Completed (successful)
[7:5]
[3:0]
N[3:0]/Busy
COMMAND Bits Description: NOOP, operation This operation will executed when 8051 needs switch between Ethernet FIFO's. Allocate Memory N3-0 specifies many byte pages allocate Ethernet packet pages allowed (1536 bytes) packet.). Writing this command this register, Immediately generates "FAILED" code code cleared when allocation complete. This command generate ALLOC interrupt upon completion. When allocation request cannot completed insufficient memory, FAILED will remain set. subsequent release memory pages either MMUCR, engine SIEDMA) will cause MMUCR automatically continue allocate command until requested pages have been successfully allocated. firmware software should never issue another allocate command until previous allocate command been successfully completed. allocation time take worst case (N[3:0] 200ns. RESET Frees buffer RAM, clears interrupts, resets queue pointers. Remove Packet from Queue issued after completed processing packet number RXFIFO. This command removes receive packet number from FIFO brings next receive frame any) area (output FIFO). Remove Release FIFO Same (011), also frees memory used packet presently FIFO output. This command especially useful quick "ignore" packets. Release specific Packet Frees pages allocated packet specified (PACKET NUMBER REGISTER). This command should used frames pending transmission. This
command typically used remove transmitted frames from Done FIFO, after reading their completion status. Enqueue Packet into Endpoint EP[3:0] Ethernet FIFO: Places Packet number indicated register transmit queue endpoint pointed MMUTX_SEL register. MMUTX_SEL register must written before this command issued. Reset Endpoint EP[3:0] Ethernet FIFO Resets associated FIFO holding packet numbers awaiting transmission TXFIFO_STAT bits endpoint pointed MMUTX_SEL register. MMUTX_SEL register must written before this command issued. This command does release memory allocated packets that dequeued. Only command "001" uses bits through When using Reset Endpoint EP[3:0] Ethernet FIFO command, responsible releasing memory associated with outstanding packets, re-enqueuing them. Packet numbers completion FIFO read FIFO ports register before issuing command. commands releasing memory should only issued corresponding packet number memory allocated Commands through require USB/ETH control appropriately since command access Ethernet related FIFOs Command Sequencing
Note Note
Note Note
second allocate command (command should issued until present completed. Completion determined reading FAILED allocation result register through allocation interrupt. second release command should issued previous still being processed. BUSY indicates that release command progress. After issuing command contents shouldnot changed until BUSY goes low. After issuing command command should issued until BUSY goes low. BUSY Readable command register address. When set, indicates that still processing release command. When clear, already completed last release command. BUSY FAILED bits upon trailing edge command.
Allocation Result Register This register updated upon ALLOCATE MEMORY command. Table Allocation Result Register (0x7F54) NAME FAILED ALLOCATION RESULT REGISTER DESCRIPTION FAILED zero indicates successful allocation completion. allocation fails, only cleared when pending allocation satisfied. This defaults high, upon reset reset command. polling purposes, ALLOC_INT Interrupt Status Register should used because synchronized read operation. Sequence: Allocate Command Poll ALLOC_INT until Read Allocation Result Register Reserved Packet number associated with last memory allocation request. value only valid FAILED clear. Returns Packet Number (0-31, 0x00-0x1F) from allocation command. This written directly into register
[6:5] [4:0]
Reserved P[4:0]
Note:
value read from after allocation request intended written into without masking higher bits (provided FAILED Packet Number Byte Count Registers
value written into registers defined below determines which packet number accessible through area. Also included Byte Length Ethernet Packet. Some commands number stored this register packet number parameter. This register cleared RESET RESET Command. Packet Number Register value written into this register determines which packet number accessible through ETHERNET area. Some commands number stored this register packet number parameter. This register cleared RESET RESET Command. Table Packet Number Register PACKET NUMBER REGISTER DESCRIPTION Reserved Packet selector access packet 0x6000 buffer window
[7:5 [4:0]
(0x7F55) NAME Reserved P[4:0]
Byte Count Register High Table Packet Number Byte Count Register High PNBCRL (0x7F63) PACKET NUMBER Byte Count REGISTER High NAME DESCRIPTION Reserved Reserved PacketByteCnt PacketByteCnt High Three bits Packet Byte Count
[7:3] [2:0]
Byte Count Register Table Byte Count Register PNBCRH (0x7F62) PACKET NUMBER Byte Count REGISTER NAME DESCRIPTION PacketByteCnt PacketByteCnt bits Packet Byte Count
[7:0]
Byte Count Conversion Registers eight registers defined below used convert between Ethernet Byte count values. (8051) writes received packet length into these registers which will convert value appropriate. MCU(8051) then read converted length. Ethernet USB: Ethernet packet received EPH. Ethernet packet length always even. Ethernet Data Packet Control Byte (1), actual packet length hardware packet length Therefore, PNCR High byte should set. Ethernet Data Packet Control Byte clear (0), actual packet length hardware packet length Therefore, PNCR High byte should cleared. ETH2USB must (1). registers written with packet length received from packet length FIFO register bits defined above. When this register read, value registers should value written into FIFO packet length.
Ethernet: packet received from SIE. packet exact packet length. ETH2USB must cleared (0). PNCR High byte don't care. registers written with packet length received from packet length FIFO register bits defined above. When this register read, value registers should value written into FIFO packet length.
Byte Count Conversion Register High Table Byte Count Conversion Register High PNCRH (0x7F6D) PACKET NUMBER Byte Count REGISTER High NAME DESCRIPTION ETH2USB ETH2USB This selects whether conversion Ethernet buffer transfers Ethernet Buffer transfers. ETH2USB Ethernet Conversion ETH2USB Ethernet Conversion ODD/EVEN ODD/EVEN This controls ODD/EVEN control byte Ethernet Data Buffer Conversion. When set(1), indicates odd; when clear(0), indicates even. Reserved Reserved PacketByteCnt PacketByteCnt High Three bits Packet Byte Count
[5:3] [2:0]
Byte Count Conversion Register Table Byte Count Conversion Register PNCRL (0x7F6C) PACKET NUMBER Byte Count REGISTER NAME DESCRIPTION PacketByteCnt PacketByteCnt Eight bits packet Byte Count
[7:0]
Ethernet Registers registers described below allow 8051 manage Ethernet transmit FIFO's. FIFO's operate possible modes. first mode Automatic manage release mode. this mode, SMSC USB97C196 will manage completion removal transmit buffers upon transmit completion automatically. buffers removed placed into free buffer area MMU. This mode offers most efficient method buffer management recommended mode operation. second mode manual release removal. this mode, 8051 manage done FIFO's manually, using registers defined below. This method allows MCU's firmware more flexibility memory management, which viable option particular application. FIFO Register This register used help software manage Queues. This will provide method handle "CLEAR_FEATURE:ENDPOINT_STALL" condition gracefully. When read, this register will return Packet Number next packet waiting queue pointed MMUTX_SEL register, will that Packet Number selected FIFO.
Table -USB FIFO USB_POP_TX (0x7F64 RESET=0x80) NAME POPTX_STAT FIFO DESCRIPTION FIFO empty status more packet Empty Reserved This value packet number handle that FIFO pointer MMUTX_SEL. FIFO popped when this register read.
[6:5] [4:0]
Reserved POP_TX
Note:
software's responsibility ensure that appropriate disabled during this operation, issue deallocate command desired.
Done FIFO Register This register used help software manage Queues. packets transmitted pushed onto this FIFO regardless state Auto Release Management Register. When read, this register will return Packet Number next packet Done queue, will that Packet Number selected DONE FIFO. Table -USB DONE FIFO Register USB_POP_TX_DONE (0x7F65 RESET=0x80) DONE FIFO NAME DESCRIPTION POPTX_STAT DONE FIFO empty status more packet Empty FULL When this (1), FIFO Full. When Clear (0), FIFO Full Reserved Reserved [4:0] POP_TX This value packet number handle that DONE FIFO pointer MMUTX_SEL. DONE FIFO popped when this register read. Note: software's responsibility ensure that appropriate disabled during this operation, issue deallocate command desired. Ethernet Awaiting FIFO Register This register used help 8051 manage Ethernet Queues. This will provide method handle waiting Ethernet packet packet numbers Auto Release feature used. When read, this register will return Packet Number next packet waiting Awaiting queue. Reading this register effect contents FIFO when this register read MCU.
Table Ethernet Awaiting FIFO Eth_TX_Awaiting (0x7F66 RESET=0x80) NAME TX_Awaiting_ Stat [6:5] [4:0] Reserved TX_Awaiting_ Value Eth_TX_Awaiting DESCRIPTION FIFO empty status more packet Empty Reserved This value packet number handle that FIFO. FIFO popped when this register read.
Ethernet Done FIFO Register This register used help software manage Ethernet Queues. This will provide method handle completed Ethernet packet packet numbers Auto Release feature used. When read, this register will return Packet Number next packet waiting Completed queue will that Packet Number FIFO. programs SMSC USB97C196 implement "Auto Release", responsibility manually release packet from memory. Table Ethernet Done FIFO Eth_POP_TX_Done (0x7F67 RESET=0x80) NAME POPTXDone_ STAT [6:5] [4:0] Reserved POPDone_TX Eth_POP_TX_Done DESCRIPTION FIFO empty status more packet Empty Reserved This value packet number handle that Done FIFO. Done FIFO popped when this register read. MEMORY INFORMATION REGISTER Table MEMORY INFORMATION REGISTER MEMORY INFORMATION REGISTER (0x7F56 RESET=0x20) NAME DESCRIPTION [5:0] FREE PAGES FREE PAGES AVAILABLE This register read AVAILABLE time determine amount free pages available. register defaults 0x20 upon reset upon RESET command. (Page size bytes)
Receive Data Packet Number Length FIFO Registers These registers, when read, will retrieve from packet number pointing received data buffers Packet Number, Packet Length processing. This packet which come Point will then forwarded Ethernet CSMA/CD engine forwarded onto Ethernet network under normal operation. Receive Packet Number FIFO Register Table Receive Packet Number FIFO Register USB_RX_FIFO (0x7F58) Receive Packet Number FIFO Register NAME DESCRIPTION Empty This when Packet Number FIFO empty Full This when Packet Number FIFO Full Bulk When this (1), indicates that packet received from Bulk endpoint (3). When this cleared (0), indicates that packet Non-Bulk (control general purpose) endpoint. This register allows 8051 determine this dedicated Bulk Endpoint result does need read packet Status header. Packet_Number Packet Number When packet been received, 8-byte header been written SIEDMA, associated Packet Number placed this FIFO.
[4:0]
Receive FIFO Packet Length Register Table Receive FIFO Packet Length Register USB_RX_FIFO_Length_Low (0x7F59) Receive FIFO Packet Length Register NAME DESCRIPTION [7:0] RX_FIFO_Length This register defines lower packet size Bytes) _Low packets received from Receive FIFO Packet Length Register High Table Receive FIFO Packet Length Register High USB_RX_FIFO_Length_High (0x7F5A) Receive FIFO Packet Length Register High NAME DESCRIPTION [2:0] RX_FIFO_Length This register defines higher packet size Bytes) _High packets received from
Ethernet Receive Data Packet Number Length FIFO Registers These registers, when read, will retrieve from packet number pointing received data buffers Packet Number, Packet Length processing. This packet which come Ethernet Receive Block will then forwarded 8051 control forwarded onto under normal operation. ETHERNET Receive Packet Number FIFO Register Table Ethernet Receive Packet Number FIFO Register Ethernet_RX_FIFO (0x7F5B) ETHERNET Receive Packet Number FIFO Register [4:0] NAME Empty Full Reserved Packet_Number DESCRIPTION This when Packet Number FIFO empty. This when Packet Number FIFO Full (Note: this required since FIFO will deep). Reserved Packet Number When packet been received, 8-byte header been written SIEDMA, associated Packet Number placed this FIFO.
ETHERNET Receive FIFO Packet Length Register Table ETHERNET Receive FIFO Packet Length Register RX_FIFO_Length_Low (0x7F5C) ETHERNET Receive FIFO Packet Length Register NAME DESCRIPTION [7:0] RX_FIFO_Length This register defines lower packet size Bytes) _Low packets received from ETHERNET Block ETHERNET Receive FIFO Packet Length Register High Table ETHERNET Receive FIFO Packet Length Register High RX_FIFO_Length_High (0x7F5D) ETHERNET Receive FIFO Packet Length Register High NAME DESCRIPTION [2:0] RX_FIFO_Length This register defines higher packet size Bytes) _High packets received from ETHERNET Note: Ethernet Byte Counts derived from block always even. odd/even determination Ethernet packet received must determined ODD/EVEN Control word Ethernet Receive packet buffer. Refer Ethernet Data buffer description following sections.
Transmit FIFO Status Registers Transmit FIFO Status Register Table Transmit FIFO Status Register USB_TXSTAT_A (0x7F60 RESET=0xAA) TRANSMIT FIFO STATUS REGISTER NAME DESCRIPTION EP3TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [7:6]='11' Invalid Bits [7:6]='10' Empty Packets queued) Bits [7:6]='01' Full Packets queued) Bits [7:6]='00' Partially Full Packets queued) EP3TX_FULL EP2TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [5:4]='11' Invalid Bits [5:4]='10' Empty Packets queued) Bits [5:4]='01' Full Packets queued) Bits [5:4]='00' Partially Full Packets queued) EP2TX_FULL EP1TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [3:2]='11' Invalid Bits [3:2]='10' Empty Packets queued) Bits [3:2]='01' Full Packets queued) Bits [3:2]='00' Partially Full Packets queued) EP1TX_FULL EP0TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [1:0]='11' Invalid Bits [1:0]='10' Empty Packets queued) Bits [1:0]='01' Full Packets queued) Bits [1:0]='00' Partially Full Packets queued) EP0TX_FULL
Transmit FIFO Status Register Table Transmit FIFO Status Register USB_TXSTAT_B (0x7F61 RESET=0x0A) TRANSMIT FIFO STATUS REGISTER NAME DESCRIPTION [7:4] Reserved Reserved EP5TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [3:2]='11' Invalid Bits [3:2]='10' Empty Packets queued) Bits [3:2]='01' Full Packets queued) Bits [3:2]='00' Partially Full Packets queued) EP5TX_FULL EP4TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [1:0]='11' Invalid Bits [1:0]='10' Empty Packets queued) Bits [1:0]='01' Full Packets queued) Bits [1:0]='00' Partially Full Packets queued) EP4TX_FULL
Management Register Table Management Register TX/RX_MGMT (0x7F57 RESET= 0x00) TX/RX Management Register NAME DESCRIPTION [7:4] Reserved Reserved Read zero SIE_RCV_Bad Receive This when (1), will allow bulk transactions received that have Invalid CRC. When this cleared (0), will receive bulk packet that invalid CRC. Nack_all_RX Nack received packets Normal Operation (Default) NACK packets Firmware NAK_ALLRX inhibit from asking SIEDMA allocate pages while observing page free bits.
TX/RX_MGMT (0x7F57 RESET= 0x00) NAME nUSB_auto_Gen _Zero
TX/RX Management Register DESCRIPTION Auto Generate Zero Length Packets Upon termination sequence Bulk packets logical Ethernet Packet, SMSC USB97C196 will generate Zero length packet when Logical length multiple (USB Bulk Length). When this cleared (0), zero length packets Automatically transmitted Bulk String (logical Ethernet packet) length multiple When this (1), Zero Length Packets need allocated manually being into Bulk FIFO immediately after prior Bulk packet enqueued. Automatic Memory de-allocate Mode Auto Memory buffer de-allocation Manual de-allocation, FIFO still automatic. This control selects between Auto Manual memory pages de-allocation. This should statically start operation, changed during about transmit. This should default normal operation. When set, handles freeing memory pages.
USB_auto_ Release
PACKET HEADER DEFINITION
following headers contain information determine status length Ethernet received transmit packets. These headers used both Ethernet CSMA/CD engine respectively. fields different Ethernet control there also differentiation when they used USB/Ethernet transmission reception. Receive Frame Status Double Word Packet RAM. Offset Status double word used obtain additional information relating Bulk packet received USB97C196. Frame Counter [15:0] This word value determines number SOF's (Start frames) since device been reset. This information used determine Isochronious timing information. PACKET ID[3.0] This value shows value current received packet. Bad_CRC- This determines current received packet invalid CRC. This only Receive Management Register
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION
Packet Header Definition following header contains information determine endpoint, status, payload "received data". (Length received packet obtained from Received FIFO Packet Length Registers High Low).
OFFSET 0x005 0x004 0x003 0x002 0x001 0x000
Table Packet Header Definition EXTENDED FRAME COUNT[15.11] FRAME COUNT[10.8] FRAME COUNT[7.0] RESERVED TMP_ADDRESS[6.0] PACKET ID[3.0] Bad_CRC Last_TOG Same_TOG ENDPOINT[3.0]
Packet Description: Offset packet header. Offset 0x000 0x005 generated SIE. Offset 0x000, Same_TOG This when receives same toggle that received previous packet. This necessarily error condition, This could indicate condition when return handshake packet lost. Note that Same_TOG isochronous transfers. Last Packet Toggle Value iii) Current Packet Toggle Value "SAME TOG"
Offset 0x000 Last_TOG last toggle received. Offset 0x000 Bad_CRC, when detects CRC.
Ethernet Transmit Receive packet Status definition table shown below defines structure packet buffer when Ethernet packet received transmitted. Table Ethernet/USB Transmit Receive packet buffer definition Status (Buffer) Status Offset (Decimal) Ethernet Status Byte Ethernet Status Byte High Ethernet RECEIVE FRAME STATUS WORD This word, bytes, written beginning each receive frame memory. available register. This information normally required under normal operations. This information available 8051 Embedded processor informational diagnostic content.
Status Byte Status Byte High
ALGN
BROD CAST
BADCRC
ODDFRM
TOOLNG
SHORT
HASH VALUE
MULT CAST
ALGNERR Frame alignment error. BRODCAST Receive frame broadcast. BADCRC Frame error. ODDFRM This when indicates that received frame number bytes. TOOLNG received frame longer than 802.3 maximum size (1518 bytes cable). TOOSHORT received frame shorter than 802.3 minimum size bytes cable).
HASH VALUE Provides hash value used index Multicast Registers. used receive routines speed group address search. hash value consists most significant bits calculated Destination Address, maps into multicast table. Bits 5,4,3 hash value select byte multicast table, while bits 2,1,0 determine within byte selected. Examples address mapping shown table below: ADDRESS HASH VALUE MULTICAST TABLE MT-0 MT-2 MT-4 MT-7
MULTCAST Receive frame multicast. hash value corresponds multicast table that set, address multicast, packet will pass address filtering regardless other filtering criteria. Ethernet Transmit FRAME STATUS WORD Status RAM) This byte value, stores transmit status upon individual transmit packet completion. Packet interrupt processing should this copy status information, needed. value stored these bytes copies status register. This status word "Snap Shot" CSMA/CD transmit status associated packet. status register will updated subsequent packet transmissions. Status register used real time values (like TXENA LINK OK). Status Byte Status Byte High
UNRN DEFR
LINK_
OVRN
_ROL
_DEF MULT
LOST CARR
LATCOL SNGL
SQET
16COL
TX_SUC
TXUNRN Transmit Under run. Under occurs, also clears TXENA TCR. Cleared setting TXENA high. This should never under normal operation. LINK_OK State 10BASE-T Link Integrity Test. transition value this generates interrupt when ENABLE Control Register set. RX_OVRN Upon FIFO overrun, receiver asserts this clears FIFO. receiver stays enabled. After valid preamble been detected subsequent frame, RX_OVRN de-asserted. RX_OVRN Interrupt Status Register will also stay until cleared CPU. Note that receive overruns could occur only receive memory allocations fail. CTR_ROL Counter Roll over. When more counters have reached maximum count (15). Cleared reading register. EXC_DEF Excessive deferral. When last/current transmit deferred more than 1518 byte times. Cleared every packet sent.
LOST_CARR Lost carrier sense. When indicates that Carrier Sense present preamble. Valid only MON_CSN enabled. This condition causes TXENA reset. Cleared setting TXENA TCR. LATCOL Late collision detected last transmit frame. late collision detected (later than byte times into frame). When detected transmitter JAMs turns itself clearing TXENA TCR. Cleared setting TXENA TCR. WAKEUP When this set, indicates that receive packet received that packet signature defined Packet Signature Control Registers. This indicates valid detection packet signature match. enabled WAKEUP_EN CTR. TX_DEFR Transmit Deferred. When set, carrier detected during first uSec inter frame gap. Cleared every packet sent. LTX_BRD Last transmit frame broadcast. frame broadcast. Cleared start every transmit frame. SQET Signal Quality Error Test. transmitter opens window after transmission completed receiver returns inactive. During this window, transmitter expects SQET signal from transceiver. absence this signal 'Signal Quality Error' reported this status bit. Transmission stops STP_SQET also when SQET set. This cleared setting TXENA high. 16COL- collisions reached. when collisions detected transmit frame. TXENA reset. Cleared when TXENA high. LTX_MULT Last transmit frame multicast. frame multicast. Cleared start every transmit frame. MULCOL Multiple collision detected last transmit frame. when more than collision experienced. Cleared when TX_SUC high packet being sent. SNGLCOL Single collision detected last transmit frame. when collision detected. Cleared when TX_SUC high packet being sent. TX_SUC Last transmit successful. transmit completes without fatal error. This cleared start frame transmission when TXENA high. Fatal errors are: collisions SQET fail STP_SQET FIFO Underrun Carrier lost MON_CSN Late collision
Ethernet Transmit Receive Packet Data definition
Data Packet payload format shown Table Ethernet Transmit Receive Packet Data Format page This layout memory similar TRANSMIT RECEIVE areas. data area holds packet itself. packet memory format, internally, word format, accesses byte mode. Table Ethernet Transmit Receive Packet Data Format Ethernet Transmit Receive Packet Data Format Data Payload Area Offset Offset Offset Offset Offset Offset Last Data Byte Length ODD) Offset Control Byte Table Ethernet Transmit Receive Control Data Byte functionality ,shown below, describes entity which sets modifies Data Packet Memory described Table Ethernet Transmit Receive Packet Data Format. Table Ethernet Transmit Receive Control Data Byte functionality TRANSMIT PACKET RECEIVE PACKET Written/modified created Written CSMA engine DATA AREA from Host packet packets. Written/modified created Written CSMA engine Last Data Byte from Host packet packets. Also CONTROL BYTE Written control ODD/EVEN Written CSMA. data bytes ODD/EVEN DATA AREA RAM) data area starts offset packet structure, extend 1536 bytes. data area contains bytes DESTINATION ADDRESS followed bytes SOURCE ADDRESS, followed variable length number bytes. transmit, bytes provided created from Host packet packets. later typically correct method however, also move data into packet buffer diagnostic special Ethernet packets. This also true source address. SMSC USB97C196 does insert source address. receive, bytes provided CSMA engine. 802.3 Frame Length word (Frame Type Ethernet) interpreted SMSC USB97C196. treated transparently data both transmit receive operations.
SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION
architecture SMSC USB97C196 such that there data FIFO's associated with individual endpoints. does differentiate packets endpoint number. firmware must read endpoint number from packet header pass packet appropriate endpoint handler. This makes chip dynamic flexible allocating buffers store payload size from 1023 bytes. Each endpoint configured separately following register(s) there USB97C196: Endpoint Control Registers Table Endpoint Control Registers EP_CTRL[5.0] (0x7F85-0x7F80 RESET=0x00) NAME TX_ISO
ENDPOINT CONTROL REGISTERS DESCRIPTION instructs handle handshakes transmit endpoints during "IN" transactions, SIEDMA engine should handle packet queue status after packet transmission. When endpoint configured isochronous operation (Bit '1'), packet transmissions considered successful SIEDMA must move packet number into Completion FIFO. When endpoint non-isochronous (Bit '0'), then must receive valid handshake from host before packet released. This guarantees data integrity non-isochronous transactions. Successfully transmitted packets automatically de-queued packet released. Non-Isochronous Isochronous instructs handle handshakes receive endpoints during "OUT" "SETUP" transactions. Once packet matches 7-bit Function Address, must begin page allocation generate packet buffer RAM. must check PID_Valid CRC_Valid bits dequeue "bad" packets. will inhibit handshakes when enabled. Non-isochronous Isochronous
RX_ISO
EP_CTRL[5.0] (0x7F85-0x7F80 RESET=0x00) NAME TX_CONT[1:0]
RX_CONT[1:0]
TX_TOGGLE
RX_TOGGLE
ENDPOINT CONTROL REGISTERS DESCRIPTION 0,0= Endpoint disabled, does send handshakes. 0,1= Send STALL handshake transaction directed this 1,0= Normal Operation. sent depending whether data EPXs TX_QUEUE. 1,1= Send handshake transaction directed this regardless TX_QUEUE status. (Note 0,0= Endpoint disabled, does send handshakes. 0,1= Send STALL handshake transaction directed this 1,0= Normal Operation. sent depending RX_OK status 1,1= Send handshake transaction directed this (Note This toggled after each successful transmission. TX_TOGGLE reset cleared must insure that endpoint disabled before modifying them. This reflects last DATA0/DATA1 toggle.
Note There Endpoint Control Register virtual endpoint. When decodes token, endpoint number used index which EP_CTRL register bits should used respond SIEDMA. Note These registers written time won't affected until after current transaction particular endpoint) completed. particular register written several times during transaction, only last value written will take effect after transaction. Note This allows firmware manage endpoint(s) hold queued data until firmware ready, even host asking. This critical version, required Isochronous synchronization, well STALL recovery. Note There Endpoint Control Register virtual endpoint. When decodes token, endpoint number used index which EP_CTRL register bits should used respond SIEDMA. Note These registers written time won't affected until after current transaction particular endpoint) completed. particular register written several times during transaction, only last value written will take effect after transaction.
NonControl Endpoint Register Section 8.4.5.4 Spec V1.1 states that non-control endpoint receives SETUP PID, must ignore transaction return response." order hardware this correctly, needs know which endpoints non-control endpoints. Each NonControl Endpoint register will correspond associated Endpoint. NonControl Endpoint register will correspond Endpoint will write these registers, corresponding bit=1 each endpoint that non-control endpoint. hardware will respond Setup endpoint whose corresponding (1). Table NonControl Endpoint Register NONCTRL_EP (0x7FAC RESET=0x00) NONCONTROL ENDPOINT REGISTER NAME DESCRIPTION Reserved Reserved This should written Reserved Reserved This should written When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID.
Endpoint Command Register conjunction with Endpoint Control Registers defined above, Endpoint Command Register allows dynamic modification configuration specific endpoints. This register which SMSC Family devices, which allows write each individual field within existing register Endpoint without having read modify write operations. Firmware this register with full constant, could OR-in number: This register allows individual setting clearing bits EP_CTRL registers. Table Endpoint Command Register EP_COMM (0x7FAA- RESET=0x00) ENDPOINT Command Register NAME DESCRIPTION TX/RX This bit, when will allow command specified bits control endpoint. When this cleared (0), command control endpoint. other words, (1), command will affect TX_ISO, TX_ENABLE, STALL_TXEP, TX_TOGGLE (defined EPCTRL). clear (0), command will affect RX_ISO, RX_ENABLE, STALL_RXEP, RX_TOGGLE (also defined EPCTRL). [6:4] COMMAND Command Bits Endpoint disabled, does send handshakes. Send STALL handshake (transmit) /OUT (Reception) transaction directed this Normal Operation. sent depending whether data EPXs TX_QUEUE RX_QUEUE. Send handshake IN/OUT transaction directed this regardless TX_QUEUE RX_QUEUE status. Clear Toggle Toggle Clear Endpoint Select Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Reserved Reserved Reserved
[3:0]
EP_Select
EP_COMM (0x7FAA- RESET=0x00) NAME Example:
ENDPOINT Command Register DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EP_CMD cEPCMD_RX_ cEPCMD_EP_BUSY_ c_EPCMD_EP3_; cEPCMD_EP3_ manifest constant EP_CMD cEPCMD_RX_ cEPCMD_EP_BUSY_ epNo; variable
epNo BYTE
Firmware implementing code structures this way, performance enhanced avoiding read modify write. There issue involving stepping wrong field, including toggles.
FRAME Count Register Table FRAME Count Register FRAMEL 0x7F90 Reset 0x00 FRAME COUNT REGISTER (LOW) NAME DESCRIPTION [7:0] FRAME[7:0] Frame Number from each packet loaded with RISING edge when SOF_TOKEN '1'. FRAME Count Register Table FRAME Count Register FRAMEH 0x7F91 Reset 0x00 NAME EXT_FR[15:11] FRAME COUNT REGISTER (HIGH) DESCRIPTION Extended Frame Count. extended count bits loaded with RISING edge when SOF_TOKEN '1'. extended Frame count must also enabled (EN_EXTFRAME SIE_CONFIG). Frame Number from each packet loaded with RISING edge when SOF_TOKEN '1'.
[7:3]
[2:0]
FRAME[10:8]
Local Address Register Table Local Address Register SIE_ADDR (0x7F92 RESET=0x00) LOCAL ADDRESS REGISTER NAME DESCRIPTION RX_ALL Overrides token address decoding such that compare done. Token also ignored when RX_ALL=1. This forces packets transmitted wire received Packet Queue [6:0] ADDR[6:0] This register only written 8051. SIE's local address assigned during enumeration. Note: When RX_ALL enabled, software should enable endpoints they will respond Address with same endpoint possibly cause contention line. Software should also each endpoint RX_ISO prevent handshakes from being sent. Alternate Address Register Table Alternate Address Register ALT_ADDR (0x7F99 RESET=0x00) ALTERNATE ADDRESS NAME DESCRIPTION EN_ALTADDR Alternate address. Enabled, this allows Endpoints through available this address. Disabled, this register does affect EP_OK generation. ALT6 Alternate address ALT5 Alternate address ALT4 Alternate address ALT3 Alternate address ALT2 Alternate address ALT1 Alternate address ALT0 Alternate address
Status Register Table Status Register SIE_STAT (0x7F93 RESET=0xXX) NAME TIMEOUT STATUS REGISTER DESCRIPTION Indicates that error occurred during last transaction. Considered valid rising edge Indicate that last transaction ended because inter-packet time condition (i.e.:>16 times). Considered valid rising edge EOT. Indicates that token received SETUP token.
SETUP_TOKEN
SIE_STAT (0x7F93 RESET=0xXX) NAME SOF_TOKEN PRE_TOKEN
USB_RESET
STATUS REGISTER DESCRIPTION Indicates that been received. Considered valid when '0'. Indicates that detected (preamble) packet bus. signal asserted when seen valid SYNC followed valid PID. Indicates that last transaction completed without error time-out. Considered valid rising edge EOT. When active '1', indicates that line being reset. This signal asserted when detects string single ended long time. Transaction. transition '1', indicates transaction. transition indicates beginning transaction.
Note:
This read only register reflects status signals from state machine. This register polled test purposes, error handling routines recovery.
Control Register Table Control Register SIE_CTRL1 (0x7F94 RESET=0x00) CONTROL REGISTER NAME DESCRIPTION SIEDMA_DISABLE Normal operation. Inhibits SIEDMA operation facilitate override FORCE_RXOK Forces send Acknowledge during receive. Must normal operation. FORCE_TTAG Normal operation. Signals that next byte written TX_FIFO last payload byte. FORCE_RXOVFLO Normal operation. Forces generate RXOVFLO clear FIFO. FORCE_TXABORT Normal operation Forces bit-stuff error host FORCE_EOT Normal operation. Forces End-of-Transaction RTAG_IN Status RTAG signal from FIFO TXOK_IN Status TXOK from These bits must normal operation. Altering these bits will cause abnormal behavior.
Note:
Control Register Table Control Register SIE_CTRL (0x7FA9 RESET=0x00) CONTROL REGISTER NAME DESCRIPTION Reserved Reserved Reserved Reserved Reserved SET_BUSY_ON_SETU Reserved This should always cleared Reserved This should always cleared Reserved This should always cleared Reserved This should always cleared Reserved This should always cleared When (1), setup pckt rcvd control endpoint will that endpoint busy direction disabled. When clear (0), setup pckt will have effect endpoint's control condition. Reserved This should always cleared Reserved This should always cleared
Reserved Reserved
Configuration Register Table Configuration Register SIE_CONFIG (0x7F98 RESET=0x40) CONFIGURATION REGISTER NAME DESCRIPTION FSEN Controls select Transceiver Slew Rate. 1.5Mbps 12Mbps RST_SIE Resets RST_FRAME Clears FRAMEL through FRAMEH EN_EXTFRAME Extended Frame Count Enable. Expands Frame count from bits bits 8051 use. Bits FRAMEH driven Bits FRAMEH count transitions FRAMEH. SIE_SUSPEND Forces into Suspend Mode. must determine that Suspend must entered. SIE_RESUME Forces transmit Resume signaling line. USB_RESUME Indicates Resume signaling been detected line while Suspend State. This signal causes Resume Power Management interrupt). USB_RESET Indicates that line being reset. Asserted when present more 12Mbps times. This causes USB_RESET Power management interrupt.
BLOCK
registers shown below interface Internal 8051 with SMSC USB97C196 internal Block. MCU, subsequent reset initialization, must initialize register block first task. Initialization registers below, must accomplished within after de-assertion reset. must initialize registers before stream host controller relinquishes reset pulse internal block that Host Controller enumerate device. Below block diagram block. indicated diagram, block consists Repeater, Control Command sequencer.
Down Stream Ports Upstream Port
PORT0 PORT1 Internal PORT2 Walkup
Port Control
Port Control
Port Control
Repeater
Serial Interface Engine
Command Sequencer
Power Control
Mode From Control Reg.
Power Control
USB97C196 Compound Device Block
Power Status
System Interface Unit This module consists address decoding multiplex logic. address decoder logic used compare address received from host during SETUP, token transfer with address HUB. There address decodes, endpoint Remote Device Control endpoint which part Block. Interface Unit Interface Unit (HIU) provides controller function this compound device. controller provides functionality Host communication. specific control status commands defined device class specification permit host controller configure control monitor each down stream port. control block, most part, like full speed device hence consists function blocks needed implement device. Included functionality required endpoint control, enumeration, control packet decoding, status maintenance reporting. Additional functions that will performed block include: Provide descriptors defined Device Class Specification Configuration Port Status Interrupt endpoint status change reporting Port Power control Frame Timer logic Fault Recovery Selective Suspend Resume port port basis Selective Reset port port basis ability decode preamble allowing Speed port enabling. Note: Speed down stream port support requires external transceivers Reflecting Remote Resume Upstream enabled down stream ports
Block Register Summary Register definitions defined below defined Table and. These registers arememory mapped into 8051 memory space defined Table Data Memory (page Table Block Register Summary RESET NAME VALUE DESCRIPTION IdVendor-Low byte Vendor little endian format (Bit Byte LSB) IdVendor00 High byte Vendor little endian format (Bit High Byte LSB)
ADDRESS 7FA0 7FA1
ADDRESS 7FA2
NAME IdProductLow Byte
RESET VALUE
7FA3
IdProductHigh Byte
7FA4
BcdDevice Byte BcdDevice High Byte HubControl1 HubControl2
7FA5
7FA6 7FA7
DESCRIPTION byte Product value little endian format (Bit LSB). This value initialized firmware upon initialization/power This value must initialized prior device participating enumeration transactions. High byte Product value little endian format (Bit LSB). This value initialized firmware upon initialization/power This value must initialized prior device participating enumeration transactions. This 8-bit value defines device release number, which assigned system manufacture. This 8-bit value defines device release number, which assigned system manufacture. Control Register1 Control Register
Control Register Table Control Register HubControl (0x7FA6- RESET=0x00) NAME NhubReset CONTROL REGISTER DESCRIPTION NHubReset When this asserted (0), controller reset state. will respond enumeration device requests. When this de-asserted (1), controller ready receive packets from Root Host Controller. Each Port will then enabled control packet from Host Reserved This should always cleared Reserved This should always cleared Reserved This should always cleared Reserved This should always cleared When this set, Port longer connected hub. directly connected Port which becomes upstream port. Figure. Force Single Ended zero (SE0). This will force condition upstream port selected Hub_Bypass bit). responsibility 8051 make sure duty cycle assertion within specified range intended operation (EOP exactly speed periods; Disconnect 2.5us). Reserved This should always cleared
Reserved Reserved Reserved Reserved Hub_Bypass
ForceSE0
Reserved
PORT0
Upstream Port
SMSC USB97C196 Block
Hub_Bypass
Down Stream Ports
Port Internal Port
FIGURE USB97C196 BYPASS MODE
Control Register Table Control Register HubControl (0x7FA7- RESET=0x00) CONTROL REGISTER NAME DESCRIPTION Reserved Reserved This should always cleared Reserved Reserved This should always cleared Reserved Reserved This should always cleared Reserved Reserved This should always cleared Reserved Reserved This should always cleared EXTXCVR2 EXTXCVREN This bit, when will disable internal Dual Speed transceiver enable associated control lines port (internal transceiver bypass). When this clear (0), internal transceiver used. Reserved Reserved This should always cleared Reserved Reserved This should always cleared
PARAMETERS
MAXIMUM GUARANTEED RATINGS Operating Temperature Range Storage Temperature Range .-55 +150 Lead Temperature Range (soldering, seconds). +325 Positive Voltage pin, with respect Ground Vcc+0.3V Negative Voltage pin, with respect Ground .-0.3V Maximum .+3.6V *Stresses above specified parameters
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