The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

Template Matcher L64230 Template Matcher DESCRIPTION


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



L64230
Template Matcher
L64230
Template Matcher
DESCRIPTION
Each filter performs basic XNOR logic operations. stored double buffered registers. controls XNOR gate while controls gate. XNOR gate performs inversion (erosion) magnitude differencing (template matching). gate performs masking (template matching) 1-bit multiplication (FIR filtering, dilation erosion). outputs taps summed produce final result. should noted that sigThe L64230 arranged (total) nificant bits signal lost. 32-tap filters with outputs each filters being summed then L64230 single-bit inputs layed variable-length shift regis- (DI31-0). filtering, only acters. multiprocessor system, this tive input DI0. However, when delayed output then summed with performing operations over winincoming partial result form com- size inputs plete output. addition carrying active. video shift register, with partial result into L64230, raster scanned signal input would input used vary threshold provide active data inputs. when clipping output single bit. L64230 high-speed, 1024-tap Digital Filter Template Matcher. device configured (one-dimensional) filter used such applications radar, sonar, other forms signal processing. L64230 also implemented (two-dimensional) applications, such real-time image processing such pattern matching, correlation, convolution, noise elimination morphological operations, dilation erosion.
FEATURES
40MHz Data Computation Rate 1024-tap High-Speed Digital Transversal Filter Template Matcher Variable Window Sizes: 1024, 512, 256, 128, Processor Cascadability Implemented Extended Data/ Coefficient Precision, Increased Filter-Tap Power, Increased Window Sizes DECC 5962-90504 Package Styles Available: 144-pin Plastic Quad Flatpack
L64230 BLOCK DIAGRAM
31-0 15-0 REGADR COEFF SELALL
15-0
32-TAP FILTERS COEFFICIENT CONTROL LOGIC
BNKLDO
BNKLDI
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
FIGURE
L64230 INTERNAL BLOCK DIAGRAM
REGADR7-0 COEFF SELALL BNKLDI PR15-0
CI7-0
Coefficient Control Register
BNKLDO
32-Tap Binary
32-Tap Binary 32-Tap Binary
32-Tap Binary DOUT15-0
DI27
32-Tap Binary
DI28
32-Tap Binary 32-Tap Binary
DI29
DI31
32-Tap Binary
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
BNKLDI Bank Load Input order bank load coefficients/ control inputs from master slave registers, BNKLDI HIGH. When asynchronously loading coefficients/control inputs BNKLDI held until bank loading occurs. When coefficient/control input loading performed synchronously, BNKLDI always held HIGH. REGADR7-0 Coefficient/Control Register Address Inputs Controls master register location that will loaded with coefficient/control inputs. Loading occurs only when LOW. REGADR7 MSB.
SIGNAL DEFINITIONS Power
power supply. pins must connected.
Controls
SELALL Coefficient Register Select-All When LOW, SELALL enables loading values CI7-0 into master latches 256, 4-tap groups processor simultaneously. This quickly initializes L64230. When HIGH, SELALL enables loading values into master latches found locations determined COEFF REGADR7-0. Write Enable When held LOW, coefficient/control signals loaded into register location indicated COEFF REGADR7-0. COEFF Coefficient Input Indicator data interpreted coefficient data when COEFF held HIGH. When COEFF held LOW, data interpreted control inputs. (See Table Processor Control/Coefficient Memory Map, more detail.)
Clock
Master Clock rising edge strobes registers. timing specifications referenced rising edge CLK.
Inputs
DI31-0 Data Input When L64230 implemented filtering application, only used. Pins, DI31-1 left disconnected. However, filtering application with window size L64230 operates with data inputs active. CI7-0 Coefficient/Control Input Eight control bits four sets coefficients (both loaded into master section coefficient/control registers. MSB. PR15-0 Partial Result Input partial result summed with processor results provide final data output. multiprocessor system, DO31-0 outputs preceding L64230 connected corresponding partial result input. partial results used varying threshold output, like clipping output single bit. Disconnected pins automatically assigned value. PR15 MSB.
Outputs
DO15-0 Data Output value output delayed output 1024 taps partial result (PR15-0). DO15 MSB. Shift Register Output filter application, input delayed 1025 cycles inverted. This signal usually connected next L64230 1-D, multiprocessor system. used processing. BNKLDO Bank Load Output BNKLDO BNKLDI signal delayed cycle. BNKLDO designed used multiprocessor system input BNKLDI next L64230.
OPERATION
L64230 operation fairly straightforward. After internal master registers have been loaded with data indicating operating mode, user need only supply system/ data clock input data. Once L64230 setup running, some coefficients (the changed while processor operating.
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
OUTDEL4-0 variable number delays performed variable delay element. Window ConfiguIf SELALL HIGH, 8-bit rations (Table displays various Control/Coefficient words individuwindow shapes corresponding acally loaded each time goes tive data inputs most common based state REGADR window configurations. Other conCOEFF. When SELALL pulsed LOW, figurations obtained. 1024 coefficients will loaded shown HIGH LOW). However, MUXCON OUTDEL values will change only when LOW. (Table gives more detail memory L64230.
CONTROL SIGNALS
mentioned previous paragraph, operation L64230 simple. However, both initialization processor loading Control/Coefficient Data will prove more interesting. initialize processor coefficients, delay value variable delay element configuration must specified. Processor Control/Coefficient Memory
Table
Coeff
Processor Control/Coefficient Memory
REGADR7-0 B30, B31, B31, A30, A31, A31, B30, B31, B31, MUXCON4 A30, A31, A31, MUXCON3 OUTDEL3 B30, B31, B31, MUXCON2 OUTDEL2 A30, A31, A31, MUXCON1 OUTDEL1 B30, B31, B31, MUXCON0 OUTDEL0 A30, A31, A31,
Table
11111 11110 11100 11000 10000 00000
Window Configurations
Configuration 1024 DI0, DI16 DI0, DI8, DI16, DI24 DI0, DI4, DI8, DI12, DI16, DI20, DI24, DI28 DI0, DI2, DI4, DI6, DI8, DI10, DI12, DI14, DI16, DI18, DI20, DI22, DI24, DI26, DI28,DI30 Active Inputs
MUXCON4-0
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
Figure
1D:y(n) PR(n
FUNCTIONAL OVERVIEW
L64230 designed perform Filtering, Template Matching Morphological Operations over variety window sizes. Figure shows basic functions performed L64230. these equations, DIi, wide. Depending upon application L64230 being used control variables: appropriately implement four previously mentioned functions. Filtering, inverted impulse response. application Template Matching, template "don't care" mask. Erosion implemented setting inverted structuring element. Dilation setup much same Filtering, with exception being that multi-bit output clipped single bit. addition, functions possible reduce effective window size masking some elements within window setting (refer Table value variable length output delay, controlled OUTDEL4-0. preceding functions outlined Table
1023
[(Bi XNOR DI0(n [(Bi, XNOR DIi(n
2D:y(n) PR(n
taneously loading coefficient registers with data loaded bus. that master registers loaded, user given three different choices transfer data from master latches into slave active latches.
latch, thus becoming active coefficient control signal. this way, coefficient replace current within clock cycle. This done only with slower clock speed, with cycle time 80ns (COM) more.
METHOD METHOD
first method load coefficient control signal master latch asynchronously reference CLK), then transfer data slave latch synchronously. Once master latches have been loaded (implementing either methods mentioned above paragraph), coefficients made active simultaneously enabling slave latches, when both BNKLDI HIGH. This method extends user, ability update coefficient sets into processor without modifying active coefficients. third method asynchronously load transfer over several cycles coefficients convenient supply BNKLDI signals synchronous CLK, this technique used. BNKLDI tied HIGH operated asynchronously. this case every time coefficient loaded, processor output could invalid cycles after rising edge processor could invalid 1050 cycles after rising edge control signals (COEFF loaded.
COEFFICIENT/CONTROL SIGNAL LOADING METHODS
Coefficients control signals double-buffered master slave registers. load coefficient control signal, data must first placed bus. data then latched into master register designated REGADR7-0 COEFF, when LOW. alternative method loading master registers with coefficient data individually, hold SELALL LOW. This makes possible quickly initialize processor simul-
METHOD
second method involves both loading transferring coefficients synchronously. This done simply tying BNKLDI HIGH. then pulsed when LOW. During this time, coefficient loaded into master latch, again determined REGADR7-0 COEFF. next rising edge CLK, coefficient transferred slave
Table
Filter
Functional Summary
Inverted Impulse Response "Don't Care" Mask Inverted Structuring Element Inverted Structuring Element Template Output Filter Output Represents Correlation Template D015 Output D015 Inverted Output
Functions
Template Matching Erosion Dilation
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
MAXIMUM RATINGS Above which useful life impaired (Notes
Storage temperature -65°C +150°C Operating ambient temperature -55°C +125°C supply voltage with respect ground -0.5 +7.0 Input signal with respect ground -0.5 Signal applied high impedance output -0.5 Output current into outputs Latchup current
OPERATING CONDITIONS meet specified electrical switching characteristics
Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) +70°C -55°C +125°C Supply Voltage 4.75 5.25 4.50 5.50
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note
Symbol ICC1 ICC2 COUT Parameter Output High Voltage Output Voltage Input High Voltage Input Voltage Input Current Current, Dynamic Current, Quiescent Input Capacitance Output Capacitance
(Note
Test Condition Min., -3.2 Min.,
Unit
2.25 ±200
Ground (Note
(Notes (Note
25°C, 25°C,
Logic Products
07/29/1999-LDS.64230-D
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321 098765432109876543210987654321 1098765432109876543210987654321 1098765432109876543210987654321
tPWH+20
COMMERCIAL OPERATING RANGE (0°C +70°C) Notes (ns)
SWITCHING CHARACTERISTICS
tPRH
tPRS
tWCL
tCLW
tHSB
tSSB
tCHS
tCSS
tOUT
tDIH
tDIS
tPWL
tPWH
tCYC
Parameter
Input Partial Result Hold Time
Input Partial Result Setup Time
HIGH after HIGH
before
SELALL BNKLDI Hold Time
SELALL BNKLDI HIGH Setup Time
BNKLDI Hold Time
BNKLDI HIGH Setup Time
BNKLDI Hold Time
BNKLDI Setup Time
SELALL Cycle Time
SELALL Pulse Width
SELALL HIGH Hold Time
SELALL Setup Time
Cycle Time
Pulse Width
HIGH Hold Time
Setup Time
REGADR HIGH Hold Time
REGADR Setup Time
Output Delay BNKLDO
Output Delay
Input Data Hold Time
Input Data Setup Time
Clock Pulse Width
Clock Pulse Width HIGH
Cycle Time
tPWH+15
LF64230
Template Matcher
Logic Products
tPWH+10
07/29/1999-LDS.64230-D
L64230
432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321
*DISCONTINUED SPEED GRADE
Symbol
tPWH+25
MILITARY OPERATING RANGE (-55°C +125°C) Notes (ns)
SWITCHING CHARACTERISTICS
tPRH
tPRS
tWCL
tCLW
tHSB
tSSB
tCHS
tCSS
tOUT
tDIH
tDIS
tPWL
tPWH
tCYC
Parameter
Input Partial Result Hold Time
Input Partial Result Setup Time
HIGH after HIGH
before
SELALL BNKLDI Hold Time
SELALL BNKLDI HIGH Setup Time
BNKLDI Hold Time
BNKLDI HIGH Setup Time
BNKLDI Hold Time
BNKLDI Setup Time
SELALL Cycle Time
SELALL Pulse Width
SELALL HIGH Hold Time
SELALL Setup Time
Cycle Time
Pulse Width
HIGH Hold Time
Setup Time
REGADR HIGH Hold Time
REGADR Setup Time
Output Delay BNKLDO
Output Delay
Input Data Hold Time
Input Data Setup Time
Clock Pulse Width
Clock Pulse Width HIGH
Cycle Time
tPWH+20
LF64230
Template Matcher
Logic Products
tPWH+20
07/29/1999-LDS.64230-D
L64230
L64230
Template Matcher
SWITCHING WAVEFORMS: NORMAL FILTER OPERATION
tCYC tPWH
tPWL
tDIS
tDIH
tOUT
BNKLDO
SWITCHING WAVEFORMS: LOADING CONTROLS INTO MASTER REGISTERS USING (SELALL HIGH)
REGADR COEFF
SWITCHING WAVEFORMS: LOADING CONTROLS INTO MASTER REGISTERS USING SELALL HIGH)
SELALL
tCSS
tCHS
SWITCHING WAVEFORMS: COEFFICIENT/CONTROL SIGNAL LOADING (METHOD
BNKLDI
tSSB
SELALL
tHSB
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
SWITCHING WAVEFORMS: COEFFICIENT/CONTROL SIGNAL LOADING (METHOD
tCLW
tWCL
SWITCHING WAVEFORMS: COEFFICIENT/CONTROL SIGNAL LOADING (METHOD III)
CYCLES Cycles Coefficients 1050 Cycles Controls
SELALL
SWITCHING WAVEFORMS: PARTIAL RESULT INPUT TIMING
tPRS
tPRH
Logic Products
07/29/1999-LDS.64230-D
L64230
Template Matcher
NOTES
specifications tested with input transition times less than output reference levels (except tDIS test), input levels nominally Output loading resistive divider which provides specified output voltage products described this spec- respectively. Alternatively, diode ification include internal circuitry bridge with upper lower current signed protect chip from damagsources respectively, substrate injection currents balancing voltage cumulations static charge. Neverthe- used. Parasitic capacitance less, conventional precautions should minimum, distributed. observed during storage, handling, these circuits order This device high-speed outputs caavoid exposure excessive electrical pable large instantaneous current stress values. pulses fast turn-on/turn-off times. result, care must exercised This device provides hard clamping testing this device. following transient undershoot overshoot. measures recommended: levels below ground above will clamped beginning -0.6 ceramic capacitor should device withstand installed between Ground indefinite operation with inputs leads close Device Under Test range -0.5 +7.0 Device opera- (DUT) possible. Similar capacitors tion will adversely affected, how- should installed between device ever, input current levels will well tester common, device ground tester common. excess Maximum Ratings indicate stress specifications only. Functional operation these products values beyond those indicated Operating Conditions table implied. Exposure maximum rating conditions extended periods affect reliability. Actual test conditions vary from Ground supply planes those designated operation guar- must brought directly anteed specified. socket contactor fingers. Supply current given applica- Input voltages should adjusted tion accurately approximated compensate inductive ground noise maintain required input NCV2 levels relative ground pin. where Each parameter shown minimum maximum value. Input requirements specified from point view external system driving chip. Setup time, example, specified minimum since exter6. Tested with outputs changing system must supply least that cycle load, clock much time meet worst-case requirements parts. Responses from rate. internal circuitry specified from Tested with inputs within point view device. Output Ground, load. delay, example, specified These parameters guaranteed maximum since worst-case operation device always provides data within 100% tested. that time. total number device outputs capacitive load output supply voltage clock frequency tENA test, transition measured crossing point with datasheet loads. tDIS test, transition measured ±200mV level from measured steady-state output voltage with ±10mA loads. balancing voltage, Z-to-0 0-to-Z tests, Zto-1 1-to-Z tests. These parameters only tested high temperature extreme, which worst case leakage current.
FIGURE OUTPUT LOADING CIRCUIT
FIGURE THRESHOLD LEVELS
tENA
tDIS
3.5V VOL*
VOH*
VOL* Measured with -10mA 10mA VOH* Measured with -10mA 10mA
Logic Products
07/29/1999-LDS.64230-D
Speed
-55°C +125°C MIL-STD-883 COMPLIANT
-55°C +125°C COMMERCIAL SCREENING
+70°C COMMERCIAL SCREENING
ORDERING INFORMATION
132-pin
BNKLDI BNKLDO
Discontinued Package
Ceramic Flatpack (F5)
DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 DI24 DI25 DI26 DI27 DI28 DI29 DI30 DI31
View
Template Matcher
REGADR2 REGADR1 REGADR0 COEFF SELALL REGADR3 REGADR4 REGADR5 REGADR6 REGADR7
Logic Products
PR10 PR11 PR12 PR13 PR14 PR15 DO15 DO14 DO13 DO12 DO11 DO10
07/29/1999-LDS.64230-D
L64230
L64230
Template Matcher
ORDERING INFORMATION
144-pin
PR10 PR11 PR12 PR13 PR14 PR15 DO15 DO14 DO13 DO12 DO11 DO10
BNKLDI BNKLDO
View
REGADR2 REGADR1 REGADR0 COEFF SELALL REGADR3 REGADR4 REGADR5 REGADR6 REGADR7
Speed
+70°C COMMERCIAL SCREENING
L64230QC25
DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23 DI24 DI25 DI26 DI27 DI28 DI29 DI30 DI31
Plastic Quad Flatpack (Q5)
Logic Products
07/29/1999-LDS.64230-D

Other recent searches


SUM85N03-08P - SUM85N03-08P   SUM85N03-08P Datasheet
SLIS031 - SLIS031   SLIS031 Datasheet
PE3501 - PE3501   PE3501 Datasheet
MC68HC05P9A - MC68HC05P9A   MC68HC05P9A Datasheet
HV583 - HV583   HV583 Datasheet
FR301 - FR301   FR301 Datasheet
FR307 - FR307   FR307 Datasheet
FIN1028 - FIN1028   FIN1028 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive