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VT82C596B
REVISION HISTORY
Document Release Revision Date 2/23/99 Revision Initial release based 82C596A Data Sheet revision Added UltraDMA-66 feature bullets overview Added integrated APIC (changed H18, K18, descriptions) Added note CMOS Register Summary Added changed function Rx42[6], Rx48[7-4], Rx5B[3], Rx5C[7-4, Rx74[29-24, Rx87-89 Added changed function Rx8, Rx4D[2-0], Rx54-55, Rx58-5B, Rx90-91, RxD2-D6 (80-88 renumbered), Offset 0[11], 20[14, 7-1], 22[14, 7-1], 24[14, 7-1], 28[15-11], 2A[15-11], 2C[11-10], 38[2-1], 44[10-1], 4C[30-0] Updated feature bullets, overview, descriptions Replaced function with registers from 686B reflect UltraDMA-66 Added changed function registers Rx42[7-6, Rx58-5B, Offset 0[8], 2C[2], 30[10-0], 34[10-0], 38[6, 4-3], (removed) Changed Function Rx42[2-0], 43[5-4], default, 55[3-0], 57[3-0], 58[3-0], 88[5], Function RxD, 42-43, 45[3-2], 54[4-3], 74-75, 7C-7D, Function Rx41[7-3], Function Rx4C-4F default value Initials
Revision
3/9/99
Revision
6/17/99
Revision June 1999
Revision History
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VT82C596B
TABLE CONTENTS
REVISION HISTORY.I TABLE CONTENTS. LIST FIGURES.IV LIST TABLES OVERVIEW PINOUTS REGISTERS REGISTER OVERVIEW CONFIGURATION SPACE REGISTER DESCRIPTIONS. Legacy Ports
Keyboard Controller Registers. Controller Registers Interrupt Controller Registers Timer Counter Registers CMOS Registers.
Function Registers Bridge.
Configuration Space Header Control. Plug Play Control Distributed Serial Control Miscellaneous General Purpose I/O.
Function Registers Enhanced Controller
Configuration Space Header IDE-Controller-Specific Confiiguration Registers Registers.
Function Registers Universal Serial Controller.
Configuration Space Header USB-Specific Configuration Registers. Registers.
Function Registers Power Management SMBus
Configuration Space Header Power Management-Specific Configuration Registers System Management Bus-Specific Configuration Registers System Management I/O-Space Registers. Power Management I/O-Space Registers
FUNCTIONAL DESCRIPTIONS POWER MANAGEMENT
Power Management Subsystem Overview Processor States System Suspend States Power Plane Control General Purpose Ports. Power Management Events System Processor Resume Events Legacy Power Management Timers System Primary Secondary Events Peripheral Events
ELECTRICAL SPECIFICATIONS.
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Table Contents
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VT82C596B
ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS. TIMING SPECIFICATIONS PACKAGE MECHANICAL SPECIFICATIONS
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Table Contents
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VT82C596B
LIST FIGURES
FIGURE SYSTEM CONFIGURATION USING VT82C596B FIGURE VT82C596B BALL DIAGRAM (TOP VIEW). FIGURE VT82C596B LIST (NUMERICAL ORDER). FIGURE VT82C596B LIST (ALPHABETICAL ORDER). FIGURE STRAP OPTION CIRCUIT. FIGURE POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM FIGURE ULTRADMA-33 TIMING DRIVE INITIATING BURST READ COMMAND. FIGURE ULTRADMA-33 TIMING DRIVE INITIATING BURST WRITE COMMAND. FIGURE ULTRADMA-33 TIMING PAUSING BURST FIGURE ULTRADMA-33 TIMING DRIVE TERMINATING BURST DURING READ COMMAND. FIGURE ULTRADMA-33 TIMING DRIVE TERMINATING BURST DURING WRITE COMMAND FIGURE ULTRADMA-33 TIMING HOST TERMINATING BURST DURING READ COMMAND. FIGURE ULTRADMA-33 TIMING HOST TERMINATING BURST DURING WRITE COMMAND FIGURE ULTRADMA-33 TIMING CYCLE FIGURE MECHANICAL SPECIFICATIONS 324-PIN BALL GRID ARRAY PACKAGE
LIST TABLES
TABLE TABLE TABLE TABLE TABLE TABLE TABLE DESCRIPTIONS. SYSTEM REGISTERS. KEYBOARD CONTROLLER COMMAND CODES CMOS REGISTER SUMMARY. CHARACTERISTICS CYCLE TIMING. CHARACTERISTICS ULTRADMA-33 INTERFACE TIMING.
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Table Contents
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VT82C596B
VT82C596B PIPC
INTEGRATED PERIPHERAL CONTROLLER PC98 COMPLIANT PCI-TO-ISA BRIDGE WITH ACPI, ENHANCED POWER MANAGEMENT, SMBUS, APIC, DISTRIBUTED DMA, SERIAL IRQ, PLUG PLAY, ULTRADMA-33/66 MASTER MODE PCI-EIDE CONTROLLER, CONTROLLER, KEYBOARD CONTROLLER,
Inter-operable with other Host-to-PCI Bridges Combine with VT82C598 (Apollo MVP3) complete 100MHz Socket-7 system Combine with VT82C693 (Apollo ProPlus) complete Socket-370 Slot-1 system Combine with VT82C693A (Apollo Pro133) complete Skt-370 Slot-1 system PC98 Compliant Bridge
Integrated Controller with integrated DMA, timer, interrupt controller Integrated Keyboard Controller with mouse support Integrated DS12885-style Real Time Clock with extended byte CMOS Day/Month Alarm ACPI Integrated Controller with root function ports Integrated UltraDMA-33/66 master mode EIDE controller with enhanced commands PCI-2.1 compliant with delay transaction Eight double-word line buffer between One-level post-write buffer Supports type transfers Distributed support legacy across Sideband signal support PC/PCI serial interrupt docking non-docking applications Serial Interrupt input Fast reset Gate operation Edge trigger level-sensitive interrupts Flash EPROM, EPROM combined BIOS support Supports positive subtractive decoding
Universal Serial Controller
v.1.1 Intel Universal v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter gather capabilities Root function ports Integrated physical layer transceivers with over-current detection status inputs Legacy keyboard PS/2 mouse support
Advanced Programmable Interrupt Controller (APIC)
Integrated on-chip Control pins provided support optional external APIC Used extend system interrupt capability PC98 compliant
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Features
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VT82C596B
UltraDMA-33/66 Master Mode EIDE Controller
Dual channel master mode supporting four Enhanced devices Transfer rate 22MB/sec cover mode multi-word mode drives, beyond Extension UltraDMA-33 interface transfer rates 33MB/sec Extension UltraDMA-66 interface transfer rates 66MB/sec Thirty-two levels (doublewords) prefetch write buffers Dual engine concurrent dual channel operation master programming interface SFF-8038i rev.1.0 Windows-95 compliant Full scatter gather capability Support ATAPI compliant devices including devices Support native compatibility modes Complete software driver support Supports glue-less "Swap-Bay" option with full electrical isolation
System Management Interface Host interface processor communications Slave interface external SMBus masters
Sophisticated PC98-Compatible Mobile Power Management
Supports both ACPI (Advanced Configuration Power Interface) legacy (APM) power management ACPI v1.0 Compliant v1.2 Compliant clock throttling clock stop control complete ACPI state support clock PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends with flexible CPU/PCI reset options, suspend DRAM, suspend disk (soft-off), with hardware automatic wake-up Multiple suspend power plane controls suspend status indicators idle timer, peripheral timer general purpose timer, plus 24/32-bit ACPI compliant timer Normal, doze, sleep, suspend conserve modes Global local device power control System event monitoring with event classes Primary secondary interrupt differentiation individual channels Dedicated input pins power sleep buttons, external modem ring indicator, notebook open/close system wake-up general purpose input ports output ports Multiple internal external sources flexible power management models programmable chip selects microcontroller chip select Enhanced integrated real time clock (RTC) with date alarm, month alarm, century field Thermal alarm support Cache SRAM power-down control docking support leakage control
Plug Play Controller interrupts steerable interrupt channel Dual interrupt signal steering on-board plug play devices Microsoft Windows 95and plug play BIOS compliant
Built-in NAND-tree scan test capability 0.5u, 3.3V, power CMOS process Single chip
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Features
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VT82C596B
OVERVIEW
VT82C596B south bridge high integration, high performance, power-efficient, high compatibility device that supports bridge functionality make complete Microsoft PC98-compliant system. addition complete extension functionality, VT82C596B includes standard intelligent peripheral controllers: Master mode enhanced controller with dual channel engine interlaced dual channel commands. Dedicated FIFO coupled with scatter gather master mode operation allows high performance transfers between devices. addition standard mode operation, VT82C596B also supports UltraDMA-33 standard allow reliable data transfer rates 33MB/sec throughput UltraDMA-66 standard 66MB/sec data transfer. controller SFF-8038i v1.0 Microsoft Windows-95 compliant. Universal Serial controller that v1.1 Universal v1.1 compliant. VT82C596B includes root with function ports with integrated physical layer transceivers. controller allows plug play isochronous peripherals inserted into system with universal driver support. controller also implements legacy keyboard mouse support that legacy software transparently non-USB-aware operating system environment. Keyboard controller with mouse support. Real Time Clock with byte extended CMOS. addition standard functionality, integrated also includes date alarm, century field, other enhancements compatibility with ACPI standard. Notebook-class power management functionality compliant with ACPI legacy requirements. Multiple sleep states (power-on suspend, suspend-to-DRAM, suspend-to-Disk) supported with hardware automatic wake-up. Additional functionality includes event monitoring, clock throttling stop (Intel processor protocol), clock stop control, modular power, clock leakage control, hardware-based software-based event handling, general purpose I/O, chip select external SMI. Full System Management (SMBus) interface. Distributed capability support legacy over bus. PC/PCI Serial mechanisms also supported docking non-docking applications. Plug Play controller that allows complete steerability interrupts interrupt channel. Three additional steerable interrupt channels provided allow plug play reconfigurability on-board peripherals Windows compliance. Integrated APIC (see Win98 Hardware Design Guide) VT82C596B also enhances functionality standard peripherals. integrated interrupt controller supports both edge level triggered interrupts channel channel. integrated controller supports type addition standard modes. Compliant with PCI-2.1 specification, VT82C596B supports delayed transactions that slower peripherals block traffic bus. Special circuitry built allow concurrent operation without causing dead lock even PCI-to-PCI bridge environment. chip also includes eight levels (doublewords) line buffers from further enhance overall system performance.
Cache Sideband Signals: Init CPUreset StopClk FERR IGNNE Boot North Bridge MA/Command (Module VT82C596B Crystal Expansion Cards GPIO, Power Control, Reset System Memory
Figure System Configuration Using VT82C596B
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Overview
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VT82C596B
PINOUTS
Figure VT82C596B Ball Diagram (Top View)
RST# USBP1+ SERR# RDY# RDY# RQB# GNT# RQC# REQ# DACK# IOW# IOR# CS1# CS3# IRQ0
RUN# RQD#
STOP# SEL#
RQA#
GPO29 SCI# P0GPI DIR#
IOW# IOR#
PIRQ USBD#
DACK#
ACS#/ CS3# CS1# APD0 AAK#/ VREF APD1 CLK#
OC0# OC1#
KEYL
KBCS# /MSDT
ARQ#/ SPKR WSC# FERR# SLP# INIT INTR SMI#
RTCALE
KBDT PIRQ DACK IOR#
RST# ST2#
KBCK
ALRT# BALE DACK IOCS BHE# ST1# DACK
A20G/ MSCK STP# STP#
PIRQ PIRQ IOCH IOW# SMEM SMEM
DACK
DATA
DACK DACK
LOW# BTN# TEST# SMI#
DACK RFSH#
CHK#
ZWS#
Note: Some pins above have alternate functions alternate names. table above contains only name, lists descriptions contain names.
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Pinouts
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VT82C596B
Figure VT82C596B List (Numerical Order)
Name PCIRST# AD27 IDSEL AD19 FRAME# SERR# AD13 PCIREQB# PGNT# SDD6 SDD4 SDD13 SDDRQ SDDACK# SDA2 PDD8 PDD7 AD31 AD26 AD23 AD18 IRDY# AD12 PCIREQC# PREQ# SDD9 SDD11 SDD1 SDIOW# SDA1 SDCS1# PDD9 PDD6 AD30 AD25 AD22 AD17 TRDY# CBE1# AD11 CBE0# PCKRUN# PCIREQD# SDD7 SDD5 SDD3 SDD14 SDIOR# SDA0 SDCS3# PDD10 PDD5 AD28 CBE3# AD20 CBE2# STOP#
Name AD14 AD10 PCLK SDD8 SDD10 SDD2 SDD15 SDRDY PDD12 PDD3 PDD11 PDD4 AD29 AD24 AD21 AD16 DEVSEL# AD15 PCIREQA# SDD12 SDD0 PDD14 PDD1 PDD13 PDD2 USBP1+ GPO28 GPO29/SCI# GPO30 PDIOW# PDIOR# PDDRQ PDD15 PDD0 PIRQD# USBP0+ GPI21 GPO0 GPO27 PDA0 PDA2 PDA1 PDDACK# PDRDY GPI18 USBP1H03 USBP0H04 GPI19 GPI20 PDCS3#
Name PDCS1# APICCS#/D0/GPO13 THRM# GPI8 IRQ0OUT GPO14 USBOC0# USBOC1# GPI14 KEYLOCK GNDUSB VREF APICACK#/D1/GPO12 STPCLK# SERIRQ GPI7 IRQ1 KBCS#/GPO26/MSDT ROMCS# GPI16 GPI17 VCCUSB GPO19 SPKR APICRQ#/WSC#/GPI5 FERR# SLP# RTCAS GPO25 GPI13 SLPBTN# USBCLK PCS0# GPI15 VBAT IGNNE# INIT INTR REQA# GPI2 RTCCS# GPO24 XDIR# GPO22 XOE# GPO23 KBDT RSMRST# PWRGD CPURST A20M# GNTA# GPO9 REQB# GPI3 KBCK MCCS# PCS1#
Name VCCSUS SMBALRT# GPI11 RTCX1 RCIN# A20GATE MSCK GNTB# GPO10 REQC# GPI4 GNTC# GPO11 PIRQC# GPI10 SUSCLK GPI12 GPI1 PME# SMI# CPUSTP# GPO17 PCISTP# GPO18 PIRQA# PIRQB# VCCSUS CFG1 CFG2 SMBCLK RTCX2 IOCHRDY IOW# SA16 BCLK IRQ3 LA23 GPO7 IRQ12 LA18 GPO2 DACK5# SUSST1# GPO20 SUSST2# GPO21 GPO8 SMBDATA IRQ9 SMEMW# SA18 DRQ3 DRQ1 SA11 IRQ5 BALE IRQ10 LA20 GPO4 DACK0# MEMW# DRQ6
Name DRQ7 SUSC# GPO16 BATLOW# GPI9 PWRBTN# DRQ2 SA19 DACK3# SA14 SA12 IRQ6 IOCS16# LA21 IRQ14 MEMR# DACK6# SD11 TEST# SUSB# GPO15 EXTSMI# RSTDRV SMEMR# SA17 DACK1# RFSH# SA10 IRQ4 SBHE# IRQ11 LA19 GPO3 DRQ0 DACK7# SD13 SD15 SUSA# IOCHCK# GPI0 ZWS# IOR# SA15 SA13 IRQ7 DACK2# MCS16# LA22 GPO6 IRQ15 LA17 GPO1 DRQ5 SD10 SD12 SD14 IRQ8# GPI6
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Pinouts
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VT82C596B
Figure VT82C596B List (Alphabetical Order)
Name Name Name Name Name A20GATE MSCK FERR# KBCS#/GPO26/MSDT PWRGD SDD09 A20M# FRAME# LA17 GPO1 RCIN# SDD10 AD00 LA18 GPO2 REQA# GPI2 SDD11 AD01 LA19 GPO3 REQB# GPI3 SDD12 AD02 LA20 GPO4 REQC# GPI4 SDD13 AD03 LA21 GPO5 RFSH# SDD14 AD04 LA22 GPO6 GPI12 SDD15 AD05 LA23 GPO7 ROMCS# SDDACK# AD06 GPI10 RSMRST# SDDRQ AD07 MCCS# RSTDRV SDIOR# AD08 MCS16# RTCAS/GPO25 SDIOW# AD09 MEMR# RTCCS#/GPO24 SERIRQ GPI7 AD10 MEMW# RTCX1 SERR# AD11 KEYLOCK RTCX2 SDRDY AD12 KBDT SA00 SLP# AD13 KBCK SA01 SMBALRT#/GPI11 AD14 SA02 SMBCLK AD15 SA03 SMBDATA AD16 SA04 SMEMR# AD17 SA05 SMEMW# AD18 SA06 SMI# AD19 SA07 SPKR GNDUSB AD20 GNTA# GPO9 PCKRUN# SA08 STOP# AD21 GNTB# GPO10 PCLK SA09 STPCLK# AD22 GNTC# GPO11 PCIREQA# SA10 SUSA# AD23 GPI1 PME# PCIREQB# SA11 SUSB# GPO15 AD24 GPI13 SLPBTN# PCIREQC# SA12 SUSC# GPO16 AD25 GPI14 PCIREQD# SA13 SUSCLK AD26 GPI15 PCIRST# SA14 SUSST1# GPO20 AD27 GPI16 PCISTP#/GPO18 SA15 SUSST2# GPO21 AD28 GPI17 PCS0# SA16 AD29 GPI18 PCS1# SA17 TEST# AD30 GPI19 PDA0 SA18 THRM# GPI8 AD31 GPI20 PDA1 SA19 TRDY# GPI21 PDA2 SBHE# USBCLK APICAK#//D1/O12 GPO00 PDCS1# SD00 USBOC0# APICCS#/D0/O13 GPO08 PDCS3# SD01 USBOC1# APICRQ#/WSC#/I5 GPO27 PDD00 SD02 USBP0U10 BALE GPO28 PDD01 SD03 USBP0+ BATLOW# GPI9 GPO29 SCIOUT# PDD02 SD04 USBP1T07 BCLK GPO30 PDD03 SD05 USBP1+ CBE0# IDSEL PDD04 SD06 VBAT CBE1# IGNNE# PDD05 SD07 CBE2# INIT PDD06 SD08 CBE3# INTR PDD07 SD09 CFG1 IOCHCK# GPI0 PDD08 SD10 CFG2 IOCHRDY PDD09 SD11 CPURST IOCS16# PDD10 SD12 CPUSTP# GPO17 IOR# PDD11 SD13 DACK0# IOW# PDD12 SD14 DACK1# IRDY# PDD13 SD15 DACK2# IRQ0OUT GPO14 PDD14 SDA0 DACK3# IRQ1 PDD15 SDA1 DACK5# IRQ3 PDDACK# SDA2 DACK6# IRQ4 PDDRQ SDCS1# DACK7# IRQ5 PDIOR# SDCS3# DEVSEL# IRQ6 PDIOW# SDD00 VCCSUS DRQ0 IRQ7 PGNT# SDD01 VCCSUS DRQ1 IRQ8# GPI6 PREQ# SDD02 VCCUSB DRQ2 IRQ9 PDRDY SDD03 VREF DRQ3 IRQ10 PIRQA# SDD04 XDIR# GPO22 DRQ5 IRQ11 PIRQB# SDD05 XOE# GPO23 DRQ6 IRQ12 PIRQC# SDD06 ZWS# DRQ7 IRQ14 PIRQD# SDD07 GPO19 EXTSMI# IRQ15 PWRBTN# SDD08 Referenced VCCSUS: BATLOW#, CFG1-2, EXTSMI#, GPI1, GPO8, IRQ8#, LID, PWRBTN#, PWRGD, RI#, RSMRST#, SUSA-C#, SUSST1-2#, TEST#
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Pinouts
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VT82C596B
Table Descriptions
Interface
Signal Name PCLK FRAME# AD[31:0] A10, Signal Description Clock. PCLK provides timing transactions Bus. Frame. Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. Address/Data Bus. standard address data lines. address driven with FRAME# assertion data driven received following cycles.
C/BE[3:0]# IRDY# TRDY# STOP# DEVSEL# SERR#
IDSEL PIRQA-D#
PREQ# PGNT# PCKRUN#
Command/Byte Enable. command driven with FRAME# assertion. Byte enables corresponding supplied requested data driven following clocks. Initiator Ready. Asserted when initiator ready data transfer. Target Ready. Asserted when target ready data transfer. Stop. Asserted target request master stop current transaction. Device Select. VT82C596B asserts this signal claim transactions through positive subtractive decoding. Parity. single parity provided over AD[31:0] C/BE[3:0]#. System Error. SERR# pulsed active device that detects system error condition. Upon sampling SERR# active, VT82C596B programmed generate CPU. Initialization Device Select. IDSEL used chip select during configuration read write cycles. Interrupt Request. These pins typically connected INTA#INTD# pins follows: PIRQC# PIRQD# PIRQA# PIRQB# Slot INTA# INTB# INTC# INTD# Slot INTB# INTC# INTD# INTA# Slot INTC# INTD# INTA# INTB# Slot INTD# INTA# INTB# INTC# Request. This signal goes North Bridge request bus. Grant. This signal driven North Bridge grant access VT82C596B. Clock Run. This signal indicates whether clock will stopped (high) running (low). VT82C596B drives this signal when clock running (default reset) releases when stops clock. External devices assert this signal request that clock restarted prevent from stopping. Refer Mobile Design Guide more details.
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Pinouts
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VT82C596B
Interface
Signal Name CPURST INTR
Signal Description Reset. VT82C596B asserts CPURST reset during power-up. Interrupt. INTR driven VT82C596B signal that interrupt request pending needs service. Non-Maskable Interrupt. used force non-maskable interrupt CPU. VT82C596B generates when either SERR# IOCHK# asserted. Initialization. VT82C596B asserts INIT detects shut-down special cycle soft reset initiated register Stop Clock. STPCLK# asserted VT82C596B response different Power-Management events. System Management Interrupt. SMI# asserted VT82C596B response different Power-Management events. Numerical Coprocessor Error. This signal tied coprocessor error signal CPU. Internally generates interrupt active. Ignore Numeric Error. This connected "ignore error" CPU. Sleep. Used sleep. Used with slot-1 CPUs only. currently used with socket-7 CPUs.
INIT STPCLK# SMI# FERR# IGNNE# SLP#
Universal Serial Interface
Signal Name USBP0+ USBP0USBOC0# USBP1+ USBP1USBOC1# USBCLK Signal Description Port Data Port Data Port Over Current Detect. Port disabled this input low. Port Data Port Data Port Over Current Detect. Port disabled this input low. Clock. 48MHz clock input Universal Serial interface
System Management (SMB) Interface (I2C Bus)
Signal Name SMBCLK SMBDATA SMBALRT# GPI11 Signal Description Clock. Data. MultiFunction Alert. (Rx74[5] When chip enabled allow assertion generates interrupt power management resume event. General Purpose Input (Rx74[5] General purpose input.
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Pinouts
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VT82C596B
UltraDMA-33 Enhanced Interface
Signal Name PDRDY PDDMARDY# PDSTROBE
Signal Description EIDE Mode: Primary Channel Ready. Device ready indicator UltraDMA Mode: Primary Device Ready. Output flow control. device assert PDDMARDY# pause output transfers Primary Device Strobe. Input data strobe (both edges). device stop PDSTROBE pause input data transfers EIDE Mode: Secondary Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device Ready. Output flow control. device assert SDDMARDY# pause output transfers Secondary Device Strobe. Input data strobe (both edges). device stop SDSTROBE pause input data transfers EIDE Mode: Primary Device Read. Device read strobe UltraDMA Mode: Primary Host Ready. Primary channel input flow control. host assert PHDMARDY# pause input transfers Primary Host Strobe. Output data strobe (both edges). host stop PHSTROBE pause output data transfers EIDE Mode: Secondary Device Read. Device read strobe UltraDMA Mode: Secondary Host Ready. Input flow control. host assert SHDMARDY# pause input transfers Host Strobe Output strobe (both edges). host stop SHSTROBE pause output data transfers EIDE Mode: Primary Device Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted host prior initiation UltraDMA burst; negated host before data transferred UltraDMA burst. Assertion STOP host during after data transfer UltraDMA mode signals termination burst. EIDE Mode: Secondary Device Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted host prior initiation UltraDMA burst; negated host before data transferred UltraDMA burst. Assertion STOP host during after data transfer UltraDMA mode signals termination burst. Primary Device Request. Primary channel request Secondary Device Request. Secondary channel request Primary Device Acknowledge. Primary channel acknowledge Secondary Device Acknowledge. Secondary channel acknowledge
SDRDY SDDMARDY# SDSTROBE
PDIOR# PHDMARDY# PHSTROBE
SDIOR# SHDMARDY# SHSTROBE
PDIOW# PSTOP
SDIOW# SSTOP
PDDRQ SDDRQ PDDACK# SDDACK#
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Pinouts
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VT82C596B
UltraDMA-33 Enhanced Interface (continued)
Signal Name PDCS1# PDCS3# SDCS1# SDCS3# PDA[2-0] SDA[2-0] PDD[15-0]
G17, G18, A18, B17, F19, E17, E19, D17, D19, C19, B19, A19, A20, B20, C20, D20, D18, E20, E18, D15, C15, A15, E14, B14, D13, B13, D12, C12, A13, C13, A14, C14, D14, B15,
Signal Description Primary Master Chip Select. This signal corresponds CS1FX# primary connector. Primary Slave Chip Select. This signal corresponds CS3FX# primary connector. Secondary Master Chip Select. This signal corresponds CS17X# secondary connector. Secondary Slave Chip Select. This signal corresponds CS37X# secondary connector. Primary Disk Address. PDA[2:0] used indicate which byte either command block control block being accessed. Secondary Disk Address. SDA[2:0] used indicate which byte either command block control block being accessed. Primary Disk Data
SDD[15-0]
Secondary Disk Data
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Pinouts
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VT82C596B
Interface
Signal Name SA[19:0]
W10, T10, Y11, W11, T11, T12, Y13, V13, U13, W14, T14, W19, Y19, W18, Y18, V17, Y17, T16, W16,
Signal Description Address
LA[23:17]
SD[15:0]
"Latched" Address Bus: LA[23:17] address lines bi-directional. These address lines allow accesses physical memory 16Mbytes. Data. SD[15:0] provide data path devices residing bus. SD7:4 strap options keyboard inputs (see Function Rx5A)
SBHE#
IOR# IOW# MEMR# MEMW# SMEMR# SMEMW# BALE
IOCS16# MCS16# IOCHCK# IOCHRDY
ZWS#
Byte High Enable. SBHE# indicates, when asserted, that byte being transferred upper byte (SD[15:8]) data bus. SBHE# negated during refresh cycles. Read. IOR# command slave device which indicates that slave drive data data bus. Write. IOW# command slave device which indicates that slave latch data from data bus. Memory Read. MEMR# command memory slave which indicates that drive data onto data bus. Memory Write. MEMW# command memory slave which indicates that latch data from data bus. Standard Memory Read. SMEMR# command memory slave, under 1MB, which indicates that drive data onto data Standard Memory Write. SMEMW# command memory slave, under 1MB, which indicates that latch data from data bus. Address Latch Enable. BALE active high signal asserted VT82C596B indicate that address (SA[19:0], LA[23:17] SBHE# signal) valid 16-Bit Chip Select. This signal driven devices indicate that they support 16-bit cycles. Memory Chip Select slaves that 16-bit memory devices drive this line indicate they support 16-bit memory cycles. Channel Check. When this signal asserted, indicates that parity uncorrectable error occurred device memory Bus. Channel Ready. This signal normally high. Devices assert IOCHRDY indicate that additional time (wait states) required complete cycle. Zero Wait State. Devices assert ZWS# indicate that wait states required.
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Interface (continued)
Signal Name RFSH# IRQ0OUT GPO14
Signal Description Refresh. output RFSH# indicates when refresh cycle progress. input RFSH# driven 16-bit masters indicate refresh cycle. Address Enable. asserted during cycles prevent slaves from misinterpreting cycles valid cycles. Multifunction Rx74[7] Interrupt Request Output. Reflects state internal system timer IRQ0 signal. Rx74[7] General Purpose Output Interrupt Request Interrupt Request Interrupt Request Interrupt Request Interrupt Request Interrupt Request Multifunction Rx5A[2] Internal disabled. Interrupt Request from external Rx5A[2] Internal enabled. General Purpose Input Interrupt Request Interrupt Request Interrupt Request Interrupt Request Interrupt Request Interrupt Request Request. Used request services from internal controller.
IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8# GPI6
IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DRQ7-5,
DACK7-5, 3-0#
SPKR
U17, U16, Y16, W17, V16, T15, Y10,
Acknowledge. Used internal controller indicate that request service been granted. Terminal Count. Asserted slaves terminal count indicator. Speaker Drive. output internal timer/counter
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Interface
Signal Name XDIR# GPO22
Signal Description MultiFunction X-Bus Data Direction. (Rx75[6]=0) Asserted read cycles memory read cycles programmed BIOS APIC address space. XDIR# tied directly direction control 74F245 transceiver that buffers X-Bus data ISA-Bus data. SD0-7 connect side transceiver XD0-7 connect side. XDIR# high indicates that SD0-7 drives XD0-7. General Purpose Output (Rx75[6]=1) General purpose output. MultiFunction X-Bus Output Enable. (Rx75[6]=0) Asserted decoded X-Bus cycles. XOE# tied directly output enable 74F245 transceiver that buffers X-Bus data ISA-Bus data (see XDIR# above). General Purpose Output (Rx75[6]=1) General purpose output. MultiFunction External Keyboard Controller Chip Select. (Rx76[2] Asserted during read write accesses ports 64h. General Purpose Output (Rx76[2]=1) General purpose output. Chip Select. Chip Select BIOS ROM. Microcontroller Chip Select. Asserted during read write accesses ports 66h. Programmable Chip Selects. Asserted during cycles programmable read write address ranges. Devices selected these pins assumed XBus (XDIR# XOE# enabled).
XOE# GPO23
KBCS# GPO26
ROMCS# MCCS# PCS[1-0]#
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Internal Real Time Clock
Signal Name RTCX1 RTCX2 RTCCS# GPO24
Signal Description Crystal Input: 32.768 crystal oscillator input. Crystal Output: 32.768 crystal output MultiFunction External Chip Select. (Rx76[0] Asserted read write accesses port 71h. Externally connected pair gates logically chip select with IOR# IOW#) generate active-low read write commands. General Purpose Output (Rx76[0] General purpose output. MultiFunction External Address Strobe. (Rx76[1] Asserted writes Port 70h. General Purpose Output (Rx76[1] General purpose output.
RTCAS GPO25
Internal Keyboard Controller
Signal Name KEYLOCK PIRQ1 Signal Description Extended Function (PIIX4 PIRQ1) Rx59[1]=1 Lock. Input internal keyboard controller Extended Function (PIIX4 Connect) Rx5A[0]=1 (Internal keyboard controller enabled -strapped from XD0) Keyboard Clock Extended Function (PIIX4 Connect) Rx5A[0]=1 (Internal keyboard controller enabled -strapped from XD0) Keyboard Data MultiFunction Rx5A[1]=0 (internal keyboard controller disabled strapped from XD1) Gate A20. From optional external keyboard controller Rx5A[1]=1 (internal keyboard controller enabled -strapped from XD1) Mouse Clock. Mouse clock (extended function available PIIX4) MultiFunction Rx5A[1]=0 (Internal keyboard controller disabled -strapped from XD1) Keyboard Controller Chip Select. (Rx76[2]=0 external keyboard controller enabled) Chip select external keyboard controller. General Purpose Output (Rx76[2]=1 external keyboard controller disabled) General purpose output Rx5A[1]=1 (Internal keyboard controller enabled -strapped from XD1) Mouse Data. Mouse data (extended function available PIIX4)
KBCK
KBDT
MSCK A20GATE
MSDT KBCS# GPO26
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PC/PCI Serial Control
Signal Name REQ[A-C]# GPI[2-4] GNT[A-C]# GPO[9-11] SERIRQ GPI7
Signal Description PC/PCI Requests. Used agent request services PC/PCI protocol. functions refer Rx7D[2-0]. PC/PCI Grants. Used acknowledge services PC/PCI protocol. functions refer Rx7D[2-0]. Serial Interrupt Request. Used with Distributed DMA. Rx68[3].
Control
Signal Name A20GATE MSCK Signal Description Gate A20: Gate output from optional external keyboard controller used. Logically combined with Port bit-1 (Fast_A20) output A20M# signal. internal keyboard mouse controller used, this becomes mouse clock input (the A20GATE signal comes directly from internal keyboard controller). Mask. Connect mask input CPU.
A20M#
APIC Interface
Signal Name APICREQ# WSC# GPI5 I/I/I Signal Description MultiFunction Internal APIC Write Snoop Complete. (Rx74[7]=1 Rx74[1]=1) Asserted north bridge indicate that snoop activity initiated last PCI-to-DRAM write complete that safe perform APIC interrupt. External APIC Request. (Rx74[7]=1 Rx74[1]=0) Asserted external APIC synchronous PCICLK prior sending interrupt over APIC serial bus. This signals VT82C596B flush internal buffers. General Purpose Input (Rx74[7] MultiFunction Internal APIC Data (Rx74[7]=1 Rx74[1]=1) External APIC Chip Select. (Rx74[7]=1 Rx74[1]=0) VT82C596B drives this signal active select external APIC used). This occurs external APIC enabled cycle detected within programmed APIC address range. General Purpose Output (Rx74[7] MultiFunction Internal APIC Data (Rx74[7]=1 Rx74[1]=1) External APIC Acknowledge. (Rx74[7]=1 Rx74[1]=0) Asserted VT82C596B indicate that internal buffers have been flushed response APICREQ#). This indicates external APIC that VT82C596B's internal buffers have been flushed that APIC send interrupt. General Purpose Output (Rx74[7]
APICCS# APICD0 GPO13
O/O/O
APICACK# APICD1 GPO12
O/O/O
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General Purpose Inputs
Signal Name GPI0 IOCHCK# GPI1 PME# GPI2 REQA# GPI3 REQB# GPI4 REQC# GPI5 APICREQ# GPI6 IRQ8# GPI7 SERIRQ GPI8 THRM# GPI9 BATLOW# GPI10 GPI11 SMBALRT# GPI12 GPI13 SLPBTN#
Signal Description
General Purpose Input (Rx74[0] General Purpose Input General Purpose Input (Rx7D[0] General Purpose Input (Rx7D[1] General Purpose Input (Rx7D[2] General Purpose Input (Rx74[7] General Purpose Input (Rx5A[2] General Purpose Input (Rx68[3] General Purpose Input (Rx74[2] General Purpose Input (Rx74[3] General Purpose Input (Rx74[4] General Purpose Input (Rx74[5] General Purpose Input (Rx74[6] General Purpose Input Also functions ACPI sleep button bit-9 register ACPI Space (Function enabled GPI14 General Purpose Input GPI15 General Purpose Input GPI16 General Purpose Input GPI17 General Purpose Input GPI18 General Purpose Input GPI19 General Purpose Input GPI20 PIRQ0 General Purpose Input (Rx59[0] also Rx55[3:0] GPI21 PIRQ2 General Purpose Input (Rx59[2] also Rx58[3:0] underlined name above indicates default function power
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General Purpose Outputs
Signal Name
Signal Description
GPO0 General Purpose Output GPO1 LA17 General Purpose Output Rx74[0] GPO2 LA18 General Purpose Output Rx74[0] GPO3 LA19 General Purpose Output Rx74[0] GPO4 LA20 General Purpose Output Rx74[0] GPO5 LA21 General Purpose Output Rx74[0] GPO6 LA22 General Purpose Output Rx74[0] GPO7 LA23 General Purpose Output Rx74[0] GPO8 General Purpose Output F3Rx54[1-0]. Optional clock output GPO9 GNTA# General Purpose Output Rx7D[0] GPO10 GNTB# General Purpose Output Rx7D[1] GPO11 GNTC# General Purpose Output Rx7D[2] GPO12 APICACK# General Purpose Output Rx74[7] GPO13 APICCS# General Purpose Output Rx74[7] GPO14 IRQ0OUT General Purpose Output Rx74[7] GPO15 SUSB# General Purpose Output Rx75[0] also F3Rx54[3]. GPO16 SUSC# General Purpose Output Rx75[0] also F3Rx54[2]. GPO17 CPUSTP# General Purpose Output Rx75[1] GPO18 PCISTP# General Purpose Output Rx75[2] GPO19 General Purpose Output Rx75[3] GPO20 SUSST1# General Purpose Output Rx75[4] also F3Rx54[4]. GPO21 SUSST2# General Purpose Output Rx75[5] also F3Rx54[7]. GPO22 XDIR# General Purpose Output Rx75[6] GPO23 XOE# General Purpose Output Rx75[6] GPO24 RTCCS# General Purpose Output Rx76[0] GPO25 RTCAS General Purpose Output Rx76[1] GPO26 KBCS# General Purpose Output Rx76[2] GPO27 General Purpose Output GPO28 General Purpose Output GPO29 SCIOUT# General Purpose Output Rx74[7] GPO30 General Purpose Output underlined name above indicates default function power
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Power Management
Signal Name PWRBTN#
Signal Description Power Button. Used Power Management subsystem monitor external system on/off button switch. VT82C596B performs 200us debounce this input Rx40[5] This input referenced VCCSUS. ACPI Sleep Button. General purpose input also functions ACPI sleep button bit-9 register ACPI Space (Function enabled. Reset CPU. This signal from optional external keyboard controller used) causes INIT signal generated CPU. Resume Reset. Resets internal logic connected VCCSUS power plane also resets portions internal logic. External System Management Interrupt. When enabled allow falling edge this input causes SMI# generated enter mode. Once asserted, this should held least four PCICLKs. VT82C596B also asserts EXTSMI# response SMI# being activated within Serial function. This should connected external pullup. Power Management Requests. Used internal power management monitor requests bus.
SLPBTN# GPI13 RCIN# RSMRST# EXTSMI#
PCIREQ[A-D]#
E10, A11, B11,
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Power Management (continued)
Signal Name GPI10
Signal Description Notebook Computer Display Open Closed Monitor. Used Power Management subsystem monitor opening closing display notebook computers. used detect either low-to-high and/or high-to-low transitions generate SMI#. VT82C596B performs usec debounce this input Rx40[5] optionally programmed general purpose input (Rx74[4]=1). Ring Indicator. connected external modem circuitry allow system re-activated received phone call. This input referenced VCCSUS. optionally programmed general purpose input (Rx74[6]=1). Thermal Detect. VT82C596B enabled allow asserting this signal initiates hardware Clock Throttling mode. This causes STPCLK# cycled preset programmable rate (see Function configuration space Rx4C). optionally programmed general purpose input (Rx74[2]=1). ACPI System Control Interrupt. Connected external APIC used. optionally programmed general purpose output (Rx74[7]=0). Clock Stop. Signals system clock generator disable clock outputs. optionally programmed general purpose output (Rx75[1]=1). Clock Stop. Signals system clock generator disable clock outputs. optionally programmed general purpose output (Rx75[2]=1). Cache SRAM Power Mode. Used power down Cache SRAMs during Stop Clock state. optionally programmed general purpose output (Rx75[3]=1). Suspend Plane Control. Asserted during power management POS, STR, suspend states. Used control primary power plane. Suspend Plane Control. Asserted during power management suspend states. Used control secondary power plane. optionally programmed general purpose output (Rx75[0]=1). Suspend Plane Control. Asserted during power management suspend state. Used control tertiary power plane. optionally programmed general purpose output (Rx75[0]=1). Suspend Status Typically connected North Bridge (e.g., VT82C598 Apollo MVP3) provide information host clock status. Asserted when system stop host clock, such Stop Clock during POS, STR, suspend states. optionally programmed general purpose output (Rx75[4]=1). Suspend Status Typically connected other system devices provide information system suspend state. Asserted during POS, STR, suspend states. optionally programmed general purpose output (Rx75[5]=1).
GPI12
THRM# GPI8
SCIOUT# GPO29 CPUSTP# GPO17
PCISTP# GPO18
GPO19
SUSA# SUSB# GPO15
SUSC# GPO16
SUSST1# GPO20
SUSST2# GPO21
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Resets Clocks
Signal Name PWRGD PCIRST# RSTDRV BCLK SUSCLK
Signal Description Power Good. Connected PWRGOOD signal Power Supply. Reset. Active reset signal bus. VT82C596B will assert this during power-up from control register. Reset Drive. Reset signal bus. Clock. clock. Oscillator. 14.31818 clock signal used internal Timer. Suspend Clock. 32.768 output clock North Bridge (e.g., VT82C598 Apollo MVP3) DRAM refresh purposes. Stopped during Suspend-toDisk Soft-Off modes.
Configuration Test
Signal Name CFG1 CFG2 TEST# Signal Description Configuration Used select type (0=Socket-7, 1=Slot-1). Determines polarity INIT CPURST signals. Configuration Used select type decoding Kbytes memory (FFFF0000h-FFFFFFFFh): Positive decode, Subtractive decode. Test. Used select chip test modes. Pulled externally VCCSUS normal operation.
Power Ground
Signal Name E11, E12, E16, F14, F15, P15, R15, Signal Description Core Power. 3.3V nominal (3.15V 3.45V). This supply turned only when mechanical switch power supply turned PWRON signal conditioned high. This should connected same voltage circuitry. Voltage Reference. nominal (4.75 5.25) provide input tolerance. This voltage should only when mechanical switch power supply turned PWRON signal conditioned high. Suspend Power. Always available unless mechanical switch power supply turned off. "soft-off" state implemented, then this connected VCC. Signals powered referenced this plane are: BATLOW#, CFG1-2, EXTSMI#, GPI1, GPO8, IRQ8#, LID, RI#, SMBALRT#, SMBCLK, SMBDATA, PWRBTN#, SUS[A-C]#, SUSCLK, SUSST[1-2]#, TEST#, PWROK, RSMRST#. Battery. Battery input internal (RTCX1, RTCX2) Differential Output Power Source (USBP0+, P0-, P1+, P1-) Differential Output Ground Ground
VREF
VCCSUS
N16,
VBAT VCCUSB GNDUSB
D10, E13, J9-12, K9-12, L9-12, M9-12 M16, N18,
Connect
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Table Registers
Legacy Registers
REGISTERS
Register Overview
following tables summarize configuration registers VT82C596B. These tables also document power-on default value ("Default") access type ("Acc") each register. Access type definitions used (Read/Write), (Read/Only), reserved used (essentially same RO), just (Read Write Clear individual bits). Registers indicated have some read/only bits that always read back fixed value (usually unused); registers designated have some read-only read write bits (see individual register descriptions details). Detailed register descriptions provided following section this document. offset default values shown hexadecimal unless otherwise indicated Port
Table System
Port 00-1F 20-3F 40-5F 60-6F (60h) (61h) (64h) 70-77 78-7F 81-8F 90-91 93-9F A0-BF C0-DF E0-FF 100-CF7 Function Master Controller Timer Counter Actual Port Decoding 0000 0000 000x nnnn 0000 0000 010x xxnn
Master Controller Registers Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read Write Mask
Default Default
Master Interrupt Controller 0000 0000 001x xxxn Keyboard Controller 0000 0000 0110 xnxn Data 0000 0000 0110 x0x0 Misc Functions Spkr Ctrl 0000 0000 0110 xxx1 Command Status 0000 0000 0110 x1x0 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn -available system use- 0000 0000 0111 1xxx -reserved- (debug port) Page Registers -available system useSystem Control -available system useSlave Interrupt Controller Slave Controller -available system use-available system use0000 0000 1000 0000 0000 0000 1000 nnnn 0000 0000 1001 000x 0000 0000 1001 0010 0000 0000 1001 nnnn 0000 0000 101x xxxn 0000 0000 110n nnnx 0000 0000 111x xxxx
Port Master Interrupt Controller Regs Master Interrupt Control Master Interrupt Mask Master Interrupt Control Shadow Master Interrupt Mask Shadow shadow registers disabled Port Port Timer/Counter Registers Timer Counter Count Timer Counter Count Timer Counter Count Timer Counter Control Keyboard Controller Registers Keyboard Controller Data Misc Functions Speaker Control Keyboard Ctrlr Command Status
Default Default
CF8-CFB Configuration Address 0000 1100 1111 10xx CFC-CFF Configuration Data 0000 1100 1111 11xx D00-FFFF -available system use-
Port CMOS Registers Default CMOS Memory Address Disa CMOS Memory Data (128 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) Disable port (CMOS Memory Address) bit-7. control occurs specific CMOS data locations (0-0Dh). Ports 72-73 used access locations CMOS. Ports 74-75 used access CMOS internal disabled.
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Default Default Port Slave Controller Registers Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Channel Base Current Address Channel Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read Write Mask Default
Port Port
Page Registers Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel Page Channel System Control Registers System Control
Port Slave Interrupt Controller Regs Default Slave Interrupt Control Slave Interrupt Mask Slave Interrupt Control Shadow Slave Interrupt Mask Shadow accessible shadow registers disabled
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Function Registers PCI-to-ISA Bridge Configuration Space PCI-to-ISA Bridge Header Registers Offset 10-27 28-2B 2F-2C 30-33 34-3B Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) Subsystem Read -reserved- (expan. base addr) -reserved- (unassigned) -reserved- (interrupt line) -reserved- (interrupt pin) -reserved- (min gnt) -reserved- (max lat) Default 1106 0596 0087 0200 Configuration Space PCI-to-ISA Bridge-Specific Registers Offset Plug Play Control Default -reserved- program) 51-53 -reserved00 Edge Level Selection Routing External MIRQ0-1 Routing INTB-A Routing INTD-C Routing External MIRQ2 PIRQ Configuration Control Internal Test Mode Control 5F-5D -reserved00 power-up default value depends external strapping Offset 61-60 63-62 65-64 67-66 69-68 6B-6A 6D-6C 6F-6E Offset 71-73 77-74 7B-78 7F-7C 85-86 8A-FF Distributed Channel Base Address Enable Channel Base Address Enable Channel Base Address Enable Channel Base Address Enable Serial Control Channel Base Address Enable Channel Base Address Enable Channel Base Address Enable Miscellaneous Subsystem Write -reservedGPIO Chip Select Control Programmable Chip Select Control PC/PCI Control Programmable Chip Select Mask Positive Decoding Control Positive Decoding Control Positive Decoding Control Positive Decoding Control -reservedTest Test Control -reservedDefault 0000 0000 0000 0000 0000 0000 0000 0000 Default 0000 0000 0000 0000 0000 0000
Configuration Space PCI-to-ISA Bridge-Specific Registers Offset 4F-4E Control Control Test Mode Clock Control Decode Control Keyboard Controller Control Type Control Miscellaneous Control Miscellaneous Control Miscellaneous Control -reservedIDE Interrupt Routing -reservedDMA Master Access Control Master Access Control Master Access Control Default 0300
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Function Registers Controller Configuration Space Header Registers Offset 13-10 17-14 1B-18 1F-1C 23-20 24-2F 30-33 34-3B Configuration Space Header Default Vendor 1106 Device 0571 Command 0080 Status 0280 Revision Programming Interface Class Code Base Class Code -reserved- (cache line size) Latency Timer Header Type Built Self Test (BIST) Base Address Data Command 000001F0 Base Address Control Status 000003F4 Base Address Data Command 00000170 Base Address Control Status 00000374 Base Address Master Control 0000CC01 -reserved- (unassigned) -reserved- (expan base addr) -reserved- (unassigned) Interrupt Line Interrupt Minimum Grant Maximum Latency Configuration Space IDE-Specific Registers Offset 4B-48 53-50 55-5F 61-60 62-67 69-68 69-6F 72-73 76-77 7A-7B 7E-7F 83-80 84-87 8B-88 8C-FF Configuration Space Registers Chip Enable Configuration -reserved- program) FIFO Configuration Miscellaneous Control Miscellaneous Control Miscellaneous Control Drive Timing Control Address Setup Time -reserved- program) Non-1F0 Port Access Timing Non-1F0 Port Access Timing UltraDMA33 Extd Timing Control UltraDMA FIFO Control -reservedIDE Primary Sector Size -reservedIDE Secondary Sector Size -reservedIDE Primary Status Primary Interrupt Control -reservedIDE Primary Command Primary Command -reservedIDE Secondary Status Secondary Interrupt Control -reservedIDE Secondary Command Secondary Command -reservedIDE Primary Descriptor Address -reservedIDE Secondary Descriptor Addr -reservedDefault
A8A8A8A8
03030303 0200 0200 0000 0000 0000 0000
Registers Controller (SFF 8038 v1.0 Compliant Offset Registers Default Primary Channel Command -reserved00 Primary Channel Status -reserved00 Primary Channel Table Addr Secondary Channel Command -reserved00 Secondary Channel Status -reserved00 Secondary Channel Table Addr
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Function Registers Controller Configuration Space Header Registers Offset 10-1F 23-20 24-3B 3E-3F Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST -reservedBase Address -reservedInterrupt Line Interrupt -reservedDefault 1106 3038 0000 0200 00000301 Registers Controller Offset 11-10 13-12 Registers Command Status Interrupt Enable Frame Number Frame List Base Address Start Frame Modify Port Status Control Port Status Control Default 0000 0000 0000 0000 00000000 0080 0080
Configuration Space USB-Specific Registers Offset 42-43 44-45 46-47 48-5F 61-BF C1-C0 C2-FF Control Miscellaneous Control Miscellaneous Control -reserved-reserved- (test only, program) -reserved- (test) -reservedSerial Release Number -reservedLegacy Support -reservedDefault
2000
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Function Registers Power Management Configuration Space Power Management Header Registers Offset Configuration Space Header Default Vendor 1106 Device 3050 Command 0000 Status 0280 Revision Programming Interface Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST 10-3F -reserved00 Default values changed writing offsets 61-63h. Configuration Space Power Management-Specific Registers Offset 45-44 47-46 4B-48 4E-4F 53-50 56-57 5B-58 5C-60 64-8F Offset 93-90 94-D1 D7-FF Power Management Debounce Control General Configuration Interrupt Configuration -reservedPrimary Interrupt Channel Secondary Interrupt Channel Power Mgmt Base (256 Bytes) Host Power Management Control Clock Stop Control -reservedGP0/1 Timer Control GPIO Select Wakeup Control -reservedGP2/3 Timer Control -reservedWrite value Offset (Prog Intfc) Write value Offset (Sub Class) Write value Offset (Base Class) -reservedSystem Management SMBus Base -reservedSMBus Control SMBus Host Slave Command SMBus Slave Address Port SMBus Slave Address Port SMBus Revision -reservedDefault 0000 0000 0000 0001 0000 0000 0000 0000 Default 0000 0001
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Space Power Management- Registers Default 0000 0000 Offset Offset 13-10 16-1F Offset 21-20 23-22 25-24 26-27 Offset 29-28 2B-2A 2D-2C 33-30 37-34 3B-38 3C-3F Offset 41-43 45-44 46-47 4B-48 4F-4C 50-FF Basic Control Status Registers Power Management Status Power Management Enable Power Management Control -reservedPower Management Timer -reservedProcessor Registers Processor Control Processor LVL2 Processor LVL3 -reservedGeneral Purpose Registers General Purpose Status General Purpose Enable General Purpose Enable -reservedGeneric Registers Global Status Global Enable Global Control -reservedSMI Command Primary Activity Detect Status Primary Activity Detect Enable Timer Reload Enable -reservedGeneral Purpose Registers General Purpose Control -reservedExternal Input Value -reservedGPI Port Input Value Port Output Value -reservedDefault 0000 0000 0000 0000 0000 Default 0000 0000 Default 0000 0000 0000 Default 0000 0000 0010 0000 0000 0000 0000 0000 0000 Default input input 7FFFFFFF
Space System Management Registers Offset System Management SMBus Host Status SMBus Slave Status SMBus Host Control SMBus Host Command SMBus Host Address SMBus Host Data SMBus Host Data SMBus Block Data SMBus Slave Control SMBus Shadow Command SMBus Slave Event SMBus Slave Data -reserved-
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Configuration Space
Mechanism These ports respond only double-word accesses. Byte word accesses will passed unchanged. Port CFB-CF8 Configuration Address Configuration Space Enable Disabled .default Convert configuration data port writes configuration cycles always reads 30-24 Reserved 23-16 Number Used choose specific system 15-11 Device Number Used choose specific device system 10-8 Function Number Used choose specific function selected device supports multiple functions Register Number Used select specific DWORD device's configuration space always reads Fixed Port CFF-CFC Configuration Data
Refer Specification Version further details operation above configuration registers.
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Configuration Space
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Port System Control Hard Disk Activity Status default .always reads Reserved Power-On Password Bytes Inaccessable .default=0 .always reads Reserved Address Line Enable disabled forced (real mode) default address line enabled High Speed Reset Normal Briefly pulse system reset switch from protected mode real mode
Register Descriptions
Legacy Ports This group registers includes Controllers, Interrupt Controllers, Timer/Counters well number miscellaneous ports originally implemented using discrete logic original PC/AT motherboards. registers listed integrated on-chip. These registers implemented precise manner backwards compatibility with previous generations hardware. These registers listed information purposes only. Detailed descriptions actions programming these registers included numerous industry publications (duplication that information here beyond scope this document). these registers reside space. Port Misc Functions Speaker Control always reads Reserved IOCHCK# Active. This when IOCHCK# signal asserted. Once set, this cleared setting bit-3 this register. Bit-3 should cleared enable recording next IOCHCK#. IOCHCK# generates enabled. Timer/Counter Output This reflects output Timer/Counter without synchronization. Refresh Detected This toggles every rising edge REFRESH# signal. IOCHCK# Disable Enable IOCHCK# assertions.default Force IOCHCK# inactive clear "IOCHCK# Active" condition bit-6 default=0 Reserved Speaker Enable. Disable .default Enable Timer/Ctr output drive SPKR Timer/Counter Enable. Disable .default Enable Timer/Counter
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Register Descriptions Legacy Ports
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Port Keyboard Mouse Status Keyboard Output Buffer Full Keyboard Output Buffer Empty. default Keyboard Output Buffer Full Input Buffer Full Input Buffer Empty. default Input Buffer Full System Flag Power-On Default default Self Test Successful Command Data Last write data write default Last write command write Keylock Status Locked Free Mouse Output Buffer Full Mouse output buffer empty. default Mouse output buffer holds mouse data General Receive Transmit Timeout error default Error Parity Error parity error (odd parity received). default Even parity occurred last byte received from keyboard mouse Control Register (R/W Commands 20h/60h) .always reads Reserved Compatibility Disable scan conversion Convert scan codes format; convert 2byte break sequences 1-byte PC-compatible break codes default Mouse Disable Enable Mouse Interface default Disable Mouse Interface Keyboard Disable Enable Keyboard Interface default Disable Keyboard Interface Keyboard Lock Disable Enable Keyboard Inhibit Function. default Disable Keyboard Inhibit Function System Flag .default=0 This read back status register bit-2 Mouse Interrupt Enable Disable mouse interrupts default Generate interrupt IRQ12 when mouse data comes output bufer Keyboard Interrupt Enable Disable Keyboard Interrupts. default Generate interrupt IRQ1 when output buffer been written.
Keyboard Controller Registers keyboard controller handles keyboard mouse interfaces. ports used: port port Reads from port return status byte. Writes port command codes (see command code list following register descriptions). Input output data transferred port "Control" register also available. accessable writing commands command port (port 64h); control byte written first sending command port, then sending control byte value. control register read sending command port 64h, waiting "Output Buffer Full" status then reading control byte value from port 60h. Traditional (non-integrated) keyboard controllers have "Input Port" "Output Port" with specific pins dedicated certain functions other pins available general purpose I/O. Specific commands provided these pins high low. outputs "open-collector" allow input these pins, output value that would high (non-driving) desired input value read input port. These ports defined follows: Code Code Input Port Keyboard Data Mouse Data Turbo (PS/2 mode only) user-defined user-defined user-defined user-defined undefined Code Code Output Port SYSRST (1=execute reset) GATEA20 (1=A20 enabled) Mouse Data Mouse Clock Keyboard Interrupt (IRQ1) Mouse Interrupt (IRQ Keyboard Clock Keyboard Data Test Port Code Code Keyboard Clock Mouse Clock Note: Command code transfers input port data output buffer. Command code copies output port values output buffer. Command code transfers test input port data output buffer. Port Keyboard Controller Input Buffer Only write port port bit-1 (1=full). Port Keyboard Controller Output Buffer Only read from port port bit-0 (0=empty).
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Register Descriptions Legacy Ports
7HFKQRORJLHV
&RQQHFW
VT82C596B
Port Keyboard Mouse Command This port used send commands keyboard mouse controller. command codes recognized VT82C596B listed table below. Note: VT82C596B Keyboard Controller compatible with VT82C42 Industry-Standard Keyboard Controller except that integrated nature, many input output port pins available externally general purpose pins (even though P13-P16 power-up strapping options). other words, many commands below provided "work", otherwise perform useful function (e.g., commands that P12-P17 high low). Also note that setting P10-11, P22-23, P26-27, T0-1 high directly serves useful purpose, since these bits used implement keyboard mouse ports directly controlled keyboard controller logic.
Table Keyboard Controller Command Codes
Code 21-3Fh 61-7Fh Keyboard Command Code Description Read Control Byte (next byte Control Byte) Read SRAM Data (next byte Data Byte) Write Control Byte (next byte Control Byte) Write SRAM Data (next byte Data Byte) Write nibble (bits 0-3) P10-P13 Output Keyboard Controller Version Test Password installed (always returns indicate installed) Disable Mouse Interface Enable Mouse Interface Mouse Interface Test (puts test results port 60h) (value: 0=OK, 1=clk stuck low, 2=clk stuck high, 3=data stuck 4=data stuck FF=general error) self test (returns not) Keyboard Interface Test (see Mouse Test) Disable Keyboard Interface Enable Keyboard Interface Return Version high high high high high high high high Code Keyboard Command Code Description Read input port (read P10-17 input data output buffer) Poll input port (read input data P11-13 repeatably bits status Poll input port high (same except P15-17) Unblock P22-23 (use before change active mode) Reblock P22-23 (protection mechanism Read mode (output mode info port output buffer (bit-0=0 ISA, PS/2) Read Output Port (copy P10-17 output port values port Write Output Port (data byte following written keyboard output port came from keyboard) Write Keyboard Output Buffer clear status bit-5 (write following byte keyboard) Write Mouse Output Buffer status bit-5 (write following byte mouse; value mouse input buffer appears have come from mouse) Write Mouse (write following byte mouse) Read test inputs (T0-1 read bits resp byte) P23-P21 command bits Pulse P23-P20 6usec command bits
other codes listed undefined.
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Register Descriptions Legacy Ports
7HFKQRORJLHV
&RQQHFW
VT82C596B
Ports C0-DF Slave Controller Channels Slave Controller control System Channels 4-7. There Slave Controller registers: Address Bits 15-0 0000 0000 1100 000x 0000 0000 1100 001x 0000 0000 1100 010x 0000 0000 1100 011x 0000 0000 1100 100x 0000 0000 1100 101x 0000 0000 1100 110x 0000 0000 1100 111x 0000 0000 1101 000x 0000 0000 1101 001x 0000 0000 1101 010x 0000 0000 1101 011x 0000 0000 1101 100x 0000 0000 1101 101x 0000 0000 1101 110x 0000 0000 1101 111x Register Name Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Read/Write Mask Bits
Controller Registers Ports 00-0F Master Controller Channels Master Controller control System Channels 0-3. There Master Controller registers: Address Bits 15-0 0000 0000 000x 0000 0000 0000 000x 0001 0000 0000 000x 0010 0000 0000 000x 0011 0000 0000 000x 0100 0000 0000 000x 0101 0000 0000 000x 0110 0000 0000 000x 0111 0000 0000 000x 1000 0000 0000 000x 1001 0000 0000 000x 1010 0000 0000 000x 1011 0000 0000 000x 1100 0000 0000 000x 1101 0000 0000 000x 1110 0000 0000 000x 1111 Register Name Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Base Current Address Base Current Count Status Command Write Request Write Single Mask Write Mode Clear Byte Pointer Master Clear Clear Mask Mask Bits
Note that bits address decoded. Note that bits address decoded. Master Controller compatible with Intel 8237 Controller chip. Detailed descriptions 8237 Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications. Slave Controller compatible with Intel 8237 Controller chip. Detailed description 8237 controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Ports 80-8F Page Registers There eight Page Registers, each channel. These registers provide bits 16-23 24-bit address each channel (bits 0-15 stored registers Master Slave Controllers). They located following Port addresses: Address Bits 15-0 0000 0000 1000 0111 0000 0000 1000 0011 0000 0000 1000 0001 0000 0000 1000 0010 0000 0000 1000 1111 0000 0000 1000 1011 0000 0000 1000 1001 0000 0000 1000 1010 Register Name Channel Page (M-0).RW Channel Page (M-1).RW Channel Page (M-2).RW Channel Page (M-3).RW Channel Page (S-0) Channel Page (S-1) Channel Page (S-2) Channel Page (S-3)
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Register Descriptions Legacy Ports
7HFKQRORJLHV
&RQQHFW
VT82C596B
Interrupt Controller Shadow Registers following shadow registers enabled setting Rx47 (offset PCI-ISA Bridge function register group). shadow registers enabled, they read back indicated port instead standard interrupt controller registers (writes interrupt controller register ports directed standard interrupt controller registers). Port Master Interrupt Control Shadow .always reads Reserved OCW3 OCW2 ICW4 ICW4 ICW1 Port Master Interrupt Mask Shadow .always reads Reserved T7-T3 Interrupt Vector Address Port Slave Interrupt Control Shadow .always reads Reserved OCW3 OCW2 ICW4 ICW4 ICW1 Port Slave Interrupt Mask Shadow .always reads Reserved T7-T3 Interrupt Vector Address Timer Counter Registers Ports 40-43 Timer Counter Registers There Timer Counter registers: Address Bits 15-0 0000 0000 010x xx00 0000 0000 010x xx01 0000 0000 010x xx10 0000 0000 010x xx11 Register Name Timer Counter Count Timer Counter Count Timer Counter Count Timer Counter Mode
Interrupt Controller Registers Ports 20-21 Master Interrupt Controller Master Interrupt Controller controls system interrupt channels 0-7. registers control Master Interrupt Controller. They are: Address Bits 15-0 0000 0000 001x xxx0 0000 0000 001x xxx1 Register Name Master Interrupt Control Master Interrupt Mask
Note that bits address decoded. Master Interrupt Controller compatible with Intel 8259 Interrupt Controller chip. Detailed descriptions 8259 Interrupt Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Ports A0-A1 Slave Interrupt Controller Slave Interrupt Controller controls system interrupt channels 8-15. slave system interrupt controller also occupies register locations: Address Bits 15-0 0000 0000 101x xxx0 0000 0000 101x xxx1 Register Name Slave Interrupt Control Slave Interrupt Mask
Note that address bits decoded. Slave Interrupt Controller compatible with Intel 8259 Interrupt Controller chip. Detailed descriptions 8259 Interrupt Controller operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
Note that bits address decoded. Timer Counters compatible with Intel 8254 Timer Counter chip. Detailed descriptions 8254 Timer Counter operation obtained from Intel Peripheral Components Data Book numerous other industry publications.
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Register Descriptions Legacy Ports
7HFKQRORJLHV
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VT82C596B
Offset Binary Range Range Description 00-3Bh 00-59h Seconds 00-3Bh 00-59h Seconds Alarm 00-3Bh 00-59h Minutes 00-3Bh 00-59h Minutes Alarm 12hr: 01-1Ch 01-12h Hours 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 01-12h Hours Alarm 12hr: 01-1Ch 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 01-07h Week Sun=1: 01-07h 01-1Fh 01-31h Month 01-0Ch 01-12h Month 00-63h 00-99h Year Register Update Progress DV2-0 Divide (010=ena keep time) RS3-0 Rate Select Periodic Interrupt Register SQWE 24/12 Register IRQF Register
CMOS Registers Port CMOS Address Disable.WO Enable Generation. asserted encountering IOCHCK# SERR# bus. Disable Generation .default CMOS Address (lower bytes).WO Port CMOS Data. CMOS Data (128 bytes) Note: Ports 70-71 accessed Rx5A bit-2 select internal RTC. Rx5A bit-2 zero, accesses ports 70-71 will directed external RTC.
Port CMOS Address CMOS Address (256 bytes). Port CMOS Data. CMOS Data (256 bytes) Note: Ports 72-73 accessed Rx5A bit-2 select internal RTC. Rx5A bit-2 zero, accesses ports 72-73 will directed external RTC.
Port CMOS Address CMOS Address (256 bytes). Port CMOS Data. CMOS Data (256 bytes) Note: Ports 74-75 accessed only Function Rx5B bit-1 enable internal SRAM Rx48 bit-3 (Port 74/75 Access Enable) enable port 74/75 access. Ports 70-71 compatible with industrystandards used access lower bytes 256-byte on-chip CMOS RAM. Ports 72-73 used access full extended 256byte space. Ports 74-75 used access full on-chip extended 256-byte space cases where on-chip disabled. system Real Time Clock (RTC) part "CMOS" block. control registers located specific offsets CMOS data area (00Dh 7D-7Fh). Detailed descriptions CMOS operation programming obtained from VT82887 Data Book numerous other industry publications. reference, definition register locations bits summarized following table:
Inhibit Update Transfers Periodic Interrupt Enable Alarm Interrupt Enable Update Ended Interrupt Enable function (read/write bit) Data Mode (0=BCD, 1=binary) Hours Byte Format (0=12, 1=24) Daylight Savings Enable
Note:
Interrupt Request Flag Periodic Interrupt Flag Alarm Interrupt Flag Update Ended Flag Unused (always read
Reads VBAT voltage Unused (always read
0E-7C Software-Defined Storage Registers (111 Bytes) Offset Extended Functions Date Alarm Month Alarm Century Field Binary Range Range 01-1Fh 01-31h 01-0Ch 01-12h 13-14h 19-20h
Note:
80-FF Software-Defined Storage Registers (128 Bytes) (See also Function Rx5B[3] Rx77[2-1])
Table CMOS Register Summary
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Register Descriptions Legacy Ports
7HFKQRORJLHV
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VT82C596B
Function Registers Bridge registers located function configuration space VT82C596B. These registers accessed through configuration mechanism address CF8/CFC. Configuration Space Header Offset Vendor 1106h Offset Device 0596h Offset Command always reads 15-8 Reserved Address Data Stepping Disable Enable .default always reads Reserved Special Cycle Enable .Normally default Master always reads Memory Space. Normally reads Space Normally reads test offset bit-4 set, access above indicated bits reversed: bit-3 above becomes read only (reading back bits above become read write (with default Offset Status Detected Parity Error write clear Signalled System Error. always reads Signalled Master Abort write clear Received Target Abort write clear Signalled Target Abort write clear 10-9 DEVSEL# Timing fixed (medium) Data Parity Detected. always reads Fast Back-to-Back Capable. always reads always reads Reserved Offset Revision Revision (00h first silicon) Offset Program Interface Offset Class Code 01h. Offset Class Code Offset Header Type Header Type Code. (Multifunction Device) Offset BIST Offset 2F-2C Subsystem offset 70-73 change value returned.
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Control Offset Control. Command Delay Normal .default Extra Extended Ready Disable .default Enable Slave Wait States Wait States .default Wait States Chipset Wait States Wait States .default Wait States Recovery Time Disable .default Enable Extend-ALE Disable .default Enable Wait States Wait State.default Wait States Write Disable .default Enable Offset Test Mode Refresh Arbitration program) default=0 XRDY Test Mode program). default=0 Port Fast Reset Disable .default Enable A20G Emulation program). default=0 Double Clock Disable (DMA Clock Clock) .default Enable (DMA Clock Clock) SHOLD Lock During INTA program) def=0 Refresh Request Test Mode program) def=0 Refresh Disable .default Enable Offset Clock Control. Latch IO16# Enable (recommended setting) default Disable MS16# Output Enable (recommended setting) default Disable Master Request Test Mode program).def=0 Reserved defined function) .default CLOCK Select Enable Clock PCICLK/4. default Clock selected bits Clock Select bit-3 PCICLK/3. default PCICLK/2 PCICLK/4 PCICLK/6 PCICLK/5 PCICLK/10 PCICLK/12 Note: Procedure CLOCK switching: Change value 2-0;
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Function Registers PCI-to-ISA Bridge
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VT82C596B
Offset Miscellaneous Control Master Write Wait States Wait States. default Wait State Gate INTRQ Disable. default Enable Flush Line Buffer Cycle Disable. default Enable Config Command Rx04 Access (Test Only) Normal: Bits 0-1=RO, 3=RW default Test Mode: Bits 0-1=RW, Bit-3=RO Reserved program) .default Reserved function) .default Burst Read Interruptability Allow burst reads interrupted. default Don't allow burst reads interrupted Post Memory Write Enable Disable. default Enable Post Memory Write function automatically enabled when Delay Transaction (see Rx47 bit-6 below) enabled, independent state this bit. Offset Miscellaneous Control Reset Source CPURST Reset default INIT Reset Delay Transaction Enable Disable. default Enable "Post Memory Write" function automatically enabled when this enabled, independent state Rx46 bit-0 above. EISA 4D0/4D1 Port Enable Disable (ignore ports 4D0-1) default Enable (ports 4D0-1 EISA specification) Interrupt Controller Shadow Register Enable Disable. default Enable Reserved (always program 0).default Note: Always mask this bit. This read back either must always programmed with Write Delay Transaction Time-Out Timer Enable Disable. default Enable Read Delay Transaction Time-Out Timer Enable Disable. default Enable Software Reset .write generate reset
Offset Decode Control Setting these bits enables indicated address range included ROMCS# decode: FFFE0000h-FFFEFFFFh default=0 FFF80000h-FFFDFFFFh default=0 FFF00000h-FFF7FFFFh (new). default=0 000E0000h-000EFFFFh (new) default=0 000E8000h-000EFFFFh (old). default=0 000E0000h-000E7FFFh (old) default=0 000D8000h-000DFFFFh default=0 000D0000h-000D7FFFh default=0 000C8000h-000CFFFFh default=0 000C0000h-000C7FFFh. default=0
Offset Keyboard Controller Control Timeout Test program) default Reserved program). default Mouse Lock Enable Disabled .default Enabled Reserved program). default Reserved function) default Offset Type Control Master Line Buffer. default=0 type Timing Channel default=0 type Timing Channel default=0 type Timing Channel default=0 type Timing Channel default=0 type Timing Channel default=0 type Timing Channel default=0 type Timing Channel default=0
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
DMA/Master Memory Access Control Memory Hole Bottom Address These bits correspond HA[23:16] .default=0 DMA/Master Memory Access Control Memory Hole Address (HA[23:16]) These bits correspond HA[23:16] .default=0 Note: Access memory defined memory hole will forwarded PCI. This function disabled address less than equal bottom address.
Offset Miscellaneous Control Voltage Interface Disable .default Enable Reserved Program). always reads Extra Port 74/75 Enable Disable .default Enable Integrated Controller Disable Enable.default Disable Integrated Controller Disable Enable.default Disable 512K Memory Decode Rx4E[15-12] select memory contents Rx4E[15-12] plus 512K memory .default Offset Interrupt Routing Wait PGNT Before Grant Master Disable .default Enable (must Select Access Devices Below 100h Access ports 00-FFh bus.default Access ports 00-FFh (applies external devices only; internal devices such mouse controller effected) Reserved program) default Second Channel Routing IRQ14 IRQ15.default IRQ10 IRQ11 Primary Channel Routing IRQ14.default IRQ15 IRQ10 IRQ11
4F-4E DMA/Master Memory Access Control 15-12 Memory DMA/Master accesses 0000 default 0001 1111 Note: Masters that access addresses higher than memory will directed bus. Forward E0000-EFFFF Accesses PCI.def=0 Forward A0000-BFFFF Accesses .def=0 Forward 80000-9FFFF Accesses .def=1 Forward 00000-7FFFF Accesses .def=1 Forward DC000-DFFFF Accesses .def=0 Forward D8000-DBFFF Accesses .def=0 Forward D4000-D7FFF Accesses .def=0 Forward D0000-D3FFF Accesses .def=0 Forward CC000-CFFFF Accesses .def=0 Forward C8000-CBFFF Accesses .def=0 Forward C4000-C7FFF Accesses .def=0 Forward C0000-C3FFF Accesses .def=0
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Plug Play Control Offset Reserved Program) default Reserved Offset Polarity always reads Reserved PIRQA# Non-invert (Level).default Invert (Edge) PIRQB# Non-invert (Level).default Invert (Edge) PIRQC# Non-invert (Level).default Invert (Edge) PIRQD# Non-invert (Level).default Invert (Edge) Note: PIRQA-D# normally connect interrupt pins INTA-D# (see definitions more information). Offset Routing .always reads Reserved PIRQ2 Routing (see routing table) Routing Table 0000 Disabled. default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 Reserved 1110 IRQ14 1111 IRQ15 Offset PIRQ Configuration (04h) .always reads Reserved PIRQ2 GPI21 Selection (Pin PIRQ2 GPI21 default PIRQ1 KEYLOCK Selection (Pin PIRQ1 default KEYLOCK PIRQ0 GPI20 Selection (Pin PIRQ0 default GPI20
Offset Routing PIRQA# Routing (see routing table) PIRQ0 Routing (see routing table) Offset Routing PIRQC# Routing (see routing table) PIRQB# Routing (see routing table) Offset Routing PIRQD# Routing (see routing table) PIRQ1 Routing (see routing table)
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Function Registers PCI-to-ISA Bridge
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VT82C596B
Offset Internal Test Mode .always reads Reserved Rx32 Rx7F Century Byte Disable. default Enable Reset Enable program) .default=0 SRAM Access Enable Disable. default Enable This internal disabled desired still able access internal SRAM ports 74-75. internal enabled, setting this does nothing (the internal SRAM should accessed either ports 70/71 72/73. Test Mode Enable program) .default=0 Offset Control. Gate Port Command Output Disable. default Enable Passive Release Disable. default Enable Internal Passive Release Disable. default Enable Dummy Request Disable. default Enable Extended Command Disable. default Enable External APIC Configuration External APIC Bus. default External APIC (disable XOE# APIC cycles) .always reads Reserved Line Buffer Disable cycles to/from line buffer Disable Line Buffer
Offset Control Bits this register latched from pins SD7-4 powerup read/write accessible changed after power-up change default strap setting: Keyboard RP16 latched from Keyboard RP15 latched from Keyboard RP14 latched from Keyboard RP13 latched from always reads Reserved Internal Enable Disable Enable .default Internal Mouse Enable Disable .default Enable Internal Enable Disable .default Enable External strap option values connecting indicated external 4.7K pullup (for driving during reset with 7407 open collector buffer (for shown suggested circuit below:
5(6(7
Note:
Figure Strap Option Circuit
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Distributed Serial Control Offset 61-60 Distributed Base Enable 15-4 Channel Base Address Bits 15-4 default Channel Enable Disable .default Enable always reads Reserved Offset 63-62 Distributed Base Enable 15-4 Channel Base Address Bits 15-4 default Channel Enable Disable .default Enable always reads Reserved Offset 65-64 Distributed Base Enable 15-4 Channel Base Address Bits 15-4 default Channel Enable Disable .default Enable always reads Reserved Offset 67-66 Distributed Base Enable 15-4 Channel Base Address Bits 15-4 default Channel Enable Disable .default Enable always reads Reserved Offset 69-68 Serial Control always reads 15-4 Reserved Serial Enable Disable .default Enable Serial Mode Continuous Mode .default Quiet Mode Start-Frame Width Clocks .default Clocks Clocks -reservedThe frame size fixed clocks. Offset 6B-6A Distributed Base Enable. 15-4 Channel Base Address Bits 15-4.default Channel Enable Disable. default Enable .always reads Reserved Offset 6D-6C Distributed Base Enable 15-4 Channel Base Address Bits 15-4.default Channel Enable Disable. default Enable .always reads Reserved Offset 6F-6E Distributed Base Enable 15-4 Channel Base Address Bits 15-4.default Channel Enable Disable. default Enable .always reads Reserved
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Miscellaneous General Purpose Offset 73-70 Subsystem 31-0 Subsystem Subsystem Vendor Write Only. Always reads back Contents read offset Offset 77-74 GPIO Chip Select Control always reads 31-30 Reserved PCS1# Internal (Pin Disable .default Enable PCS0# Internal (Pin Disable .default Enable Rx32 Remap Rx7F Century Byte Disable .default Enable Rx32 Write Protect Disable .default Enable Rx0D Write Protect Disable .default Enable Controller Shadow Registers Disable .default Enable always reads 23-22 Reserved PCS1# Enable (Pin Disable .default Enable PCS0# Enable (Pin Disable .default Enable MCCS# Enable (Pin Disable .default Enable GPO26 Enable (Pin Disable .default Enable GPO25 Enable (Pin Disable .default Enable GPO24 Enable (Pin Disable .default Enable GPO23 Enable (Pin Disable .default Enable GPO22 Enable (Pin Disable .default Enable
GPO21 Enable Disable. default Enable GPO20 Enable Disable. default Enable GPO19 Enable (Pin K16) Disable. default Enable GPO18 Enable (Pin Disable. default Enable GPO17 Enable (Pin Disable. default Enable Decode Subtractive default Positive APIC Enable Disable. default Enable GPI12 Enable (Pin P18) Disable. default Enable GPI11 Enable (Pin N17) Disable. default Enable GPI10 Enable (Pin P16) Disable. default Enable GPI9 Enable (Pin U19) Disable. default Enable GPI8 Enable (Pin H19) Disable. default Enable Internal APIC Disable. default Enable GPI0/IOCHCK, GPO[7-1]/LA[23-17] Select GPI0, GPO[7-1]. default IOCHCK, LA[23-17]
Bits 18-0 also control multi-function definitions. Refer General Purpose Inputs Outputs sections descriptions more information.
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Programmable Chip Select Mask PCS1 Port Address Mask bits PCS0 Port Address Mask bits
Offset 7B-78 Programmable Chip Select Control 31-16 PCS1 Port Address [15-0] 15-0 PCS0 Port Address [15-0] Offset 7F-7C PC/PCI Control always reads 31-11 Reserved Pair Enable Disable .default Enable Pair Enable Disable .default Enable Pair Enable Disable .default Enable Channel Enable Disable .default Enable Channel Enable Disable .default Enable Channel Enable Disable .default Enable always reads Reserved Channel Enable Disable .default Enable Channel Enable Disable .default Enable Channel Enable Disable .default Enable Channel Enable Disable .default Enable
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Positive Decoding Control Positive Decoding Disable. default Enable Positive Decoding Disable. default Enable Decode Range 3BCh-3BFh, 7BCh-7BEh default 378h-37Fh, 778h-77Ah 278h-27Fh, 678h-67Ah -reserved3 Game Port Positive Decoding Disable. default Enable MIDI Positive Decoding Disable. default Enable MIDI Decode Range 300h-303h. default 310h-313h 320h-323h 330h-333h
Offset Positive Decoding Control On-Board Port Positive Decoding Disable .default Enable Microsoft-Sound System Port Positive Decoding Disable .default Enable Microsoft-Sound System Decode Range 0530h-0537h .default 0604h-060Bh 0E80-0E87h 0F40h-0F47h APIC Positive Decoding Disable .default Enable BIOS Positive Decoding Disable .default Enable PCS1 Positive Decoding Disable .default Enable PCS0 Positive Decoding Disable .default Enable
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Positive Decoding Control .always reads Reserved Decoding Range Primary default Secondary Sound Blaster Positive Decoding Disable. default Enable Sound Blaster Decode Range 220h-22Fh, 230h-233h default 240h-24Fh, 250h-253h 260h-26Fh, 270h-273h 280h-28Fh, 290h-293h
Offset Positive Decoding Control Port Positive Decoding Disable .default Enable COM-Port Decode Range 3F8h-3FFh (COM1) .default 2F8h-2FFh (COM2) 220h-227h 228h-22Fh 238h-23Fh 2E8h-2EFh (COM4) 338h-33Fh 3E8h-3EFh (COM3) Port Positive Decoding Disable .default Enable COM-Port Decode Range 3F8h-3FFh (COM1) .default 2F8h-2FFh (COM2) 220h-227h 228h-22Fh 238h-23Fh 2E8h-2EFh (COM4) 338h-33Fh 3E8h-3EFh (COM3)
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Control .always reads Reserved PCLK Input Delay Select CLK66 Feedback Delay Select
Offset Test UltraDMA-66 Test Disable .default Enable Port Test Disable .default Enable Port Test Select always reads Reserved
Offset Test always reads Reserved Enable.default Disable Test Mode Disable .default Enable Test Mode Select
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Function Registers PCI-to-ISA Bridge
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Programming Interface Master Capability. fixed (Supported) .always reads Reserved Programmable Indicator Secondary fixed Supports both modes (may either mode writing bit-2) Channel Operating Mode Secondary Compatibility Mode (fixed addressing) Native Mode (flexible addressing) Programmable Indicator Primary. fixed Supports both modes (may either mode writing bit-0) Channel Operating Mode Primary Compatibility Mode (fixed addressing) Native Mode (flexible addressing) Compatibility Mode (fixed IRQs addresses): Command Block Control Block Registers Channel Registers 1F0-1F7 170-177 Native Mode (registers programmable space) Command Block Control Block Registers Channel Registers @offset @offset @offset @offset Command register blocks bytes space Control registers bytes space (only byte used) Offset Class Code (01h=IDE Controller) Offset Base Class Code (01h=Mass Storage Ctrlr) Offset Latency Timer (00h) Latency Timer.default=0 .always reads Reserved Offset Header Type (00h). Offset BIST (00h)
Function Registers Enhanced Controller This Enhanced controller interface fully compatible with 8038i v.1.0 specification. There sets software accessible registers configuration registers Master registers. configuration registers located function configuration space VT82C596B. Master registers defined SFF8038i v1.0 specification. Configuration Space Header Offset Vendor (1106h=VIA) Offset Device (0571h=IDE Controller) Offset Command always reads 15-10 Reserved Fast Back Back Cycles .fixed (disabled) SERR# Enable.fixed (disabled) Address Stepping default=1 (enabled) recommends that this always provide additional address decode time devices. Parity Error Response.fixed (disabled) Palette Snoop .fixed (disabled) Memory Write Invalidate .fixed (disabled) Special Cycles .fixed (disabled) Master default (disabled) operation issued only when "Bus Master" enabled. Memory Space.fixed (disabled) Space default (disabled) When "I/O Space" disabled, device will respond addresses both compatible native mode. Offset Status Detected Parity Error default=0 Signalled System Error. default=0 Received Master Abort. default=0 Received Target Abort default=0 Signalled Target Abort .Fixed 10-9 DEVSEL# Timing .default (medium) Data Parity Detected. default=0 Fast Back Back .Fixed always reads Reserved Offset Revision Revision Code Controller Logic Block
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Function Registers Enhanced Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Interrupt Line (0Eh) Offset Interrupt (00h) Interrupt Routing Mode Legacy mode interrupt routing. default Native mode interrupt routing Offset (00h) Offset Latency (00h).
Offset 13-10 Data Command Base Address. Specifies byte address space. .always read 31-16 Reserved 15-3 Port Address. default=01F0h Fixed 001b fixed Offset 17-14 Control Status Base Address. Specifies byte address space which only third byte active (i.e., 3F6h default base address 3F4h). .always read 31-16 Reserved 15-2 Port Address. default=03F4h Fixed fixed Offset 1B-18 Data Command Base Address Specifies byte address space. .always read 31-16 Reserved 15-3 Port Address default=0170h Fixed 001b fixed Offset 1F-1C Control Status Base Address Specifies byte address space which only third byte active (i.e., 376h default base address 374h). .always read 31-16 Reserved 15-2 Port Address default=0374h Fixed fixed Offset 23-20 Master Control Regs Base Address Specifies byte address space compliant with SFF8038i specification. .always read 31-16 Reserved 15-4 Port Address default=CC0h Fixed 0001b fixed
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Function Registers Enhanced Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
IDE-Controller-Specific Confiiguration Registers Offset Chip Enable. always reads Reserved Reserved Program).R/W, default Primary Channel Enable. default (disabled) Secondary Channel Enable default (disabled) Offset Configuration Primary Read Prefetch Buffer Disable .default Enable Primary Post Write Buffer Disable .default Enable Secondary Read Prefetch Buffer Disable .default Enable Secondary Post Write Buffer Disable .default Enable Reserved Change). default=0 Reserved Change). default=1 Reserved Change). default=1 Reserved Change). default=0 Offset Reserved Program) always reads Reserved Reserved Program). default Offset FIFO Configuration .always reads Reserved Threshold Primary Channel default Threshold Secondary Channel default
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Function Registers Enhanced Controller
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VT82C596B
Offset Miscellaneous Control Primary Channel Read FIFO Flush Enable FIFO flush read when interrupt asserts primary channel. .default=1 (enabled) Secondary Channel Read FIFO Flush Enable FIFO flush Read when interrupt asserts secondary channel. Default=1 (enabled) Primary Channel End-of-Sector FIFO Flush Enable FIFO flush each sector primary channel. Default=0 (disabled) Secondary Channel End-of-Sector FIFO Flush Enable FIFO flush each sector secondary channel. Default=0 (disabled) .always reads Reserved DRDY Pulse Width Maximum DRDY# pulse width after cycle count. Command will deassert spite DRDY# status avoid system ready hang. limitation. default clocks clocks clocks
Offset Miscellaneous Control always reads Reserved Master Read Cycle IRDY# Wait States wait states wait state.default Master Write Cycle IRDY# Wait States wait states wait state.default Reserved Program).R/W, default Master Status Register Read Retry Retry master status register read when master write operation read complete Disabled Enabled.default Reserved Program).R/W, default UltraDMA Host Must Wait First Strobe Before Termination Enabled.default Disabled Offset Miscellaneous Control always reads Reserved Interrupt Steering Swap Don't swap channel interrupts.default Swap interrupts between channels always reads Reserved Memory Read Multiple Command Disable .default Enable Memory Read Invalidate Command Disable .default Enable Secondary Channel Threshold Enable Disable (data transfer starts immediately FIFO empty) Enable (data transfer will start until FIFO filled threshold bits Rx43) .default Primary Channel Threshold Enable Disable (data transfer starts immediately FIFO empty) Enable (data transfer will start until FIFO filled threshold bits Rx43) .default
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Function Registers Enhanced Controller
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&RQQHFW
VT82C596B
Offset 53-50 UltraDMA Extended Timing Control Drive UltraDMA-Mode Enable Method Enable using "Set Feature" command. Enable setting bit-30 this register Drive UltraDMA-Mode Enable Disable. default Enable UltraDMA-Mode Operation Drive Transfer Mode Based Mode default Based UltraDMA Mode .always reads 28-26 Reserved 25-24 Drive Cycle Time 30nsec @33MHz) default Drive UltraDMA-Mode Enable Method Drive UltraDMA-Mode Enable Drive Transfer Mode .always reads Reserved Clock Source MHz. default .always reads Reserved 17-16 Drive Cycle Time 12-10 Drive UltraDMA-Mode Enable Method Drive UltraDMA-Mode Enable Drive Transfer Mode .always reads Reserved Drive Cycle Time Drive UltraDMA-Mode Enable Method Drive UltraDMA-Mode Enable Drive Transfer Mode .always reads Reserved Clock Source MHz. default .always reads Reserved Drive Cycle Time
Offset 4B-48 Drive Timing Control following fields define Active Pulse Width Recovery Time DIOR# DIOW# signals: 31-28 Primary Drive Active Pulse Width. def=1010b 27-24 Primary Drive Recovery Time def=1000b 23-20 Primary Drive Active Pulse Width. def=1010b 19-16 Primary Drive Recovery Time def=1000b 15-12 Secondary Drive Active Pulse Width def=1010b 11-8 Secondary Drive Recovery Time def=1000b Secondary Drive Active Pulse Width def=1010b Secondary Drive Recovery Time def=1000b actual value each field encoded value field plus indicates number clocks. Offset Address Setup Time Primary Drive Address Setup Time Primary Drive Address Setup Time Secondary Drive Address Setup Time Secondary Drive Address Setup Time each field above: .default Offset Secondary Non-1F0 Port Access Timing. DIOR#/DIOW# Active Pulse Width. def=1111b DIOR#/DIOW# Recovery Time. def=1111b actual value each field encoded value field plus indicates number clocks. Offset Primary Non-1F0 Port Access Timing` DIOR#/DIOW# Active Pulse Width. def=1111b DIOR#/DIOW# Recovery Time. def=1111b actual value each field encoded value field plus indicates number clocks.
Each byte defines UltraDMA operation indicated drive. definitions same within each byte.
Revision June 1999
-51-
Function Registers Enhanced Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset 61-60 Primary Sector Size .always reads 15-12 Reserved 11-0 Number Bytes Sector default=200h Offset 69-68 Secondary Sector Size .always reads 15-12 Reserved 11-0 Number Bytes Sector .def=200h (512 bytes)
Offset UltraDMA FIFO Control Reserved Program). default=0 Split Change Channel Enable .default Disable always reads Reserved Change Drive Clear FIFO Internal States Disabled Enabled .default Dummy FIFO Push After Transfer Enabled Disabled .default This normally effective handling transfer lengths that doubleword multiples Complete Cycle with Transfer Size Less Than FIFO Size Enabled.default Disabled
Revision June 1999
-52-
Function Registers Enhanced Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Secondary Status Interrupt Status Prefetch Buffer Status Post Write Buffer Status Read Prefetch Status Write Prefetch Status Operation Complete .always reads Reserved Offset Secondary Interrupt Control .always reads Reserved Flush FIFO Before Generating Interrupt Desable default Enable Offset Secondary Command Reload Sector Size After Last Command Register Write .always reads Reserved Offset Secondary Command Controller Perform Mode Data Port Prefetch Controller Perform Mode Data Port Buffer Write Controller Perform Mode Read Pipeline Operation Controller Perform Mode Write Pipeline Operation Stop Master .always reads Reserved
Offset Primary Status Interrupt Status Prefetch Buffer Status Post Write Buffer Status Read Prefetch Status Write Prefetch Status Operation Complete always reads Reserved Offset Primary Interrupt Control. always reads Reserved Flush FIFO Before Generating Interrupt Desable.default Enable Offset Primary Command Reload Sector Size After Last Command Register Write always reads Reserved Offset Primary Command Controller Perform Mode Data Port Prefetch Controller Perform Mode Data Port Buffer Write Controller Perform Mode Read Pipeline Operation Controller Perform Mode Write Pipeline Operation Stop Master always reads Reserved
Revision June 1999
-53-
Function Registers Enhanced Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Registers These registers compliant with 8038I v1.0 standard. Refer 8038I v1.0 specification further details. Offset Primary Channel Command Offset Primary Channel Status Offset Primary Channel Table Address
Offset 83-80 Primary Descriptor Address Offset 8B-88 Secondary Descriptor Address
Offset Secondary Channel Command Offset Secondary Channel Status Offset Secondary Channel Table Address
Revision June 1999
-54-
Function Registers Enhanced Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Revision (nnh) Silicon Revision Code indicates first silicon) Offset Programming Interface (00h) Offset Class Code (03h) Offset Base Class Code (0Ch) Offset Latency Timer Timer Value default Offset Header Type (00h). Offset 23-20 Register Base Address. .always reads 31-16 Reserved 15-5 Register Base Address. Port Address base 32-byte Register block, corresponding AD[15:5] 00001b Offset Interrupt Line (00h) .always reads Reserved Interrupt Routing default 0000 Disabled. default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disabled Offset Interrupt (04h)
Function Registers Universal Serial Controller This host controller interface fully compatible with UHCI specification v1.1. There sets software accessible registers: configuration registers registers. configuration registers located function configuration space VT82C596B. registers defined UHCI v1.1 specification. Configuration Space Header Offset Vendor Vendor (1106h Technologies) Offset Device Device (3038h VT82C596B Controller) Offset Command always reads 15-8 Reserved Address Stepping default=0 (disabled) Reserved (parity error response) .fixed Reserved (VGA palette snoop) .fixed Memory Write Invalidate default=0 (disabled) Reserved (special cycle monitoring) .fixed Master default=0 (disabled) Memory Space. default=0 (disabled) Space default=0 (disabled) Offset Status Reserved (detected parity error). always reads Signalled System Error. default=0 Received Master Abort. default=0 Received Target Abort default=0 Signalled Target Abort default=0 10-9 DEVSEL# Timing Fast Medium .default (fixed) Slow Reserved always reads Reserved
Revision June 1999
-55-
Function Registers Universal Serial Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
USB-Specific Configuration Registers Offset Miscellaneous Control Memory Command Option Support Memory-Read-Line, Memory-ReadMultiple, Memory-Write-and-Invalidate .default Only support Memory Read, Memory Write Commands Babble Option Automatically disable babbled port when babble occurs.default Don't disable babbled port Parity Check Option Disable PERR# generation.default Enable parity check PERR# generation always reads Reserved Data Length Option Support length 1280.default Support length 1023 Power Management Disable power management.default Enable power management Option burst access.default burst access Wait States Zero wait .default wait Offset Miscellaneous Control Improvement Specification Compliant. default stuffing error occurs before EOP, receiver will accept packet Specification Compliant stuffing error occurs before EOP, receiver will ignore packet Patch Read Resume Issue Enable (Fix Bug) (Normal Setting). default Disable (when port reset resume status, controller device attached other port) Patch Bit-Time spec says that device must assert least times. Enable (accept bit-time EOP) default Disable (require bit-time EOP) Hold Request Successive Accesses Disable Enable default Setting this "enable" causes system treat request higher priority Frame Counter Test Mode Disable. default Enable Trap Option trap 60/64 status bits only when trap 60/64 enable bits set. default trap 60/64 status bits without checking enable bits A20gate Pass Through Option Pass through A20GATE command sequence defined UHCI default Don't pass through Write port (ff) .always reads Reserved
Revision June 1999
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Function Registers Universal Serial Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Registers These registers compliant with UHCI v1.1 standard. Refer UHCI v1.1 specification further details. Offset Command Offset Status Offset Interrupt Enable Offset Frame Number Offset Frame List Base Address Offset Start Frame Modify Offset 11-10 Port Status Control Offset 13-12 Port Status Control Offset 1F-14 Reserved
Offset Serial Release Number Release Number. always reads
Offset C1-C0 Legacy Support 15-0 UHCI v1.1 Compliant always reads 2000h
Revision June 1999
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Function Registers Universal Serial Controller
7HFKQRORJLHV
&RQQHFW
VT82C596B
Function Registers Power Management SMBus This section describes ACPI (Advanced Configuration Power Interface) Power Management system VT82C596B which includes System Management (SMBus) interface controller. power management system VT82C596B supports both ACPI legacy power management functions compatible with v1.2 ACPI v1.0 specifications. Configuration Space Header Offset Vendor Vendor (1106h Technologies) Offset Device Device (3050h ACPI Power Mgmt) Offset Command always reads 15-8 Reserved Address Stepping .fixed Reserved (parity error response) .fixed Reserved (VGA palette snoop) .fixed Memory Write Invalidate .fixed Reserved (special cycle monitoring) .fixed Master .fixed Memory Space.fixed Space .fixed Offset Status Detected Parity Error always reads Signalled System Error. always reads Received Master Abort. always reads Received Target Abort always reads Signalled Target Abort always reads 10-9 DEVSEL# Timing Fast Medium .default (fixed) Slow Reserved Data Parity Detected. always reads Fast Back Back Capable always reads always reads Reserved Offset Revision (nnh) Silicon Revision Code. default Offset Programming Interface (00h) value returned this register changed writing desired value Configuration Function offset 61h. Offset Class Code (00h) value returned this register changed writing desired value Configuration Function offset 62h. Offset Base Class Code (00h) value returned this register changed writing desired value Configuration Function offset 63h. Offset Latency Timer Timer Value .default Offset Header Type (00h).
Revision June 1999
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Function Registers Power Management SMBus
7HFKQRORJLHV
&RQQHFW
VT82C596B
Power Management-Specific Configuration Registers Offset Debounce Control always reads Reserved Debounce PWRBTN# Inputs 200us Disable .default Enable always reads Reserved Offset General Configuration (00h) Enable ACPI Base Disable access ACPI block. default Allow access Power Management Register Block (see offset 4B-48 base address this register block). definitions registers Power Management Register Block included later this document, following Power Management Subsystem overview. ACPI Timer Reset Disable. default Enable Reserved Program) .default ACPI Timer Count Select 24-bit Timer. default 32-bit Timer Enable Signal Gated with PSON (SUSC#) Soft-Off Mode Disable. default Enable Clock Throttling Clock Selection usec (512 usec cycle time) default msec msec cycle time) Reserved Program) .default
Revision June 1999
-59-
Function Registers Power Management SMBus
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset 45-44 Primary Interrupt Channel (0000h) Ena/Disa IRQ15 Primary Intrpt Channel Ena/Disa IRQ14 Primary Intrpt Channel Ena/Disa IRQ13 Primary Intrpt Channel Ena/Disa IRQ12 Primary Intrpt Channel Ena/Disa IRQ11 Primary Intrpt Channel Ena/Disa IRQ10 Primary Intrpt Channel Ena/Disa IRQ9 Primary Intrpt Channel Ena/Disa IRQ8 Primary Intrpt Channel Ena/Disa IRQ7 Primary Intrpt Channel Ena/Disa IRQ6 Primary Intrpt Channel Ena/Disa IRQ5 Primary Intrpt Channel Ena/Disa IRQ4 Primary Intrpt Channel Ena/Disa IRQ3 Primary Intrpt Channel .always reads Reserved Ena/Disa IRQ1 Primary Intrpt Channel Ena/Disa IRQ0 Primary Intrpt Channel
Offset Interrupt Configuration (00h) ATX/AT Power Indicator.RO .default SUSC State always reads Reserved SUSC Default Enable Status Interrupt Assignment 0000 Disabled .default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 IRQ15
Offset 47-46 Secondary Interrupt Channel (0000h) Ena/Disa IRQ15 Secondary Intr Channel Ena/Disa IRQ14 Secondary Intr Channel Ena/Disa IRQ13 Secondary Intr Channel Ena/Disa IRQ12 Secondary Intr Channel Ena/Disa IRQ11 Secondary Intr Channel Ena/Disa IRQ10 Secondary Intr Channel Ena/Disa IRQ9 Secondary Intr Channel Ena/Disa IRQ8 Secondary Intr Channel Ena/Disa IRQ7 Secondary Intr Channel Ena/Disa IRQ6 Secondary Intr Channel Ena/Disa IRQ5 Secondary Intr Channel Ena/Disa IRQ4 Secondary Intr Channel Ena/Disa IRQ3 Secondary Intr Channel .always reads Reserved Ena/Disa IRQ1 Secondary Intr Channel Ena/Disa IRQ0 Secondary Intr Channel
Revision June 1999
-60-
Function Registers Power Management SMBus
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Clock Stop Control .always reads Reserved Internal Clock Stop Idle Disable. default Enable Internal Clock Stop During Disable. default Enable Internal Clock Stop During Suspend Disable. default Enable
Offset 4B-48 Power Management Base always reads 31-16 Reserved 15-7 Power Management Register Base Address. Port Address base 128-byte Power Management Register block, corresponding AD[15:7]. "I/O Space" offset bit-7 enables access this register block. definitions registers Power Management Register Block included later this document, following Power-Management-Specific Configuration register descriptions Power Management Subsystem overview. 0000001b Offset Host Power Management Control. Thermal Duty Cycle (THM_DTY) This 4-bit field determines duty cycle STPCLK# signal when THRM# asserted low. field decoded follows: 0000 Reserved 0001 0-6.25% 0010 6.25-12.50% 0011 18.75-25.00% 0100 31.25-37.50% 0101 37.50-43.75% 0110 43.75-50.00% 0111 50.00-56.25% 1000 56.25-62.50% 1001 62.50-68.75% 1010 68.75-75.00% 1011 75.00-87.50% 1100 75.00-81.25% 1101 81.25-87.50% 1110 87.50-93.75% 1111 93.75-100% always reads Reserved SRAM Disable .default Enable (power down cache SRAM) Stop Grant Cycle Select From Halt Stop Grant Cycle .default From Stop Grant Cycle This combined with space Rx2C[3] controlling start STPCLK# assertion during system suspend mode: Rx2C[3] Rx4C[0] Function Function STPCLK# Assertion Space Space Immediate Wait Halt Stop Grant cycle Wait Stop Grant cycle
Revision June 1999
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Function Registers Power Management SMBus
7HFKQRORJLHV
&RQQHFW
VT82C596B
Timer Start setting this timer loads value defined bits 15-8 this register starts counting down. timer reloaded occurrence certain peripheral events enabled Timer Reload Enable Register (Power Management Space Offset 38h). such event occurs timer counts down zero, then Timer Timeout Status (bit-2 Global Status register Power Management Register Space Offset 28h). Additionally, Timer Timeout Enable (bit-2 Global Enable register Power Management Register Space Offset 2Ah), then generated. Timer Automatic Reload This enable timer reload automatically after counting down Timer Base Disable. default 1/16 second second minute
Offset 53-50 GP0/1 Timer Control (0000 0000h) 31-30 Conserve Mode Timer Count Value 1/16 second .default second second minute Conserve Mode Status This reads when Conserve Mode Conserve Mode Enable Disable .default Enable 27-26 Secondary Event Timer Count Value milliseconds.default milliseconds second 0.25 milliseconds Secondary Event Occurred Status This reads indicate that secondary event occurred resume system from suspend) secondary event timer counting down. Secondary Event Timer Enable Disable .default Enable 23-16 Timer Count Value (base defined bits 5-4) Write load count value; Read current count 15-8 Timer Count Value (base defined bits 1-0) Write load count value; Read current count Timer Start setting this timer loads value defined bits 23-16 this register starts counting down. timer reloaded occurrence certain peripheral events enabled Timer Reload Enable Register (Power Management Space Offset 38h). such event occurs timer counts down zero, then Timer Timeout Status (bit-3 Global Status register Power Management Register Space Offset 28h). Additionally, Timer Timeout Enable (bit-3 Global Enable register Power Management Register Space Offset 2Ah), then generated. Timer Automatic Reload This enable timer reload automatically after counting down Timer Base Disable .default msec second minute
Revision June 1999
-62-
Function Registers Power Management SMBus
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Wakeup Control .always reads Reserved Wakeup Soft Disable. default Enable
Offset GPIO Select GPO21 Function (Pin T18) SUSST2#.default GPO21 Power Well Output Gating Disable .default Enable SUSC# Level SUSC# STR.default SUSC# GPO20 Function (Pin T17) SUSST1#.default GPO20 GPO15 Function (Pin V19) SUSB#.default GPO15 GPO16 Function (Pin U18) SUSC#.default GPO16 GPO8 Function (Pin T19) GPO8 (ACPI Rx4C[8] .default Output Output Output
Revision June 1999
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Function Registers Power Management SMBus
7HFKQRORJLHV
&RQQHFW
VT82C596B
Offset Programming Interface Read Value Rx09 Read Value value returned register offset (Programming Interface) changed writing desired value this location.
Offset 5B-58 GP2/3 Timer Control (0000 0000h) always reads 31-24 Reserved 23-16 Timer Count Value (base defined bits 5-4) Write load count value; Read current count 15-8 Timer Count Value (base defined bits 1-0) Write load count value; Read current count Timer Start setting this timer loads value defined bits 23-16 this register starts counting down. timer reloaded occurrence certain peripheral events enabled Timer Reload Enable Register (Power Management Space Offset 38h). such event occurs timer counts down zero, then Timer Timeout Status (bit-13 Global Status register Power Management Register Space Offset 28h). Additionally, Timer Timeout Enable (bit-13 Global Enable register Power Management Register Space Offset 2Ah), then generated. Timer Automatic Reload This enable timer reload automatically after counting down Timer Base Disable .default msec second minute Timer Start setting this timer loads value defined bits 15-8 this register starts counting down. timer reloaded occurrence certain peripheral events enabled Timer Reload Enable Register (Power Management Space Offset 38h). such event occurs timer counts down zero, then Timer Timeout Status (bit-12 Global Status register Power Management Re
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