Bt497 Bt498 Distinguishing Features pixel clock generation (
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Monolithic CMOS Triple RAMDACBt497/8 designed specifically high-performance, high-resolution color graphics applications. architecture enables display true-color 1600 1280 bit-mapped color graphics refresh rates. wide input pixel port internal multiplexing modes enable TTL-compatible interfacing frame buffer, while maintaining PLL-generated MHz, externally provided video data rates required high-refresh-rate, high-resolution color graphics. Bt497/8 supports pixel clock generation, supporting variety frequencies using divisor scheme. This decreases system cost elimination multiple crystal oscillators that used support variety monitor refresh rates. Bt497/8 contains three color lookup tables, three gamma 2.2), triple 8-bit video converters, programmable cursor, fully programmable video timing generator. Bt497/8 RAMDAC allows different display modes operation each pixel. Utilizing window-type scheme, each pixel control bits maps accompanying pixel data user-defined display mode. window identification index addresses color model table which determines description pixel data. example, separate windows displaying 24-plane true color, 8-plane pseudocolor, 24-plane double-buffer true color exist within single frame. programmable setup IRE) included.
Bt497 Bt498
Distinguishing Features
pixel clock generation (M/N) Supports true-color 1600 1280 resolutions 128-bit input pixel port width operation Multiple display modes pixel basis High-resolution true-color support multiplexed pixel port support Programmable pixel format Three color palette RAMs Three gamma ROMs 2.2) programmable cursor Programmable setup IRE) VRAM shift clock generation On-chip user-definable video timing generator JTAG support 160-pin (Bt497), 208-pin (Bt498) PQFP packages LVTTL (3.3 interface
Functional Block Diagram
RANGE XTAL[1] XTAL[2] VREF FSADJ
Applications
CLOCK CLOCK* Clock Pixel Clock Gamma Cursor Pixel Unpacking Logic P[127:0] Pixel Port Registers Gamma Cursor Gamma Cursor JTAG Cursor COMP2 COMP
Pixel Load Control
High-resolution color graphics CAE/CAD/CAM Image processing Instrumentation Desktop publishing
STSCAN FIELD CSYNC* SCEN*
Video Timing Generator
Control
Data
C[1,0]
D[7:0]
Brooktree
Brooktree Corporation 9868 Scranton Road Diego, 92121-3707 619-452-7580 1-800-2-BT-APPS FAX: 619-452-1249 Internet: apps@brooktree.com L497001 Rev.
Ordering Information
Model Number Bt497KHF135 Bt498KHF220 Package 160-Pin PQFP 208-Pin PQFP Ambient Temperature Range 0-70° with LFPM airflow 0-70° with LFPM airflow
Copyright 1995 Brooktree Corporation. rights reserved. Print date: February, 1996 Brooktree reserves right make changes products specifications improve performance, reliability, manufacturability. Information furnished Brooktree Corporation believed accurate reliable. However, responsibility assumed Brooktree Corporation use; infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Brooktree Corporation. Brooktree products designed intended life support appliances, devices, systems where malfunction Brooktree product reasonably expected result personal injury death. Brooktree customers using selling Brooktree products such applications their risk agree fully indemnify Brooktree damages resulting from such improper sale. Brooktree registered trademark Brooktree Corporation. Product names services listed this publication identification purposes only, trademarks registered trademarks their respective companies. other marks mentioned herein property their respective holders. Specifications subject change without notice.
PRINTED UNITED STATES AMERICA
TABLE CONTENTS
List Figures List Tables viii Circuit Description
Introduction Descriptions Interface Reading/Writing Color Data Additional Information Clock Generation Frame Buffer Interface Color Model Selection Window Identification Lookup Table
Shadow Direct Pseudocolor Linear Color Nonlinear True Colorand Nonlinear Gray Scale
Overlay/Underlay Operation
Transparent Overlay Enable Control Transparent Overlay Mask Register Transparent Overlay Color Register
On-chip Cursor Operation Cursor Color Cursor Positioning Cursor Interlace Operation
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TABLE CONTENTS
Bt497/498
Timing Generator
System Reset Timing Generator Test Features Timing Generator Display Formats Output Signals. Noninterlaced Timing Interlaced Timing.
Monitor Identification Control Interface Video Generation
Internal Registers
Control Register Pixel Format Control Register User Control Register Window Transfer Control Register Overlay Mask Control Register Overlay Color Register. Signature Analysis Control Register Control Register Timing Generator Control Register Vertical Blank Negation Point Register Vertical Blank Assertion Point Register Vertical Sync. Negation Point Register Vertical Sync. Assertion Point Register Horizontal Serration Negation Point Register Horizontal Blank Negation Point Register Horizontal Blank Assertion Point Register. Horizontal Sync. Negation Point Register Horizontal Sync. Assertion Point Register. Horizontal SCEN Negation Point Register Horizontal SCEN Assertion Point Register Equalization Pulse Negation Point Register Equalization Interval Negation Point Register. Equalization Interval Assertion Point Register Timing Generator Vertical Counter Timing Generator Horizontal Counter Device Identification Register Monitor Port Data Register Monitor Port Control Register Cursor Control Register Cursor Position Register
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Bt497/498
TABLE CONTENTS
Board Layout Considerations
Power Ground Planes Device Decoupling Power Supply Decoupling. COMP Decoupling VREF Decoupling Digital Signal Interconnect Analog Signal Interconnect. Analog Output Protection
Application Information
Test Features Bt497/8. Signature Analysis Control Register (SAR). Analog Comparator Device Identification Register JTAG Registers. Initializing Bt497/8
Initialization Sequence.
Initialization
Bt497/8-Generated VRAM Shift Clock PLL-Generated Pixel Clock Crystal Frequency Selection. Ratio Selection Deselection
Guide Frame Buffer Interface
Control Signals Typical Usage Latching First Pixels Programming Details
Parametric Information
Electrical Parameters Electrical Parameters Package Information Revision History
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LIST FIGURES
Bt497/498
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Bt497 160-pin PQFP. Bt498 208-pin PQFP. Detailed Functional Block Diagram. Full-Word Read Timing Diagram Clock Generation Block Diagram. CMOS Oscillator Interface Differential Clock Interface Single-Buffered Pixel Format Double-Buffered Pixel Format. Pixel Format 4/2:1 Single-Buffered Pixel Format 4/2:1 Double-Buffered Pixel Format 8/2:1 Pixel Format. Color Model Selection Mechanism Overlay Logic Cursor Address Cursor Position Register Cursor Positioning. Noninterlaced Format Timing Boundaries Horizontal Timing Composite Sync Generation-Noninterlaced Format Noninterlaced Horizontal Timing. Horizontal Timing Waveforms-Interlaced Format. Interlaced Horizontal Timing CSYNC* Signal NTSC Interlaced Timing Monitor Port Control Register Monitor Port Data Register Composite Video Output Waveform (7.5 Setup) Composite Video Output Waveform Setup). Representative Power/Ground Analog Area Layout Typical Analog Connection Diagram. Signature Analysis Feedback Circuit Device Identification Register JTAG Boundry Scan Registers CLOCK XTAL Connections Operation Frame Buffer Interface Bt497/8-Generated VRAM Serial Clock Pixel Clock
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Bt497/498
LIST FIGURES
Figure Latching First Pixels After BLANK Figure Signals Vertical Scale Figure Video Input/Output Timing Figure Figure Figure Figure Figure Figure Figure Figure Port-Read Timing Port-Write Timing Full-Word Read Timing Diagram Input Pixel Timing JTAG Timing Pixel Clock Input (PLL Bypassed) 160-Pin Metric Quad Flatpack (MQFP) 208-Pin Metric Quad Flatpack (MQFP)
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LIST TABLES
Bt497/498
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Assignments 208-pin PQFP Labels 160-pin PQFP Labels Interface Address Map-Control Field Definition Configuration Address Operation. Cursor Address Operation Serial Clock Frequencies. Pixel Port Naming Convention. Color Model Table Data Entry Codes (CMC). Gamma Values. Overlay/Underlay Operation Cursor Color LUT. Internal Timing Generator Signals Noninterlaced CSYNC* Output: HSYNC* VSYNC* Control Video Output Truth Table (7.5 Setup) Video Output Truth Table Setup) Typical Parts List JTAG Registers JTAG Instructions 1280 1024 Noninterlaced Register Values NTSC Register Values. Register Values Pixel Rate Selection. Recommended Operating Conditions Absolute Maximum Ratings Characteristics. Analog Output Timing Clock Generation Timing Parameters Port Timing Serial Clock Timing Pixel Timing. JTAG Timing Input Clock. Package Thermal Resistance
viii
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CIRCUIT DESCRIPTION
Introduction
Bt497 Bt498 software-compatible RAMDACs designed high-performance high-resolution applications. architecture supports 1280 1024 (Bt497) 1600 1280 (Bt498) bit-mapped color-graphics display. on-chip Phase Lock Loop (PLL) provided eliminate high-speed signals Printed Circuit Board (PCB) reduce need multiple, expensive Emitter-Coupled Logic (ECL) crystal oscillators required support multiple monitors refresh rates. uses M/(L scheme program over unique pixel clock frequencies. Bt497/8 allows different display modes operation each pixel. Utilizing window attribute scheme, control bits every pixel used pixel data pre-defined display mode (pseudo color from three color lookup tables, linear true color from three lookup tables, nonlinear true color) create overlay image. control bits Bt497/8 define pixel port source accommodate double-buffered operation animation. 128-pin pixel port supports standard format, well 4/2:1 8/2:1 interleaved format used high-end graphics Video RAMs (VRAMs). Bt497/8 provides on-chip, user-definable, three-color, bit-map cursor programmable timing generator. With timing generator, users achieve full control sync blank characteristics, both interlaced progressive scanned systems, that previous RAMDACs required externally. Video control sent monitor discrete composite sync output green (IOG) analog output. Bt497/8 contains three 8-bit DACs that programmed with pedestal.
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CIRCUIT DESCRIPTION
Descriptions
Bt497/498
Descriptions
Bt497 packaged 160-pin Plastic Quad Flatpack (PQFP), illustrated Figure Bt498 208-pin PQFP shown Figure Table lists descriptions, labels assignments both packages.
Figure Bt497 160-pin PQFP
PA[21] PA[22] PA[23] VAA5 PA[24] PA[25] PA[26] PA[27] PA[28] PA[29] PA[30] PA[31] PA[32] PA[33] PA[34] PA[35] PA[36] PA[37] PA[38] PA[39] VAA5 PA[40] PA[41] PA[42] PA[43]
VAA3 PA[20] PA[19] PA[18] PA[17] PA[16] VAA5 PA[15] PA[14] PA[13] PA[12] PA[11] PA[10] PA[9] PA[8] VAA5 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] TRST* VAA3
Bt497 160-Pin PQFP
VAA3 PA[44] PA[45] PA[46] PA[47] VAA5 PA[48] PA[49] PA[50] PA[51] PA[52] PA[53] PA[54] PA[55] VAA5 PA[56] PA[57] PA[58] PA[59] PA[60] PA[61] PA[62] PA[63] FIELD SCEN* STSCAN MON[0] MON[1] VAA3
VAA5 IOIB VAA5 VREF FSADJ VAA5 COMP COMP2 RANGE VAA5 XTAL[2] XTAL[1] VAA5 CLOCK CLOCK* CSYNC* RESET* D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] MON[3] MON[2]
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Bt497/498
CIRCUIT DESCRIPTION
Descriptions
Figure Bt498 208-pin PQFP
PB[52] PA[21] PB[53] PA[22] PB[54] PA[23] PB[55] VAA5 PA[24] PB[56] PA[25] PB[57] PA[26] PB[58] PA[27] PB[59] PA[28] PB[60] PA[29] PB[61] PA[30] PB[62] PA[31] PB[63] PA[32] PB[0] PA[33] PB[1] PA[34] PB[2] PA[35] PB[3] PA[36] PB[4] PA[37] PB[5] PA[38] PB[6] PA[39] PB[7] VAA5 PA[40] PB[8] PA[41] PB[9] PA[42] PB[10] PA[43]
VAA3 PA[20] PB[51] PA[19] PB[50] PA[18] PB[49] PA[17] PB[48] PA[16] VAA5 PB[47] PA[15] PB[46] PA[14] PB[45] PA[13] PB[44] PA[12] PB[43] PA[11] PB[42] PA[10] PB[41] PA[9] PB[40] PA[8] VAA5 PB[39] PA[7] PB[38] PA[6] PB[37] PA[5] PB[36] PA[4] PB[35] PA[3] PB[34] PA[2] PB[33] PA[1] PB[32] PA[0] TRST*
Bt498 208-Pin PQFP
VAA3 PB[11] PA[44] PB[12] PA[45] PB[13] PA[46] PB[14] PA[47] PB[15] VAA5 PA[48] PB[16] PA[49] PB[17] PA[50] PB[18] PA[51] PB[19] PA[52] PB[20] PA[53] PB[21] PA[54] PB[22] PA[55] PB[23] VAA5 PA[56] PB[24] PA[57] PB[25] PA[58] PB[26] PA[59] PB[27] PA[60] PB[28] PA[61] PB[29] PA[62] PB[30] PA[63] PB[31] FIELD SCEN* STSCAN MON[0] MON[1]
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VAA3 VAA5 VAA5 VAA5 VAA5 VAA5 VREF FSADJ VAA5 COMP COMP2 RANGE VAA5 XTAL[2] XTAL[1] VAA5 CLOCK CLOCK* CSYNC* RESET* C[0] C[1] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] MON[3] MON[2] VAA3
CIRCUIT DESCRIPTION
Descriptions
Bt497/498
Table Assignments Count Signal Name D[7:0] C[1,0] I/O/Z I/O/Z Description Data (LVTTL Compatible). Bidirectional data. port will zero fill unused bits data reads. Control Input (LVTTL Compatible). Read/Write Control Input (LVTTL Compatible). Defines transaction direction. Byte Control (LVTTL Compatible). Chip Enable Control Input (LVTTL Compatible). This input must logical enable data written read from device. During write operations, data internally registered rising edge CE*. Care should taken avoid glitches this edge-triggered input. Pixel Port Inputs (LVTTL Compatible). These inputs have internal pullup resistors that cause logic level high they left unconnected. Bt497 PA[63:0]. Pixel Port Load Clock (LVTTL Compatible). rising edge this signal captures input pixel data. Serial Clock Output (LVTTL Compatible). This signal produced pixel clock divider. meant used clock serial port video memory. Serial Clock Enable Output (LVTTL Compatible). This signal produced timing generator meant control serial port video memory. Horizontal Scan Line Indicator (LVTTL Compatible). This signal produced timing generator meant external circuitry purpose indexing serial port video memory. Field Indicator (LVTTL Compatible). This signal produced timing generator meant external circuitry purpose indexing serial port video memory. Crystal Input. This input either connected crystal driven CMOS oscillator. internal phase lock loop generates pixel clock using this input. Crystal Amplifier Output. This output connected second terminal crystal when used. Clock Inputs. These differential clock inputs designed driven logic configured single supply operation. clock rate typically pixel clock rate system. Voltage Reference Input. external voltage reference circuit must supply this input with 1.235 (typical) reference. resistor network generate reference recommended, low-frequency power supply noise VREF will directly coupled onto analog outputs. ceramic capacitor must used decouple this input VAA5. decoupling capacitor must close possible device keep lead lengths absolute minimum.
P[63:0](A,B)
SCEN*
STSCAN
FIELD
XTAL1
XTAL2 CLOCK, CLOCK*
VREF
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Bt497/498
CIRCUIT DESCRIPTION
Descriptions
Table Assignments Count Signal Name COMP, COMP2 I/O/Z Description Compensation pins. These pins provide compensation internal reference amplifier. ceramic capacitor must connected between these pins. Compensation VCO. 0.01 ceramic chip capacitor tantalum capacitor must connected between this adjacent VAA5. Full-Scale Adjust Control. resistor (RSET) connected between this controls magnitude full-scale video signal. Note that relationships Figures maintained, regardless full-scale output current. relationship between RSET full-scale output current RSET VREF (mA) full-scale output current given RSET IOR, (mA) VREF RSET where defined Setup CSYNC* MON[3:0] RESET* analog current output. Green analog current output. Blue analog current output. Composite Sync Output. Monitor Serial Port Data (LVTTL Compatible). Reset Input (LVTTL Compatible). This reset signal. assertion causes number actions, these described Initializing Bt497/8 Applications Information section. Test Reset (LVTTL compatible). JTAG input asserted power force boundary scan cells their normal, non-JTAG state. transitions this signal reset JTAG state machine. When performing JTAG operations, this should driven logic high. Test Mode Select (LVTTL compatible). JTAG input whose transitions drive JTAG state machine through sequences. When performing JTAG operations, this should driven logic high. Test Clock (LVTTL compatible). Used synchronize JTAG test structures. Maximum clock rate this MHz. When performing JTAG operations, this should driven logic high. 3052 2888 IOR, 2180 2016
RANGE
FSADJ
TRST*
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CIRCUIT DESCRIPTION
Descriptions
Bt497/498
Table Assignments Count Signal Name I/O/Z Description Test Data (LVTTL compatible). JTAG input used loading instructions controller loading test vector data boundary scan operation. When performing JTAG operations, this should driven logic high. Test Data (LVTTL compatible). JTAG output used verifying test results JTAG sampling operations. This active certain JTAG sequences, three-stated other times. When performing JTAG operations, this should left floating. +3.3 Power Supply. VAA3 pins must connected together. +5.0 Power Supply. VAA5 pins must connected together. (Bt497: pins) Ground. (Bt497: pins)
VAA3 VAA5
Note: Input, Output, Three-state.
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Bt497/498
CIRCUIT DESCRIPTION
Descriptions
Table 208-pin PQFP Labels
Label
VAA3 PA[20] PB[51] PA[19] PB[50] PA[18] PB[49] PA[17] PB[48] PA[16] VAA5 PB[47] PA[15] PB[46] PA[14] PB[45] PA[13] PB[44] PA[12] PB[43] PA[11] PB[42] PA[10] PB[41] PA[9] PB[40] PA[8] VAA5 PB[39] PA[7] PB[38] PA[6] PB[37] PA[5] PB[36] PA[4] PB[35] PA[3] PB[34] PA[2]
Label
PB[33] PA[1] PB[32] PA[0] TRST* VAA3 VAA5 VAA5 VAA5 VAA5 VAA5 VREF FSADJ VAA5 COMP COMP2 RANGE VAA5 XTAL[2] XTAL[1] VAA5 CLOCK CLOCK* CSYNC* RESET*
Label
C[0] C[1] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] MON[3] MON[2] VAA3 MON[1] MON[0] STSCAN SCEN* FIELD PB[31] PA[63] PB[30] PA[62] PB[29] PA[61] PB[28] PA[60] PB[27] PA[59] PB[26] PA[58] PB[25] PA[57] PB[24] PA[56]
Label
VAA5 PB[23] PA[55] PB[22] PA[54] PB[21] PA[53] PB[20] PA[52] PB[19] PA[51] PB[18] PA[50] PB[17] PA[49] PB[16] PA[48] VAA5 PB[15] PA[47] PB[14] PA[46] PB[13] PA[45] PB[12] PA[44] PB[11] VAA3 PA[43] PB[10] PA[42] PB[9] PA[41] PB[8] PA[40] VAA5 PB[7] PA[39] PB[6]
Label
PA[38] PB[5] PA[37] PB[4] PA[36] PB[3] PA[35] PB[2] PA[34] PB[1] PA[33] PB[0] PA[32] PB[63] PA[31] PB[62] PA[30] PB[61] PA[29] PB[60] PA[28] PB[59] PA[27] PB[58] PA[26] PB[57] PA[25] PB[56] PA[24] VAA5 PB[55] PA[23] PB[54] PA[22] PB[53] PA[21] PB[52]
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CIRCUIT DESCRIPTION
Descriptions
Bt497/498
Table 160-pin PQFP Labels
Label
VAA3 PA[20] PA[19] PA[18] PA[17] PA[16] VAA5 PA[15] PA[14] PA[13] PA[12] PA[11] PA[10] PA[9] PA[8] VAA5 PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1]
Label
PA[0] TRST* VAA3 VAA5 VAA5 VREF FSADJ VAA5 COMP COMP2 RANGE VAA5 XTAL[2] XTAL[1] VAA5 CLOCK CLOCK* CSYNC* RESET*
Label
C[0] C[1] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] MON[3] MON[2] VAA3 MON[1] MON[0] STSCAN SCEN* FIELD PA[63] PA[62] PA[61] PA[60] PA[59] PA[58] PA[57]
Label
PA[56] VAA5 PA[55] PA[54] PA[53] PA[52] PA[51] PA[50] PA[49] PA[48] VAA5 PA[47] PA[46] PA[45] PA[44] VAA3 PA[43] PA[42] PA[41] PA[40] VAA5
Label
PA[39] PA[38] PA[37] PA[36] PA[35] PA[34] PA[33] PA[32] PA[31] PA[30] PA[29] PA[28] PA[27] PA[26] PA[25] PA[24] VAA5 PA[23] PA[22] PA[21]
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Bt497/498
CIRCUIT DESCRIPTION
Interface
Interface
illustrated Figure Bt497/8 supports standard Microprocessor Unit (MPU) interface, which access internal control registers color palettes. dual-port color palette cursor color registers allow color updating with minimum contention display refresh process. words bits length require four cycles. Words performed modes, direct indirect, that differentiated encoding control bits C[0] C[1], shown Table indirect access requires address pointer that written port; direct access pointer read through port. indirect accesses generate auto-increment function word dimension. signal asserted first cycle indicate least significant byte every access. D[0] corresponds Least Significant (LSB) each byte. Figure illustrates read timing. Table Table illustrate control inputs work conjunction with internal address register specify which configuration cursor function register will accessed MPU. will zero fill reserved bits data reads. Toggling RESET* presets internal registers values shown Table Table
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Figure Detailed Functional Block Diagram
CMC[5] X[7:0] Shadow Transfer Control Logic Overlay/underlay Logic Monitor Serial Port X[7:0] R[7:0] G[7:0] B[7:0] Color Model Selection Pseudo Color Direct Color RAMLUT RAMLUT RAMLUT Gamma Gamma Gamma Linear True Color Diagnostic Registers Control Logic MON[3:0] Nonlinear True Color Cursor Logic Serialization Cursor Cursor Cursor Cursor Color CDATA[1,0] CRSR Select Horizontal Vertical Field Values Clock Synthesizer Pixel Clock Divider Timing Generator Horizontal, Vertical Field Values SYNC BLANK CSYNC*
Interface
CIRCUIT DESCRIPTION
D[7:0] C[1, RESET*
Port Interface Logic Address Pointers Data Registers
Port A[63:0]
Port B[63:0]
Pixel Port Pixel Input Registers Serialization
STSCAN FIELD SCEN* XTAL
Clocks
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Bt497/498
Bt497/498
CIRCUIT DESCRIPTION
Interface
Table Interface Address Map-Control Field Definition Control Field Function Access Type Control Cursor Functions Cursor Address Pointer Configuration Functions Configuration Address Pointer Indirect Direct Indirect Direct Control
Figure Full-Word Read Timing Diagram
C[1,0]
D[7:0]
D[7:0]
D[15:8]
D[23:16]
D[31:24]
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CIRCUIT DESCRIPTION
Interface
Bt497/498
Table Configuration Address Operation Pointer Address $xxxx $0000 $0001-$0FFF $1000 $1001 $1002-$1FFF $2000-$20FF $2100-$30FF $3100-$311F $3120-$313F $3140-$314F $3150 $3151 $3152 $3153-$4FFF $5000 $5001 $5002-$5FFF $6000 $6001 $6002 $6003 $6004 $6005 $6006 $6007 $6008 $6009 $600A $600B $600C $600D C[1,0] Reset Value $1A7 $00XXXXXX Function Configuration Address Pointer Register Control Register Reserved Pixel Format Control Register User Control Register Reserved Color Lookup Table (Red, Green, Blue, Reserved Window Attribute-Shadow Lookup Table Window Attribute-Active Lookup Table Reserved Window Transfer Control Register Overlay Mask Control Register Overlay Color Register Reserved Signature Analysis Control Register Control Register Reserved Timing Generator Control Register Vertical Blank Negation Point Register Vertical Blank Assertion Point Register Vertical Sync. Negation Point Register Vertical Sync. Assertion Point Register Horizontal Serration Negation Point Register Horizontal Blank Negation Point Register Horizontal Blank Assertion Point Register Horizontal Sync. Negation Point Register Horizontal Sync. Assertion Point Register Horizontal SCEN Negation Point Register Horizontal SCEN Assertion Point Register Equalization Pulse Negation Point Register Equalization Interval Negation Point Register
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Bt497/498
CIRCUIT DESCRIPTION
Interface
Table Configuration Address Operation Pointer Address $600E $600F $6010 $6011 $6012-$7FFF $8000 $8001 $8002 $8003-$FFFF C[1,0] Reset Value $A236C1AD Function Equalization Interval Assertion Point Register Timing Generator Vertical Counter Timing Generator Horizontal Counter Timing Generator Test Register Reserved Device Identification Register Monitor Port Data Register Monitor Port Control Register Reserved
Note: Register exists, resettable. Reserved addresses indicate register exists given pointer addresses. User should attempt access reserved addresses.
Table Cursor Address Operation Pointer Address $xxx $000-$07F $080-$0FF $100 $101-$103 $104 $105-$1FF C[1,0] Reset Value Function Cursor Address Pointer Register Cursor RAM-Plane0 Cursor RAM-Plane1 Cursor Control Register Cursor Color Lookup Table (Red, Green, Blue, Cursor Position Register Reserved
Note: Register exists, resettable. Reserved addresses indicate register exists given pointer addresses. User should attempt access reserved addresses.
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CIRCUIT DESCRIPTION Reading/Writing Color Data
Bt497/498
Reading/Writing Color Data
write color data, loads appropriate address pointer with address color palette location cursor color register modified. performs four successive write cycles: red, green, blue, dummy value. During last write cycle, bytes color information concatenated into 24-bit word written location specified address register. address register then auto-increments next location, which modify simply writing another sequence red, green, blue data. read color data, loads address pointer with address color palette location cursor color register read. performs four successive read cycles: red, green, blue, Following last read cycle, address register increments next location, which modify simply reading another sequence color data.
Additional Information
Although color cursor color registers dual ported, pixel data addressing same palette entry being written during write cycle, maximum pixel disturbed. control registers written read time. prevent pixels from being disturbed during writes certain control registers, outputs should disabled through User Control Register. setup times shown Characteristics section minimum required internally capture data. Note that invalid address loaded into address pointer, data written device will ignored invalid data will read MPU. This recommended, could cause problems Bt497/8-compatible products. incomplete access occurs, (less than four cycles between LB*s) that access following full access will ignored.
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Bt497/498
CIRCUIT DESCRIPTION
Clock Generation
Clock Generation
Bt497/8 on-board generating pixel clock, shown Figure pixel clock fully programmable, able generate over unique pixel clock frequencies using single crystal.
Figure Clock Generation Block Diagram
CLOCK CLOCK*
Divider
XTAL1 Crystal 6-25 XTAL2
Pixel Clock M/NxL
Internal RAMDAC Pixel Clock
advanced contains internal loop filter provide maximum noise immunity reduce jitter. Except reference crystal oscillator, external components adjustments necessary. uses M/(L scheme provide precise frequencies. values programmed through command registers with variety values, which generally provide frequency granularity that averages less than MHz. binary 7-bit value, binary 4-bit value, selectable value one, two, four, eight. oscillator reference also used capacitively coupling oscillator's output XTAL1 input, shown Figure this configuration, XTAL2 should left disconnected.
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CIRCUIT DESCRIPTION
Clock Generation
Bt497/498
Figure CMOS Oscillator Interface
1000 CMOS Oscillator XTAL2
Bt497/8
XTAL1
CLOCK
CLOCK*
alternative using pixel clock generation, Bt497/8 designed accept differential clock signals (CLOCK CLOCK* shown Figure These clock inputs generated logic operating Note that CLOCK CLOCK* inputs require termination resistors (220 GND) that should located close driving source possible. chip resistor near Bt497/8 pins also needed ensure proper termination.
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Bt497/498
CIRCUIT DESCRIPTION
Clock Generation
Figure Differential Clock Interface Bt438
CLOCK Ohms
Bt497/8
CLOCK
Ohms
CLOCK* Ohms
CLOCK*
Ohms VREF VREF
serial clock, SC*, generated external clocking VRAM frame buffer loading pixel data. serial clock frequencies either one-half one-fourth pixel clock frequency, depending pixel format selected, shown Table output should buffered inverted then used drive input clock frame buffer. proper operation, delay through buffer should exceed limits specifications.
Table Serial Clock Frequencies Pixel Format 4/2:1 8/2:1 Frequency Fp/2 Fp/4 Fp/2 Fp/4
With assertion RESET*, forced high. When RESET* released, first falling edge will released next edge pixel clock.
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CIRCUIT DESCRIPTION Frame Buffer Interface
Bt497/498
Frame Buffer Interface
Bt497/8 incorporates internal latches multiplexers that enable pixel data transferred from frame buffer VRAM data rates. rising edge color information, consecutive pixels latched into device. additional pixel formats supported, 4/2:1 8/2:1, which consecutive pixels latched load cycles. each case, rates one-half one-fourth pixel clock rates. pixel formats controlled through Pixel Format Control Register shown Figures through shown Table Bt498 pixel port configured into ports, which accommodate double-buffered operation animation. port selection made decoding field each pixel, explained Color Model Selection Window Identification Lookup Table section. Each port divided into bytes, which represents each color, window attribute, overlay, total inputs. Bt497 64-bit pixel port option, port only, packaged 160-pin Plastic Quad Flatpack (PQFP). Because smaller port size, only pixel formats supported 4/2:1. Internal logic maintains internal LOAD signal synchronous pixel clock, guaranteed follow signal least more than three clock cycles. This LOAD signal transfers registered pixel overlay data into second registers, which then internally multiplexed pixel clock rate. Therefore, phase shifted amount relative clock source, pseudo PLL. result, pixel data registered rising edge independent internal external clock phase.
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Bt497/498
CIRCUIT DESCRIPTION
Frame Buffer Interface
Table Pixel Port Naming Convention Pixel Port (Not available Bt497) Device Bits PB[63:56] PB[55:48] PB[47:40] PB[39:32] PB[31:24] PB[23:16] PB[15:8] PB[7:0] PA[63:56] PA[55:48] PA[47:40] PA[39:32] PA[31:24] PA[23:16] PA[15:8] PA[7:0]
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CIRCUIT DESCRIPTION Frame Buffer Interface
Bt497/498
Figure Single-Buffered Pixel Format
Pixel Clock
PA[63:56] PA[55:48] PA[47:40] PA[39:32]
blue1 green1 red1
blue3 green3 red3
blue5 green5 red5
blue7 green7 red7
blue9 green9 red9
blue11 green11 red11
PA[31:24] PA[23:16] PA[15:8] PA[7:0]
blue0 green0 red0
blue green2 red2
blue4 green4 red4
blue6 green6 red6
blue8 green8 red8
blue10 green10 red10
Pixel Numbers Serialized 24-bit Pixels plus Bits
Note: This mode valid pixel clock MHz. frequency Fp/2 MHz.
Brooktree
Bt497/498
CIRCUIT DESCRIPTION
Frame Buffer Interface
Figure Double-Buffered Pixel Format
Pixel Clock
PB[63:56] PB[55:48] PB[47:40] PB[39:32]
Ignore blue1 green1 red1
Ignore blue3 green3 red3
Ignore blue5 green5 red5
PB[31:24] PB[23:16] PB[15:8] PB[7:0]
ignore blue0 green0 red0
ignore blue2 green2 red2
ignore blue4 green4 red4
PA[63:56] PA[55:48] PA[47:40] PA[39:32]
blue1 green1 red1
blue3 green3 red3
blue5 green5 red5
PA[31:24] PA[23:16] PA[15:8] PA[7:0]
blue0 green0 red0
blue2 green2 red2
blue4 green4 red4
Pixel Numbers Serialized 24-bit Pixels plus Bits
Note: This mode valid pixel clock MHz. frequency Fp/2 MHz. valid Bt497.
Brooktree
CIRCUIT DESCRIPTION Frame Buffer Interface
Bt497/498
Figure Pixel Format
Pixel Clock
PB[63:56] PB[55:48] PB[47:40] PB[39:32]
blue3 green3 red3
blue7 green7 red7
blue11 green11 red11
PB[31:24] PB[23:16] PB[15:8] PB[7:0]
blue2 green2 red2
blue6 green6 red6
blue10 green10 red10
PA[63:56] PA[55:48] PA[47:40] PA[39:32]
blue1 green1 red1
blue5 green5 red5
blue9 green9 red9
PA[31:24] PA[23:16] PA[15:8] PA[7:0]
blue0 green0 red0
blue4 green4 red4
blue8 green8 red8
Pixel Numbers Serialized 24-bit Pixels plus Bits
Note: This mode valid pixel clock MHz. frequency Fp/4 MHz. valid Bt497.
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Bt497/498
CIRCUIT DESCRIPTION
Frame Buffer Interface
Figure 4/2:1 Single-Buffered Pixel Format
Pixel Clock
PA[63:56] PA[55:48]
blue3
green3 red3
blue7
green7 red7
blue11
green11 red11
PA[47:40] PA[39:32]
blue2
green2 red2
blue6
green6 red6
blue10
green10 red10
PA[31:24] PA[23:16]
blue1
green1 red1
blue5
green5 red5
blue9
green9 red9
PA[15:8] PA[7:0] Pixel Numbers Serialized 24-bit Pixels plus Bits
blue0
green0 red0
blue4
green4 red4
blue8
green8 red8
Note: This mode valid pixel clock MHz. frequency Fp/2 MHz.
Brooktree
CIRCUIT DESCRIPTION Frame Buffer Interface
Bt497/498
Figure 4/2:1 Double-Buffered Pixel Format
Pixel Clock PORT PB[63:56] PB[55:48] PB[47:40] PB[39:32] PB[31:24] B[23:16] ignore blue3 green3 red3 ignore blue7 green7 red7 ignore blue11 green11 red11
ignore blue2
green2 red2
ignore blue6
green6 red6
ignore blue10
green10 red10
ignore blue1
green1 red1
ignore blue5
green5 red5
ignore blue9
green9 red9
PB[15:8] PB[7:0] PORT PA[63:56] PA[55:48]
ignore blue0
green0 red0
ignore blue4
green4 red4
ignore blue8
green8 red8
blue3
green3 red3
blue7
green7 red7
blue11
green11 red11
PA[47:40] PA[39:32]
blue2
green2 red2
blue6
green6 red6
blue10
green10 red10
PA[31:24] PA[23:16] PA[15:8] PA[7:0] Port Pixels Port Pixels Serialized 24-bit Pixels plus Bits
blue1
green1 red1
blue5
green5 red5
blue9
green9 red9
blue0
green0 red0
blue4
green4 red4
blue8
green8 red8
Note: This mode valid pixel clock MHz. frequency Fp/2 MHz. valid Bt497.
Brooktree
Bt497/498
CIRCUIT DESCRIPTION
Frame Buffer Interface
Figure 8/2:1 Pixel Format
Pixel Clock PORT PB[63:56] PB[55:48] blue7 green7 red7 blue15 green15 red15 blue23 green23 red23
PB[47:40] PB[39:22]
blue6
green6 red6
blue14
green14 red14
blue22
green22 red22
PB[31:24] PB[23:16]
blue5
green5 red5
blue13
green13 red13
blue21
green21 red21
PB[15:8] PB[7:0 PORT PA[63:56] PA[55:48]
blue4
green4 red4
blue12
green12 red12
blue20
green20 red20
blue3
green3 red3
blue11
green11 red11
blue19
green19 red19
PA[47:40] PA[39:32]
blue2
green2 red2
blue10
green10 red10
blue18
green18 red18
PA[31:24] PA[23:16]
blue1
green1 red1
blue9
green9 red9
blue17
green17 red17
PA[15:8] PA[7:0] Pixel Numbers Serialized 24-bit Pixels plus Bits
blue0
green0 red0
blue8
green8 red8
blue16
green16 red16
Note: This mode valid pixel clock MHz. frequency Fp/4 MHz. valid Bt497.
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CIRCUIT DESCRIPTION Color Model Selection Window Identification Lookup Table
Bt497/498
Color Model Selection Window Identification Lookup Table
shown Figure Bt497/8 contains several color model lookup tables that transform pixel data into color information. diagrams describing various pixel formats include data field named contents this field interpreted either Window Identification (WID) address (index) overlay color. WIDs index addresses into Lookup Table (LUT), that serve select pixel source, e.g., port associate pixel with particular color model. field component every pixel content differ contiguous pixels. Therefore, port color model selection performed each individual pixel. pixel formats divided into broad categories: single-buffered format double-buffered format. Bt497 only support 4/2:1 formats running single-buffered. Port available. Bt498 supports formats, including double-buffered modes. 4/2:1 modes, field from Port used field from Port ignored. 8/2:1 field from each pixel used. CMC[5] don't care 8/2:1 formats. field does directly control port color model selection. contents lower bits field (X[4:0]) constitute address active LUT. data, hereafter called WID[5:0], contained locations corresponding these addresses used affect port control color model selection according definitions given Table active accessed from port should initialized during startup procedure. avoid visual artifacts monitor, should accessed during active video, should updated through Shadow LUT.
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X[4:0] WID[5:0] Active X[7:0] CMC[1,0] CMC[4] CMC[5] WID[5:0] Overlay/Underlay Logic CMC[3,
Bt497/498
Figure Color Model Selection Mechanism
Pixel Formatting Logic X[7:0] R[7:0] G[7:0] B[7:0] X[7:0] R[7:0] G[7:0] B[7:0] X[7:0] R[7:0] G[7:0] B[7:0] Color Model Selection RAMLUT RAMLUT RAMLUT Gamma Gamma Gamma Linear Gray Scale Nonlinear
TrueColor
Port A[63:0]
Pseudocolor Direct Color Linear True Color
Port B[63:0]
Pixel Formatting Logic R[7:0] R[07:00] G[7:0] B[7:0] R[7:0] G[7:0] B[7:0]
Nonlinear Gray Scale Cursor Cursor CDATA[1,0] Cursor Cursor Color
CRSR SELECT
CIRCUIT DESCRIPTION Color Model Selection Window Identification Lookup Table
CIRCUIT DESCRIPTION Color Model Selection Window Identification Lookup Table
Bt497/498
Table Color Model Table Data Entry Codes (CMC) [5:0] Selected Input Port Color Model Input Port 24-Bit Nonlinear True Color Input Port 24-Bit Linear True Color Input Port 24-Bit Direct Color Input Port 8-Bit Nonlinear Gray Scale from Channel Input Port 8-Bit Nonlinear Gray Scale from Channel Input Port 8-Bit Nonlinear Gray Scale from Channel Input Port 8-Bit Nonlinear Gray Scale from Channel (8/2:1 only) Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel (8/2:1 only) Input Port 8-Bit Pseudocolor from Channel Input Port 8-Bit Pseudocolor from Channel Input Port 8-Bit Pseudocolor from Channel Input Port 8-Bit Pseudocolor from Channel (8/2:1 only) Input Port 24-Bit Nonlinear True Color Input Port 24-Bit Linear True Color Input Port 24-Bit Direct Color Input Port 8-Bit Nonlinear Gray Scale from Channel Input Port 8-Bit Nonlinear Gray Scale from Channel Input Port 8-Bit Nonlinear Gray Scale from Channel Input Port Nonlinear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Linear Gray Scale from Channel Input Port 8-Bit Pseudocolor from Channel Input Port 8-Bit Pseudocolor from Channel Input Port 8-Bit Pseudocolor from Channel Input Port 8-Bit Pseudocolor from Channel
Notes: (1). CMC[5] should only high 128-bit port option (ignored 8/2:1 input formats). Values defined above table CMC[5:0], should used.
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Bt497/498
CIRCUIT DESCRIPTION
Shadow
Shadow
Bt497/8 contains Shadow that used change contents active asynchronously pixel clock. Shadow accessed port. After been updated Transfer Command Window Transfer Control Register been set, data transferred into active next vertical retrace. Upon completion transfer Bt497/8 resets Transfer Command bit. Window Transfer Control Register's values listed Internal Register section. When Bt497/8 operating interlaced mode, Transfer Event high; making transfer occur only falling edge FIELD signal. Bt497/8 incorporates three LUTs used generate direct pseudocolor information. direct color each addressed independently, while pseudocolor selected address replicated three RAMs. LUTs accessed through port from pixel data routed color model that active selects. Bt497/8 incorporates three LUTs used generate linear gamma-corrected color information. Table lists gamma values that transform nonlinear color values into linear color values. These values accessed pixel data routed color model that active selects. They cannot accessed directly through port, they read using Signature Analysis Register, (SAR) data strobe mode. nonlinear true-color model selected active LUT, input pixel data routed directly DAC. nonlinear gray scale performed replicating input pixel data three DACs. Pipeline stages incorporated match delays other color tables.
Direct Pseudocolor
Linear Color
Nonlinear True Color Nonlinear Gray Scale
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CIRCUIT DESCRIPTION Nonlinear True Color Nonlinear Gray Scale
Bt497/498
Table Gamma Values Address Data Address Data Address Data Address Data
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Bt497/498
CIRCUIT DESCRIPTION Nonlinear True Color Nonlinear Gray Scale
Table Gamma Values Address Data Address Data Address Data Address Data
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CIRCUIT DESCRIPTION Overlay/Underlay Operation
Bt497/498
Overlay/Underlay Operation
noted previously, data field interpreted either index overlay color. Thus, transparent overlays accommodated without incurring expense additional planes frame buffer memory additional LUTs RAMDAC. This accomplished using contain overlay colors circuitry that regulates selection overlay underlay data display. Given that transparent overlay enabled, function explained follows: value current pixel equals transparent Overlay Color Register bits specified Overlay Mask Control Register, then current pixel will processed according window data received from location active LUT. Otherwise, value will used 8-bit pseudocolor pixel. This function appears color model selection diagram Overlay/Underlay Logic block Figure details illustrated Figure principle overlay/underlay operation described Table contents registers, Overlay Mask Control Register Overlay Color Register, define transparent overlay color value. This color value compared value contained X[7:0]. values equal, overlay said transparent underlay (normal processed) color displayed, i.e., multiplexer passes WID[5:0] CMC[5:0]; therefore, color model color source chosen contents index. values equal, overlay color displayed (the multiplexer passes value 0x00 CMC[5:0]) causing color model processing interpret field 8-bit pseudocolor pixel. This implementation defines overlay model 0x00, causing selection 8-bit pseudocolor model, with color data originating field inputs (refer Table Consequently, data contained field serves address color thereby selects overlay color.
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Bt497/498
CIRCUIT DESCRIPTION Overlay/Underlay Operation
Figure Overlay Logic
Overlay Enable
Overlay Color Register
Overlay Mask Control Register
X[7:0]
CMC[5:0]
WID[5:0]
Table Overlay/Underlay Operation Transparent Overlay Enable Overlay Mask X[7:0] Overlay Color Bits CMC[5:0] WID[5:0] (underlay) Determined bits where Mask[n] WID[5:0] (underlay) 000000 (overlay) 000000 (overlay) WID[5:0] (underlay)
Notes: (1). Overlay Mask Control Register bits [7:0] zero, result compare operation corresponding bits X[7:0] Overlay Color [7:0] will ignored. special case where Overlay Mask Control Register bits [7:0] zero, WID[5:0] will used color model control (CMC[5:0]).
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CIRCUIT DESCRIPTION Transparent Overlay Enable Control
Bt497/498
Transparent Overlay Enable Control
Transparent Overlay Enable contained within User Control Register. When transparent overlay control disabled, (set logical data (WID[5:0]) used color model control (i.e., CMC[5:0]). When transparent overlay control enabled, (set logical action multiplexer controlled result equality comparison. This 8-bit register operates contents Overlay Color Register data define extent dimension) color value. Overlay Mask Control Register bits logical allow corresponding bits Overlay Color Register field participate color comparison. Overlay Mask Control Register bits logical preclude corresponding bits Overlay Color Register field from comparison. Register initialization required. This 8-bit register defines color value, subject contents Overlay Mask Control Register. Register initialization required.
Transparent Overlay Mask Register
Transparent Overlay Color Register
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Bt497/498
CIRCUIT DESCRIPTION On-chip Cursor Operation
On-chip Cursor Operation
Bt497/8 on-chip, user-definable, three-color, pixel cursor. pattern cursor provided two-plane cursor which accessed time. Each plane provides cursor information every pixel clock cycle. These bits used select cursor color from LUT, shown Table Each plane also independently enabled disabled using Cursor Control Register. Writing appropriate register bits immediately blocks cursor from appearing, regardless position. This action recommended before doing updates either cursor cursor color LUT, avoid visual artifacts. Then re-enable appropriate planes view completed changes. assertion RESET* disables both planes. cursor accessed through planar format. Each byte write cycle constitutes bits which Most Significant (MSB) becomes leftmost location each load group. most significant byte corresponds leftmost position each address. Plane0 addresses Plane1 addresses within cursor configuration address space. Figure exact mapping between addresses corresponding observed screen.
Table Cursor Color Plane1 Plane0 Color Displayed Transparent Cursor Color Cursor Color Cursor Color $0101 $0102 $0103 Cursor Address
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CIRCUIT DESCRIPTION On-chip Cursor Operation
Bt497/498
Figure Cursor Address
Address Address Address Address Address Address
Plane1 Plane0 Byte Byte Byte Byte Address
Address
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Bt497/498
CIRCUIT DESCRIPTION
Cursor Color
Cursor Color
Cursor color follows same load sequence through color palette (red, green, blue, dummy value) accessed time.
Cursor Positioning
cursor position determined values Cursor Position Register. This 32-bit field contains sign magnitude start position cursor's left corner, shown Figure Bt497/8 contains internal counter that increments pixel going right, from +4031, counter that increments line, going down screen from +4031. When values counter match values Cursor Position Register contents cursor will displayed screen. noninterlaced mode, latest position loaded from register display counters reset zero (the left corner screen) beginning each vertical sync. interlaced mode, position update will take effect until next VSYNC* before even field. Cursor position (0,0) constitutes left corner active video display. This enables users position cursor -64) left side screen -64). Figure assertion RESET* resets cursor display counters, does reset position register. Note that other cursor registers will exhibit immediate effects when they written with values MPU. When Cursor Position Register written, value read back immediately. However, cursor will move screen until appropriate VSYNC* occurrence.
Figure Cursor Position Register
Reserved Reserved
Position Sign Sign
Position
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CIRCUIT DESCRIPTION Cursor Interlace Operation
Bt497/498
Figure Cursor Positioning
VBLANK*
HBLANK*
Cursor Display Area
Cursor Interlace Operation
When Bt497/8 operated interlaced mode, cursor displayed even field format. value Cursor Position Register even number, then first (Row even rows cursor will displayed during even field. rows, starting with will displayed field. position value value, then display sequence reversed; even rows during fields rows during even fields.
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Bt497/498
CIRCUIT DESCRIPTION
Timing Generator
Timing Generator
Bt497/8 on-chip timing generator, operating from serial clock, that provides video display memory timing reference signals interlaced noninterlaced video formats. timing boundaries values Timing Generator Control Register various timing point registers. avoid lockup timing glitches required that pixel clock freely running whenever changes made Timing Generator Registers. System Reset When asserted, system reset signal (RESET*) following effects. registered function named Video Enable forced video disabled state assertion RESET*. This condition persists after negation RESET* until overwritten port. Video Enable, when disabled state, asserts composite blanking within RAMDAC that video monitor remains black while timing generator being programmed. When asserted, RESET* forces Timing Generator Horizontal Vertical Counters zero value. Timing Generator Enable forced disabled state assertion RESET*. This condition persists after negation RESET* until overwritten port. purpose hold timing generator known state while being programmed. When asserted, RESET* causes timing generator slave mode. this case, FIELD signal placed high-impedance mode. enable user observe timing generator operation, several internal timing signals output onto accessing Timing Generator Test Register ($6011). This accomplished loading register value address pointer setting port into read mode. When enabled (low) signals listed Table will output onto port. When disabled (high) port will return normal operation. Three additional cycles still required increment next address.
Timing Generator Test Features
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CIRCUIT DESCRIPTION Timing Generator Display Formats
Bt497/498
Table Internal Timing Generator Signals Output D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Internal Signal HSYNC* SERRATION* EQUALIZATION CBLANK CSYNC* VSYNC* VBLANK* HBLANK* Description Internal Horizontal Sync Internal Serration Pulses Internal Equalization Pulses Internal Composite Blank Internal Composite Sync Internal Vertical Sync Internal Vertical Blank Internal Horizontal Blank
Timing Generator Display Formats
timing generator controlled programming appropriate values into Timing Generator Control Register. Both interlaced noninterlaced modes operation supported. horizontal register values units serial clock rate. vertical register values units horizontal lines. origin timing coordinates serial clock period immediately following start vertical sync. This means that line first line vertical sync, horizontal unit first serial clock period immediately following start horizontal sync. values load into registers less than desired timing point. Neither horizontal vertical registers programmed have value zero. When operated pixel formats 4/2:1 8/2:1, horizontal active interval, represented Horizontal Blank Negation Point Horizontal Blank Assertion Point registers, should programmed with even value. programming these registers described Internal Registers section. video display timing information sent monitor inserting blank sync information onto outputs, Timing Generator Control Register. sync information also sent digital composite sync signal (CSYNC*). noninterlaced mode CSYNC* contains horizontal vertical, optionally serrated sync information. interlaced mode horizontal equalization information also included.
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Bt497/498
CIRCUIT DESCRIPTION
Output Signals
Output Signals
Bt497/498 provides following timing generator outputs: SC*, SCEN*, STSCAN, FIELD, CSYNC*. composite signal waveform previously described; timing CSYNC* output consistent with analog outputs nearest period. FIELD signal, when master mode, transitions with leading edge internal VSYNC*. Additionally, level used output current field when interlaced mode (logical even field, logical field). noninterlaced mode, transitional edges this signal will still occur near leading edge every VSYNC*; however, level FIELD signal meaning. Externally, signal used differentiate between left right views stereo display. STSCAN output internally generated signal that used memory controller determine proper transfer address timing VRAM frame buffer serial port. logic will STSCAN signal rising edge SCEN* next line visible reset STSCAN falling edge SCEN*. SCEN* output used enabling clocking serial data from VRAMs. assertion SCEN* controlled programming timing generator registers Vertical Blank Negation Point (VBNP), Vertical Blank Assertion Point (VBAP), Horizontal Serial Clock Enable Assertion Point (HSCENAP), Horizontal Serial Clock Enable Negation Point (HSCENNP).
FIELD Output
STSCAN Output
SCEN* Output
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CIRCUIT DESCRIPTION Noninterlaced Timing
Bt497/498
Noninterlaced Timing
noninterlaced timing points illustrated Figure Timing diagrams shown Figures Register values represent period line before event occurrence should programed value less than desired time point. example 1280 1024 display given Applications Information section. timing points defined groupings: horizontal vertical.
Figure Noninterlaced Format Timing Boundaries
HSNP HBNP HSERNP HBAP HSAP
VSNP VBNP
Active Display
VBAP
VSAP
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Bt497/498
CIRCUIT DESCRIPTION
Noninterlaced Timing
Horizontal Timing Generation
generating horizontal serrated sync signals, Horizontal Sync Assertion Point (HSAP), Horizontal Sync Negation Point (HSNP), Horizontal Serration Negation Point (HSERNP) registers programmed with desired durations clock units. parameters should programmed less than desired duration. operation described follows: Timing Generator Horizontal Counter begins value zero, with HSYNC* SERRATION* waveforms active (i.e., low). When counter reaches HSNP value, HSYNC* deasserted next serial clock. Timing Generator Horizontal Counter continues counting until programmed HSERNP value reached, which point SERRATION* waveform deasserted next serial clock. Timing Generator Horizontal Counter continues until HSAP value reached, after which Timing Generator Horizontal Counter will restarted zero next serial clock. Timing diagrams generation composite sync shown Figure diagram illustrating relative register values related active screen area shown Figure generation horizontal blanking signal relatively straightforward; HBLANK* asserted next serial clock after Timing Generator Horizontal Counter reaches value programmed Horizontal Blank Assertion Point Register (HBAP). HBLANK* then deasserted next serial clock after Timing Generator Horizontal Counter reaches value programmed Horizontal Blank Negation Point Register (HBNP). horizontal timing register values should satisfy following relationships:
HSNP HSERNP HSAP HSNP HBNP HBAP HSAP
HSNP HBNP HBAP HSAP
Endpoint Hsync start Horizontal Back Porch. Endpoint HBLANK* start active video. Endpoint active video start HBLANK*. Endpoint Horizontal Front Porch start Hsync. HSAP represents total number serial clock periods line. HSCENNP last serial clock period that SCEN* will active. HSCENAP SCEN* active next serial clock period. HSCENAP should less than HBNP exactly number serial clocks that takes pixel data clocked Bt497/8 input. HBNP-HSCENAP should always equal HBAP-HSCENNP. HSERNP last serial clock period horizontal sync during vertical sync interval.
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CIRCUIT DESCRIPTION Noninterlaced Timing
Bt497/498
Figure Horizontal Timing Composite Sync Generation-Noninterlaced Format
HSYNC*
SERRATION*
VSYNC*
CSYNC*
HSAP HSNP
HSERNP
Figure Noninterlaced Horizontal Timing
Active Video
HBNP HBAP HSNP HSAP
CSYNC*
HSCENNP HSCENAP
SCEN* STSCAN
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Bt497/498
CIRCUIT DESCRIPTION
Noninterlaced Timing
Vertical Timing Generation
VSYNC* vertical timing signal generated using values contained Vertical Sync Negation Point (VSNP) Vertical Sync Assertion Point (VSAP) registers. VBLANK* vertical timing signal generated using values contained Vertical Blank Assertion Point (VBAP) Vertical Blank Negation Point (VBNP) registers. noninterlaced mode, vertical timing register intervals specified units horizontal lines (i.e., load period HSAP). vertical timing counter incremented each horizontal sync assertion time; subsequently, only time that vertical timing signals transition HSYNC* assertion. vertical timing registers should programmed satisfy following relationship:
VSNP VBNP VBAP VSAP
composite blank signal derived logically OR'ing internal HBLANK* with VBLANK*. VSNP VBNP Endpoint Vsync start Vertical Back Porch. VSNP represents number lines during vertical sync period. Endpoint VBLANK* start active video. register values represent number blanked lines above active video display plus lines Vertical Sync Video blanked starting next line. Endpoint VBLANK* start Vsync. VSAP represents total number lines frame. Timing Generator Vertical Counter reset zero after Vertical Sync asserted.
VBAP VSAP
Composite Sync
composite sync signal combines Hsync with serration pulses during vertical sync interval onto discrete output. components CSYNC* output enabled disabled using Timing Generator Control Register, shown Table Note that characteristics CSYNC* defined Table also exhibited analog output SYNC component timing.
Table Noninterlaced CSYNC* Output: HSYNC* VSYNC* Control Timing Control Register CSYNC* Output HSYNC* (Bit Enabled Enabled Disabled Disabled VSYNC* (Bit Enabled Disabled Enabled Disabled Normal operation CSYNC* looks like HSYNC* serrations) CSYNC* looks like VSYNC* serrations) CSYNC* inactive (high level)
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CIRCUIT DESCRIPTION Interlaced Timing
Bt497/498
Interlaced Timing
nature composite sync video signals during equalization vertical sync intervals, interlace mode timing events based half-line intervals. accomplish this timing generator clocks horizontal vertical counters twice scan line. first starts external horizontal sync interval. second occurs half-way point scan line used mainly trigger consecutive serration equalization pulses during vertical sync. Timing Registers described this section Internal Register section. register values represent period half-line before event occurrence should programmed value less than desired time point. Note that since counters clocked twice scan line, values registers half value programmed noninterlaced mode. Examples timing values NTSC included Application Information section. timing points defined into groupings, Horizontal Vertical. Horizontal Vertical Sync signals independently disabled during interlaced operation. Disabling either Sync signals, bits Timing Control Register, will result both Horizontal Vertical Sync being disabled. Note that this limitation does exist during noninterlaced operation. relationships between programmed register values waveforms shown Figures additional horizontal time point required interlaced mode. EQNP Equalization Negation Point (EQNP) value programmed control register that represents equalizing pulse width (minus SC*) normally programmed half HSYNC* width. equalize pulses only occur during pre- post-equalization intervals shown Figure start horizontal timing determined field displayed. field even, starts even half-line; odd, starts half-line shown Figure state field reflected FIELD pin, which changes onset Vertical Sync. During Even Field, FIELD low; during field, FIELD high. SCEN* STSCAN signals extend over half-line boundaries follow same behavior noninterlaced mode.
Horizontal Timing Generation
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Bt497/498
CIRCUIT DESCRIPTION
Interlaced Timing
Figure Horizontal Timing Waveforms-Interlaced Format
EQNP
EQUALIZE*
HSNP HSYNC*
HSAP
HSERNP SERRATION*
HBLANK*
HBNP Vertical Counter
HBAP Vertical Counter
Figure Interlaced Horizontal Timing CSYNC* Signal
HSYNC* Internal
Half Line
Half Line
Half Line
Half Line
HBNP
HBAP
Active Video
Active Video
CSYNC* Even Field
CSYNC* Field
EQNP HSAP
Full Scan Line
HSNP
Vertical Sync.
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CIRCUIT DESCRIPTION Interlaced Timing
Field Even Field
VBLANK*
EQUALIZATION Interval
VSYNC* (Serration Interval)
SERRATION*
Figure NTSC Interlaced Timing
Half-Line Number
EQUALIZE*
HSYNC*
CSYNC*
Even Field Field
VBLANK*
EQUALIZATION Interval
VSYNC*
EIAP
Pre-Equalization
Post-Equalization
EINP
SERRATION*
Half Line Number
EQUALIZE*
HSYNC*
CSYNC*
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Bt497/498
Bt497/498
CIRCUIT DESCRIPTION
Interlaced Timing
Vertical Timing Generation
Interlaced display Bt497/8 adopts convention displaying first line active video, corresponding first line frame buffer even field; frame buffer displayed field. This allows Bt497/8 properly order cursor scan line. keep this convention, VBNP must programmed with value ensure that beginning horizontal events happened even cycle. VBAP programmed even value depending number lines frame buffer. value VSAP register represents total number half-lines while value VSNP reflects number half-lines serration during vertical sync. additional timing parameters, shown Figure required interlaced operation. EINP Equalization Interval Negation Point (EINP) indicates last half-line following vertical sync which generate equalization pulse. value this register VSNP register determine number equalization pulses post-equalization interval. Equalization Interval Assertion Point (EIAP) corresponds first equalization pulse before vertical sync. value this register VSAP register determine number equalization pulses pre-equalization interval. vertical timing registers should satisfy following relationship:
VSNP EINP VBNP VBAP EIAP VSAP
EIAP
Composite Sync Generation
composite sync signal combines HSYNC* with serration equalization pulses discrete output. start HSYNC* component depends field displayed. even field starts first even half-line after VSYNC* interval; field will start first half-line. interlaced mode, HSYNC* VSYNC* registers should match. they enabled, CSYNC* will operate normally; they disabled, CSYNC* will output logic When Timing Generator Control Register programmed slave mode, timing generator accepts FIELD signal input. this mode, transition occurring this input will cause Timing Generator Vertical Counter reset subsequent horizontal sync occurrence. Bt497/8 interlaced mode, level that FIELD input transitions will determine which field current (i.e., high-to-low transition causes timing generator start even field next HSYNC* leading edge). Since Timing Generator Horizontal Counters reset, clock drift will eventually cause vertical sync slave line longer, blanked front porch line shorter.
Slave Mode Operation
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CIRCUIT DESCRIPTION Monitor Identification Control Interface
Bt497/498
Monitor Identification Control Interface
Bt497/8 incorporates separate 4-bit registers hardware portion software driven, synchronous, half-duplex, serial interface. This interface provides means reading video monitor identification codes controlling certain monitor functions from host system. host system communicates with interface registers port. important note that interface control circuitry required. serial monitor features will active during active video. These features could accessed during blanking. Monitor Port Control Register, shown Figure configures individual monitor pins, MON[3:0], inputs outputs. MC[3]-MC[0] bits pins output; pins considered inputs. configured output, Monitor Port Data Register value will drive MON[3:0] pins. configured input, will latch data pins store Monitor Port Data Register (Figure 26).
Figure Monitor Port Control Register
Figure Monitor Port Data Register
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Bt497/498
CIRCUIT DESCRIPTION
Video Generation
Video Generation
Every clock cycle, selected color information from color model cursor presented converters. Sync blank information adds appropriately weighted currents analog outputs, producing specific output levels required video applications, illustrated Figure Figure varying output current from each converters produces corresponding voltage level, which used drive color monitor. Note that only green output (IOG) contain sync information. Table Table detail sync blank information from timing generator modifies output levels. converters Bt497/8 segmented architecture which currents routed either current output sophisticated decoding scheme. This architecture eliminates need precision component ratios greatly reduces switching transients associated with turning current sources off. Monotonicity glitch guaranteed using identical current sources current steering their outputs. on-chip operational amplifier stabilizes converter's full-scale output current against temperature power supply variations.
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CIRCUIT DESCRIPTION Video Generation
Bt497/498
Figure Composite Video Output Waveform (7.5 Setup)
RED, BLUE GREEN
19.05 0.714 26.67 1.000
White Level
92.5
1.44 0.00
0.054 9.05 0.000 7.62
0.340 0.286
Black Level Blank Level
0.00
0.000
Sync Level
Table Video Output Truth Table (7.5 Setup) Analog Level White Data Data-Sync Black Black-Sync Blank Sync (mA) 26.67 Data 9.05 Data 1.44 9.05 1.44 7.62 (mA) (mA) 19.05 Data 1.44 Data 1.44 1.44 1.44 VSYNC* HSYNC* Disabled Disabled Enabled Disabled Enabled Disabled Enabled VBLANK* HBLANK* Disabled Disabled Disabled Disabled Disabled Enabled Enabled Input Data Data Data
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Bt497/498
CIRCUIT DESCRIPTION
Video Generation
Figure Composite Video Output Waveform Setup)
RED, BLUE GREEN
17.62 0.660 25.24 0.95
White Level
0.00
0.000 7.62
0.286
Black/Blank Level
0.00
0.000 0.00
0.000
Sync Level
Table Video Output Truth Table Setup) Analog Level White Data Data-Sync Black Black-Sync Blank Sync (mA) 25.24 Data 7.62 Data 7.62 7.62 (mA) (mA) 17.62 Data Data VSYNC* HSYNC* Disabled Disabled Enabled Disabled Enabled Disabled Enabled VBLANK* HBLANK* Disabled Disabled Disabled Disabled Disabled Enabled Enabled Input Data Data Data
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INTERNAL REGISTERS
This section details Bt497/498 internal registers. user should access reserved address locations. Furthermore, user needs aware reserved bits when accessing internal registers interface. Reserved bits nothing they written most give zero value when their register read out. However, ensure compatibility with future Bt497/498 code-compatible products, recommended that reserved bits maintained with read-modify-write access, which only updates unreserved bits. Also, some registers, unreserved bits resettable, reserved bits have reset value zero.
NOTE: Read Only, Resettable, Readable Writable.
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INTERNAL REGISTERS
Control Register
Bt497/498
Control Register (C[1,0] Address $0000)
Bit(s) 31-15 Reserved Enable Disable Enable Field Read /Write Reset Value Description Reserved. Returns zeros when read. enable control. logical enables pixel clock source, using crystal connected XTAL1 XTAL2 inputs reference. logical disables PLL. CLOCK CLOCK* would then directly used internal pixel clock. Post frequency divider.
13-11
(000) (001) (010) (011) (100) (111) Divide Divide Divide Divide Reserved Reserved
10-7
($0) ($2) ($3) ($4) ($5) ($A) ($B) ($C) ($D) ($F) ($00) ($1F) ($20) ($21) ($4F) ($50) ($51) ($7F)
Reserved Reserved Reserved Divide Divide Divide Divide Divide Reserved Reserved Reserved Reserved Multiply Multiply Multiply Multiply Reserved Reserved
divisor.
multiplicand.
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Bt497/498
INTERNAL REGISTERS Pixel Format Control Register
Pixel Format Control Register (C[1,0] Address $1000)
Bit(s) 31-2 Reserved Pixel Format Control Field Read Write Reset Value Description Reserved. Returns zeros when read. Selects pixel interleaving format. frequency each multiplex rate would follows: Fp/2 Fp/4 Fp/2 Fp/4
(00) (01) (10) (11)
4/2:1 8/2:1
User Control Register (C[1,0] Address $1001)
Bit(s) 31-12 11-8 Reserved Reserved Reserved Overlay Enable Disabled Enabled Field Read/ Write Reset Value Description Reserved. Returns zeros when read. Internal Brooktree test register. data this field should ignored. Returns zeros when read. When logical overlay enabled state, bits field compared with bits Overlay Color Register specified Overlay Mask Control Register. they equal, background pixel displayed. they equal, field used 8-bit pseudocolor pixel. This field valid only when 4/2:1 pixel format. Other formats require that this zero. Allows user force blank screen. Asserting this also disables SCEN* STSCAN outputs. Disables input pullup resistors pixel JTAG pins. Should enabled during normal operation.
Double-Buffer Enable Single Buffered Double Buffered Asynchronous Blank Normal Operation BLANK constant Input Pullup Disable Enabled Disabled
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INTERNAL REGISTERS
Window Transfer Control Register
Bt497/498
Window Transfer Control Register (C[1,0] Address $3150)
Bit(s) 31-3 Reserved Transfer Event Next Frame Next Field Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This controls actual occurrence transfer, Transfer Command set. this then transfer will occur transition field signal this transfer occurs falling edge field signal Directs RAMDAC hardware execute transfer operation immediately upon, before, arrival transfer event interval. This software cleared either events: RAMDAC hardware when transfer operation been completed; software, indicating command been withdrawn. This controlled Bt497/8 indicates when transfer underway.
Transfer Command Transfer Action
Device Status Busy, Table Unavailable Idle, Table Available
Overlay Mask Control Register (C[1,0] Address $3151)
Bit(s) 31-8 Reserved Overlay Mask Deselect Select Field Read/ Write Reset Value Description Reserved. Returns zeros when read. When this field logical selects Overlay Color Register compared with bits field.
Overlay Color Register (C[1,0] Address $3152)
Bit(s) 31-8 Reserved Overlay Color Field Read Write Reset Value Description Reserved. Returns zeros when read. bits this field that selected Overlay Mask Control Register compared bits field. they equal, background pixel displayed. they equal field used overlay 8-bit pseudocolor pixel.
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Bt497/498
INTERNAL REGISTERS Signature Analysis Control Register
Signature Analysis Control Register (C[1,0] Address $5000)
Bit(s) 31-28 Reserved Data Strobe Mode Signature Analysis Mode Data Strobe Mode Signature Analysis Busy Idle Busy Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This determines method high-speed test used. Signature analysis registers used hold test results both test methods. Status signature analysis logic. logical indicates that signature analysis completed previous signature acquisition. logical indicates that requested signature acquisition been requested, completed. Writing causes signature analysis logic become busy requests that signature analysis logic capture signature. data written into bits through will used seed signature acquisition frame. Writing zero cancels previously requested signature acquisition. Seed value test result dummy bit. Seed value test result blue DAC. Seed value test result green DAC. Seed value test result DAC.
Signature Capture Request Cancel Signature Request Request Signature Capture
23-16 15-8
Signature Analysis Seed/ Result Dummy Signature Analysis Seed/ Result Blue Signature Analysis Seed/ Result Green Signature Analysis Seed/ Result
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INTERNAL REGISTERS
Control Register
Bt497/498
Control Register (C[1,0] Address $5001)
Bit(s) 31-7 Reserved Pedestal Enable pedestal pedestal SYNC Green Enable Disabled Enabled Comparator Result Operand Operand Operand Operand Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This specifies whether blanking pedestal generated video outputs. specifies that black blank levels same. This specifies whether sync information output onto IOG. effect CSYNC* pin. This yields result comparison and/or reference output. Comparing operands whose values within LSBs will yield unpredictable results. Data written this ignored, read only. result valid only after required comparison setting time reached (i.e., after operand becomes constant). This field selects Operand comparator. normal operation, operand fields should both contain
Operand Select (00) Normal Operation (01) Select Green Output (10) Select Output (11) Reserved Operand Select (00) Normal Operation (01) Select Reference (10) Select Blue Output (11) Reserved
This field selects Operand comparator. normal operation, operand fields should both contain
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Bt497/498
INTERNAL REGISTERS Timing Generator Control Register
Timing Generator Control Register (C[1,0] Address $6000)
Bit(s) 31-7 Reserved Interlaced Mode Noninterlaced Mode Interlaced Mode Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This selects timing generators mode operation. Reset writing zero causes timing generator operate noninterlaced mode. logical causes timing generator operate interlaced mode. This controls FIELD signal direction. Reset writing zero this causes timing generator slave mode, forcing bidirectional FIELD signal input (provided master timing generator). Writing causes timing generator master mode, forcing FIELD signal output. chip interlaced mode, reset writing zero this enables equalization pulses CSYNC*. Otherwise, CSYNC* should look like noninterlaced case. Horizontal syncs occur CSYNC* except during vertical sync; during vertical sync CSYNC* serration pulses. Reset writing zero this causes vertical sync enabled CSYNC* signal. Disabling VSYNC* during interlaced operation also disables HSYNC*. Reset writing zero this causes horizontal sync enabled CSYNC* signal. Disabling HSYNC* during interlaced operation also disables VSYNC*. Upon reset writing zero this bit, both Timing Generator Horizontal Vertical Counters disabled reset zero. Writing enables both Timing Generator Horizontal Vertical Counters. Reset writing zero this causes outputs blanked, disables SCEN* STSCAN outputs. Writing one, enables three signals. signature acquired during video disable state will have data equal zero.
Master Mode Slave Master
Equalization Disable Equalize Enabled Equalize Disabled
Vertical Sync Disable VSYNC* Enabled VSYNC* Disabled Horizontal Sync Disable HSYNC* Enabled HSYNC* Disabled Timing Generator Enable Disabled Enabled
Video Enable Disabled Enabled
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INTERNAL REGISTERS Vertical Blank Negation Point Register
Bt497/498
Vertical Blank Negation Point Register (C[1,0] Address $6001)
Bit(s) 31-12 11-0 Reserved VBNP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Vertical Counter that corresponds vertical blank interval. next vertical count [VBNP+1] will trigger first line active video. Programmed value should greater than zero.
Vertical Blank Assertion Point Register (C[1,0] Address $6002)
Bit(s) 31-12 11-0 Reserved VBAP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Vertical Counter that corresponds last line active video. next vertical count [VBAP+1] will trigger beginning vertical blank interval. Programmed value should greater than zero.
Vertical Sync. Negation Point Register (C[1,0] Address $6003)
Bit(s) 31-12 11-0 Reserved VSNP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Vertical Counter that corresponds last line vertical sync interval. Programmed value should greater than zero.
Vertical Sync. Assertion Point Register (C[1,0] Address $6004)
Bit(s) 31-12 11-0 Reserved VSAP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Vertical Counter that corresponds line before beginning vertical sync. Timing Generator Vertical Counter will zero next line. VSAP+1 total number lines. Programmed value should greater than zero.
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Bt497/498
INTERNAL REGISTERS Horizontal Serration Negation Point Register
Horizontal Serration Negation Point Register (C[1,0] Address $6005)
Bit(s) 31-12 11-0 Reserved HSERNP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that represents duration serial clock periods serration pulses CSYNC* during vertical sync interval.
Horizontal Blank Negation Point Register (C[1,0] Address $6006)
Bit(s) 31-12 11-0 Reserved HBNP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that corresponds last serial clock period blanking before active video line. Programmed value should greater than zero
Horizontal Blank Assertion Point Register (C[1,0] Address $6007)
Bit(s) 31-12 11-0 Reserved HBAP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that corresponds last serial clock period active video. Horizontal blanking starts with next serial clock period. Programmed value should greater than zero.
Horizontal Sync. Negation Point Register (C[1,0] Address $6008)
Bit(s) 31-12 11-0 Reserved HSNP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that corresponds last serial clock period horizontal sync. Programmed value should greater than zero.
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INTERNAL REGISTERS
Horizontal Sync. Assertion Point Register
Bt497/498
Horizontal Sync. Assertion Point Register (C[1,0] Address $6009)
Bit(s) 31-12 11-0 Reserved HSAP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that corresponds last serial clock period line. HSAP+1 total number serial clock periods line. Timing Generator Horizontal Counter will zero next serial clock period. Programmed value should greater than zero.
Horizontal SCEN Negation Point Register (C[1,0] Address $600A)
Bit(s) 31-12 11-0 Reserved HSCENNP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that corresponds last serial clock period that SCEN* will active. Programmed value should greater than zero.
Horizontal SCEN Assertion Point Register (C[1,0] Address $600B)
Bit(s) 31-12 11-0 Reserved HSCENAP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Horizontal Counter that corresponds start SCEN*. SCEN* active next serial clock period. HSCENAP should less than HBNP exactly number serial clocks that takes pixel data clocked Bt497/8 inputs. HBNP HSCENAP should always equal (HBAP HSCENNP). Programmed value should greater than zero.
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Bt497/498
INTERNAL REGISTERS Equalization Pulse Negation Point Register
Equalization Pulse Negation Point Register (C[1,0] Address $600C) Bit(s)
31-12 11-0 Reserved EQNP
Field
Read/ Write
Reset Value
Description
Reserved. Returns zeros when read.
This field represents value Timing Generator Horizontal Counter that corresponds last serial clock period equalization pulse. Equalization pulses always begin horizontal coordinate Equalization pulses generally one-half duration horizontal sync. Programmed value should greater than zero.
Equalization Interval Negation Point Register (C[1,0] Address $600D)
Bit(s) 31-12 11-0 Reserved EINP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Vertical Counter that corresponds last half-line following vertical sync which generate equalization pulse. Programmed value should greater than zero.
Equalization Interval Assertion Point Register (C[1,0] Address $600E)
Bit(s) 31-12 11-0 Reserved EIAP Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This field represents value Timing Generator Vertical Counter that corresponds half-line before beginning pre-equalization interval. first equalization pulse before vertical sync will occur next half-line. Programmed value should greater than zero.
Timing Generator Vertical Counter (C[1,0] Address $600F)
Bit(s) 31-12 11-0 Reserved Vertical Line Counter Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This read-only field gives real-time value Timing Generator Vertical Counter time read MPU.
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INTERNAL REGISTERS
Timing Generator Horizontal Counter
Bt497/498
Timing Generator Horizontal Counter (C[1,0] Address $6010)
Bit(s) 31-12 11-0 Reserved Horizontal Serial Clock Counter Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This read-only field gives real-time value Timing Generator Horizontal Counter time read MPU.
Device Identification Register (C[1,0] Address $8000)
Bit(s) 28-31 Field Device Revision Read/ Write Reset Value Description Manufacturer Marketing Revision. value stored this field read through JTAG Access Port Port. Manufacturer Part Number. value stored this field read through JTAG Access Port Port. Manufacturer Identification Number. value stored this field read through JTAG Access Port Port. Final value register $A236C1AD
27-12
Device Part Number
$236C
11-1
Device Manufacturer $0D6
$0D6
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Bt497/498
INTERNAL REGISTERS Monitor Port Data Register
Monitor Port Data Register (C[1,0] Address $8001)
Bit(s) 31-4 Reserved MON[3] Data Field Read/ Write Reset Value Description Reserved. Returns zeros when read. configured output, MON[3] will continuously drive depending value this bit. configured input, level MON[3] captured first falling edge during read cycle. configured output, MON[2] will continuously drive depending value this bit. configured input, level MON[2] captured first falling edge during read cycle. configured output, MON[1] will continuously drive depending value this bit. configured input, level MON[1] captured first falling edge during read cycle. configured output, MON[0] will continuously drive depending value this bit. configured input, level MON[0] captured first falling edge during read cycle.
MON[2] Data
MON[1] Data
MON[0] Data
Monitor Port Control Register (C[1,0] Address $8002)
Bit(s) 31-4 Reserved Input Output Input Output Input Output Input Output Field Read/ Write Reset Value Description Reserved. Returns zeros when read. MON3 configuration. MON2 configuration. MON1 configuration. MON0 configuration.
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INTERNAL REGISTERS
Cursor Control Register
Bt497/498
Cursor Control Register (C[1,0] Address $100)
Bit(s) 31-2 Reserved Cursor Plane1 Display Enable Enabled Disabled Cursor Plane0 Display Enable Enabled Disabled Field Read/ Write Reset Value Description Reserved. Returns zeros when read. This specifies whether Plane1 cursor displayed.
This specifies whether Plane0 cursor displayed.
Cursor Position Register (C[1,0] Address $104)
Bit(s) 30-28 27-16 14-12 11-0 Field Positive Negative Read/ Write Reset Value Description Sign position cursor. Returns zeros when read. cursor position, number lines, cursor. Values from $0000 $0FFF written. Sign position cursor. Reserved. Returns zeros when read. cursor position, number pixels, cursor. Values from $0000 $0FFF written.
Reserved Position Positive Negative
Reserved Position
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BOARD LAYOUT CONSIDERATIONS
Optimize Bt497/8 layout lowest noise power ground lines shielding digital inputs providing good decoupling. trace length between groups pins should short possible minimize inductive ringing. This layout enables Bt497/8 located close power supply connector video output connector possible. well-designed power distribution network critical eliminating digital switching noise. ground planes must provide low-impedance return path digital circuits. board with minimum layers recommended. ground layer shield isolate noise from analog traces with layer (top), analog traces; layer ground plane (preferable analog ground plane); layer analog power plane. remaining layers digital traces digital power supplies. Power Ground Planes power ground planes need isolation gaps least 1/8-inch wide minimize digital switching noise effects analog signals components. Gaps placed that digital currents cannot flow through peninsula that contains analog components, signals, video connector sample layout shown Figure 29). necessary have separate planes VAA3 VAA5. VAA3 plane should cover digital signal line terminations Bt497/8 with occasional openings VAA5 access.
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BOARD LAYOUT CONSIDERATIONS
Power Ground Planes
Bt497/498
Figure Representative Power/Ground Analog Area Layout
Digital Area
Bt497/8
Analog Area
Video Connector Board Edge
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Bt497/498
BOARD LAYOUT CONSIDERATIONS
Device Decoupling
Device Decoupling
optimum performance, capacitors should located close device possible, using shortest leads possible (consistent with reliable operation) reduce lead inductance. Chip capacitors recommended lead inductance. Radial lead ceramic capacitors substituted chip capacitors better than axial lead capacitors self-resonance. Values chosen have self-resonance above pixel clock. Best power supply decoupling performance obtained providing ceramic capacitor parallel with 0.01 chip capacitor decouple each group VAA3 VAA5 pins GND. capacitors should placed close possible device pins. capacitor shown Figure Table low-frequency power supply ripple; 0.01 capacitors high-frequency power supply noise rejection. decoupling capacitors should connected VAA3, VAA5, pins, using short, wide traces. When using linear regulator, power-up sequence must verified prevent latchup. linear regulator recommended filter analog power supply power supply noise greater than This especially important when switching power supply used switching frequency close raster scan frequency. Note that about percent power supply ripple noise less than will couple onto analog outputs.
Power Supply Decoupling
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BOARD LAYOUT CONSIDERATIONS
Power Supply Decoupling
Bt497/498
Figure Typical Analog Connection Diagram
C17, Bt497/8 VAA3 Locate close possible Bt497/8 C15,
VAA5 Bt498 Bt497 RANGE
VAA5 VREF
(VCC)
C2-C4 C5-C7
XTAL[1] XTAL[2]
RSET FSADJ VAA5 OUTPUT IN4148/9 MONITOR IN4148/9 Diode Protection Circuit
GROUND
COMP COMP2
Monitor
Table Typical Parts List Location C1-C4, C13, C17, C5-C7, C11, C15, C10, RSET Description Ceramic capacitor 0.01 Ceramic chip capacitor Tantalum capacitor Tantalum capacitor Metal film resistor 1000 Metal film resistor Metal film resistor 10-24 Crystal Voltage reference Vendor Part Number Erie RPE112Z5U104M50V 12102T103QA1018 Mallory CSR13F336KM Mallory CSR13F477KM Dale CMF-55C Dale CMF-55C National Semiconductor LM385Z-1.2
Note: vendor numbers above listed only guide. Substitution devices with similar characteristics will affect performance Bt497/8. Also, VAA5 pins shown refer analog VAA5s which located vicinity other analog pins.
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Bt497/498
BOARD LAYOUT CONSIDERATIONS
COMP Decoupling
COMP Decoupling
COMP must decoupled COMP2, typically using ceramic capacitor. Low-frequency supply noise will require larger value. COMP capacitor must close COMP COMP2 pins possible. surface-mount ceramic chip capacitor preferred minimal lead inductance, which degrades noise rejection circuit. Short, wide traces will also reduce lead inductance. display ghosting problem, additional capacitance parallel with COMP capacitor help problem. ceramic capacitor should used decouple this input VAA5. VAA5 excessively noisy, better performance obtained decoupling VREF GND. Providing alternate pads (one VAA5 GND) recommended VREF decoupling capacitor. digital inputs Bt497/8 should isolated much possible from analog outputs other analog circuitry. These input signals should overlay analog power output signals. Most noise analog outputs will caused excessive edge rates (less than ns), overshoot, undershoot, ringing digital inputs. digital edge rates should faster than necessary, feedthrough noise proportional digital edge rates. Lower speed applications will benefit from using lower speed logic (3-5 edge rates) reduce data-related noise analog outputs. Transmission lines will mismatch they match source destination impedance. This degrades signal fidelity line length reflection time greater than one-fourth signal edge time. Line termination line length reduction solution. example, logic edge rates require line lengths less than inches without using termination. Ringing reduced damping line with series resistor (30-300 Radiation digital signals also picked analog circuitry. This prevented reducing digital edge rates (rise/fall time), minimizing ringing using damping resistors, minimizing coupling through board capacitance routing degrees analog signals. clock driver other digital devices circuit board must have adequate decoupling prevent noise generated digital devices from coupling into analog circuitry.
VREF Decoupling
Digital Signal Interconnect
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BOARD LAYOUT CONSIDERATIONS
Analog Signal Interconnect
Bt497/498
Analog Signal Interconnect
Bt497/8 should located close possible output connectors minimize noise pickup reflections impedance mismatch. maximize high-frequency power supply rejection, video output signals should overlay analog ground plane. maximum performance, analog video output impedance, cable impedance, load impedance should same. Analog output video edges exceeding monitor bandwidth reflected, producing cable-length dependent ghosts. Simple pulse filters reduce high-frequency energy, reducing noise. filter impedance must match line impedance. Bt497/8 analog outputs should protected against high-energy discharges, such those from monitor arc-over from "hot-switching" AC-coupled monitors. diode protection circuit shown Figure prevent latchup under severe discharge conditions without adversely degrading analog transition times. 1N4148/9 low-capacitance, fast-switching diodes, which also available multiple device packages (FSA250X FSA270X) surface-mountable pairs (BAV99 MMBD7001).
Analog Output Protection
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APPLICATION INFORMATION
Test Features Bt497/8
Bt497/498 contains Signature Analysis Control Register (SAR), output comparator, JTAG test structures that assist user evaluating performance functionality part. This section explains operating usage these test features.
Signature Analysis Control Register (SAR)
When enabled, output operates with bits data that presented inputs. These 24-bit vectors represent single pixel color, presented simultaneously inputs red, green, blue SARs, well three on-chip DACs. acts wide linear feedback shift register each succeeding input. simplify feedback circuitry 25th been added, corresponding test input. written read through port which represents fourth load cycle. Bt497/8 will only generate signatures during active video fields, starting first even field following Signature Capture Request SAR. After signature been acquired, available reading writing port. Typically, user will write specific 25-bit seed value into SAR, then Signature Capture Request bit. full field known pixel information will then input chip, after which resultant 25-bit signature read MPU. 25-bit signature results from same color data that DACs. Thus, overlay, cursor, palette bypass data validity also tested using SARs. linear feedback configuration shown Figure
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APPLICATION INFORMATION
Analog Comparator
Bt497/498
When performing system tests that SAR, recommended that pipeline delay reset prior test provide allowance input clock drift. This prevents disruption pixel data because pipeline auto-reset, which occur phase relation input clock drifts with respect output clocks. Excessive input clock drift require that signatures acquired over shorter periods where maximum drift more tightly controlled. This especially recommended during environmental power supply variation testing.
Figure Signature Analysis Feedback Circuit
D[7:0] R[7:0] D[15:8] G[7:0] D[23:16] B[7:0]
GREEN 01234567
BLUE
D[24]
Analog Comparator
other dedicated test structure Bt497/8 analog comparator. allows user measure DACs against each other, well against specific reference voltage. Four combinations tests selected Control Register. With given setting, respective signals (DAC outputs reference) will continuously input comparator. result comparator latched into Timing Generator Test Register. capture occurs bottom-right point cursor map. simple design comparator, recommended that outputs stable before capture. display rate MHz, corresponds pixels. Furthermore, either color palette pixel inputs both) should configured guarantee single continuous output from DACs under test, until capture.
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Bt497/498
APPLICATION INFORMATION Device Identification Register
Device Identification Register
Bt497/8 incorporates Device Identification Register (Figure which accessed port. register read only uniquely identifies device accordance with requirements principles forth JEDEC organization. final value read port $A236C1AD.
Figure Device Identification Register Version bits Part Number Manufacturer $0D6 bits
9068, $236C bits
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APPLICATION INFORMATION
JTAG Registers
Bt497/498
JTAG Registers
Bt497/8 incorporates special circuitry that allows accessed full compliance with standards Joint Test Action Group (JTAG). Conforming IEEE P1149.1, Standard Test Access Port Boundary Scan Architecture, Bt497/8 dedicated pins that used test purposes only. JTAG uses boundary-scan cells placed each digital pin, both inputs outputs, shown Figure scan cells interconnected into Boundary-Scan Register (BSR), which applies captures test data used functional verification Bt497/8. Note that even though Bt497 pixel pins connected package, JTAG users Bt497 still need account unconnected Port boundary-scan cells when they utilize Bt497 Boundary-Scan Register. JTAG particularly useful board testers using functional testing methods. JTAG five dedicated pins that comprise Test Access Port (TAP): Test Mode Select (TMS), Test Clock (TCK), Test Data Input (TDI), Test Data (TDO) Test Reset (TRST*). Connection verification Bt497/8 achieved through these five pins. With boundary-scan cells each digital pin, Bt497/8 able apply capture logic level. Since digital pins interconnected long shift register, logic access control pins necessary verify functionality. controller shift number test vectors through input apply them internal circuitry. output result scanned externally checked. While isolating Bt497/8 from other components board, user easy access Bt497/8 digital pins through perform complete interconnect testing without using expensive bed-of-nails testers. bidirectional port other digital I/Os require extra attention with respect JTAG. Because JTAG requires full control over each digital pin, additional Output Enable (OE) cells included port (OEMPU) various digital I/Os (OEFM). When loaded JTAG instructions, these cells control directionality their respective pins. Tables give further details concerning JTAG accessible registers test instructions supported. Brooktree created BSDL with AT&T Editor. Should JTAG testing implemented, disk with ASCII version complete BSDL file obtained calling 1-800-2BtApps.
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Bt497/498
APPLICATION INFORMATION
JTAG Registers
Figure JTAG Boundry Scan Registers
PA[0] PB[32] PA[1] PB[33] PA[2] PB[34] PA[3] PB[35] PA[4] PB[36] PA[5] PB[37] PA[6] PB[38] PA[7] PB[39] PA[8] PB[40] PA[9] PB[41] PA[10] PB[42] PA[11] PB[43] PA[12] PB[44]
PA[13] PB[45] PA[14] PB[46] PA[15] PB[47] PA[16] PB[48] PA[17] PB[49] PA[18] PB[50] PA[19] PB[51] PA[20] PB[52] PA[21] PB[53] PA[22] PB[54] PA[23] PB[55] PA[24] PB[56] PA[25] PB[57]
PA[26] PB[58] PA[27] PB[59] PA[28] PB[60] PA[29] PB[61] PA[30] PB[62] PA[31] PB[63] PA[32] PB[0] PA[33] PB[1] PA[34] PB[2] PA[35] PB[3] PA[36] PB[4] PA[37] PB[5] PA[38]
PB[6] PA[39] PB[7] PA[40] PB[8] PA[41] PB[9] PA[42] PB[10] PA[43] PB[11] PA[44] PB[12] PA[45] PB[13] PA[46] PB[14] PA[47] PB[15] PA[48] PB[16] PA[49] PB[17] PA[50] PB[18] PA[51]
PB[19] PA[52] PB[20] PA[53] PB[21] PA[54] PB[22] PA[55] PB[23] PA[56] PB[24] PA[57] PB[25] PA[58] PB[26] PA[59] PB[27] PA[60] PB[28] PA[61] PB[29] PA[62] PB[30] PA[63] PB[31] OEFM
FIELD SCEN* STSCAN* SCLK* MON[0] MON[1] MON[2] MON[3] OEMPU D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] C[1] C[0] RESET* CSYNC* CLOCK* CLOCK
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APPLICATION INFORMATION
JTAG Registers
Bt497/498
Table JTAG Registers Name Instruction Register (IR) Boundary Scan Register (BSR) Signature Analysis Register (SAR) Bypass Register (BYR) Width Description Holds decodes active instruction. Corresponds chip digital pins. Test-Register checks full data path. Holding D-FF, bypassing chip.
Table JTAG Instructions Code 7-$F Name EXTEST INTEST SAMPLE <Reserved> <Reserved> SCNOSR <Reserved> BYPASS Pass data from direct TDO. Scan contents through TAP. Register Description Scan test-vector, apply outputs. Scan test-vector, apply inputs. Capture levels BSR, scan out.
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Bt497/498
APPLICATION INFORMATION
Initializing Bt497/8
Initializing Bt497/8
Power VAA5 VAA3 supplies order. Assert release TRST*. Assert release RESET* twice. write instructions given initialization sequence will configure Bt497/8 following settings: pixel format Block Cursor, enabled both planes Cursor position Sync-on-green enabled, blank pedestal, analog compare enabled (assumes 13.5 crystal, plus (active) locations programmed True color, with input from port_A, color model palette Timing generator programmed 1280 1024, noninterlaced mode, VSYNC* enabled, HSYNC* enabled, EQUALIZATION disabled. following register states will endure from their Reset defaults: enabled Serial monitor inputs transparent overlay, double buffer, display enabled, pullups enabled pending transfer
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APPLICATION INFORMATION
Initializing Bt497/8
Bt497/498
Initialization Sequence
best results, follow Order Writes given below. important have intended Pixel Format Register selection done before enabling Control Register. Every access consists four cycles, where each cycle transfers byte.
Pixel Clock Control C1,C0
Write $1000 Configuration Pointer Write Pixel Format Register Write Configuration Pointer Write $401A7 Control Register
Load Cursor: Bitmap, Colors, Position
C1,C2
Write Cursor Pointer Write $FFFFFFFF Cursor (location Write $FFFFFFFF Cursor (location
Write $FFFFFFFF Cursor (location $FF) Write red, green, blue data Color Write red, green, blue data Color Write red, green, blue data Color Write $400030 Cursor Position Register
Load Palette
Write $2000 Configuration Pointer Write red, green, blue data Palette Write red, green, blue data Palette
Write red, green, blue data Palette
Load Registers, Control
Write $3120 Configuration Pointer Write Active (location Write Active (location Write Active (location $1f) Write $5001 Configuration Pointer Write Control Register
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Bt497/498
APPLICATION INFORMATION
Initializing Bt497/8
Load Timing Generator Registers
Write $6001 Configuration Pointer Write $027 VBNP Register Write $427 VBAP Register Write $007 VSNP Register Write $429 VSAP Register Write $31F HSERNP Register Write $0AF HBNP Register Write $32F HBAP Register Write $01F HSNP Register Write $33F HSAP Register Write $32E HSCENNP Register Write $0AE HSCENAP Register
Release Timing Generator, Begin Display
(Assumes frame buffer pixel generator ready:) Write $6000 Configuration Pointer Write $023 Timing Generator Control Register
1280 1024 Noninterlaced Display
Table noninterlaced register values. Horizontal Pixels: 1280 Vertical Lines: 1024 Horizontal Frequency: 81.13 Horizontal Sync: 0.474 Horizontal Unblanked: 9.48 Horizontal Blanking: 2.84 Total Vertical Lines: 1066 Vertical Frequency: 76.11 Vertical Sync: Lines Pixel Clock: Crystal: 13.5 Frame Buffer Pipeline: serial clock cycle
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APPLICATION INFORMATION
Initializing Bt497/8
Bt497/498
Table 1280 1024 Noninterlaced Register Values Register VBNP VBAP VSNP VSAP HSERNP HBNP HBAP HSNP HSAP HSCENNP HSCENAP Value (dec) 1063 1065 $027 $427 $007 $429 $31F $0AF $32F $01F $33F $32E $0AE
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Bt497/498
APPLICATION INFORMATION
Initializing Bt497/8
NTSC Interlaced Display
Table NTSC register values. Horizontal Pixels: Vertical Lines: Horizontal Frequency: 15.73 Horizontal Sync: 4.73 Horizontal Unblanked: 52.15 Horizontal Blanking: 11.41 Total Vertical Lines: Vertical Frequency: 59.94 Vertical Sync: Lines Equal. Pulses: Post full lines after equal before line active video field Pixel Clock: 12.273 Crystal: 13.5 Control Register PLL: Enable Pixel Format Control Register Pixel Format: 4/2:1 Timing Generation Control Register EQUAL*: Enabled Interlaced mode: Enabled VSYNC*: Enabled HSYNC*: Enabled Frame Buffer Pipeline: serial clock cycle
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APPLICATION INFORMATION
Initializing Bt497/8
Bt497/498
Table NTSC Register Values Register VBNP VBAP VSNP VSAP HSERNP HBNP HBAP HSNP HSAP HSCENNP HSCENAP EQNP EINP EIAP Value (dec) $205 $20C $206
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Bt497/498
APPLICATION INFORMATION
Initializing Bt497/8
Interlaced Display
Table register values. Horizontal Pixels: Vertical Lines: Horizontal Frequency: 15.62 Horizontal Sync: 4.79 Horizontal Unblanked: 52.51 Horizontal Blanking: 11.49 Total Vertical Lines: Vertical Frequency: Vertical Sync: Lines Equalization Pulses:5 Post full lines after equal before line active video field Pixel Clock: 14.625 Crystal 13.5 Control Register PLL: Enable Pixel Format Control Register Pixel Format: 4/2:1 Timing Generation Control Register EQUAL*: Enabled Interlaced Mode: Enabled VSYNC*: Enabled HSYNC*: Enabled Frame Buffer Pipeline: serial clock cycle
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APPLICATION INFORMATION
Initializing Bt497/8
Bt497/498
Table Register Values Register VBNP VBAP VSNP VSAP HSERNP HBNP HBAP HSNP HSAP HSCENNP HSCENAP EQNP EINP EIAP Value (dec) $26A $270 $26B
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Bt497/498
APPLICATION INFORMATION
Initialization
Initialization
Bt497/8-Generated VRAM Shift Clock PLL-Generated Pixel Clock this configuration, pixel clock generated using on-chip PLL. runs continuously meant shift pixel data from VRAMs. Here, relatively low-frequency crystal connected XTAL1 XTAL2 inputs, instead using oscillator operated pseudo-ECL supply (i.e., GND) connected CLOCK CLOCK* inputs Bt497/8, shown Figures Circuit Description section this document. crystal frequency should selected based required pixel rate(s) display pixel rate tolerance. desired ratio then computed dividing required pixel rate crystal frequency, looking values ratio table (Table closest ratio, ensuring that display still operate satisfactorily within best-fit pixel rate associated timings. clock ratio programming values through port. Reset values respectively, yielding pixel rate times crystal reference. Table shows complete range ratios ranges from ranges from 13.5 14.318 crystals. Table shows frequency only. Pixel rate further selectable 1/1, 1/2, 1/4, frequency programming value. Users planning utilize exclusively should still provide definite connections CLOCK CLOCK* pins, shown Figure With this hookup, user shut pixel display operation chip time save power. This clock shut accomplished writing into Control Register. Among other effects, note that this will also force output state.
Crystal Frequency Selection
Ratio Selection
Deselection
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APPLICATION INFORMATION
Initialization
Bt497/498
Figure CLOCK XTAL Connections Operation
CLOCK CLOCK* Divider
XTAL1 Crystal 10-24
Pixel Clock M/LxL
Internal RAMDAC Pixel Clock
XTAL2
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Bt497/498
APPLICATION INFORMATION
Initialization
Table Pixel Rate Selection Rate (MHz) Diff. w/Reference Crystal 13.50 6.714 6.727 6.750 6.778 6.800 6.818 6.833 6.857 6.875 6.889 6.900 6.909 7.000 7.091 7.100 7.111 7.125 7.143 7.167 7.182 7.200 7.222 7.250 7.273 7.286 7.300 7.333 7.375 7.400 7.429 0.19% 0.34% 0.41% 0.33% 0.27% 0.22% 0.35% 0.26% 0.20% 0.16% 0.13% 1.32% 1.30% 0.13% 0.16% 0.20% 0.25% 0.33% 0.21% 0.25% 0.31% 0.38% 0.31% 0.18% 0.20% 0.46% 0.57% 0.34% 0.39% 96.000 96.188 96.429 96.750 96.955 97.200 97.500 97.875 98.182 98.357 98.550 99.000 99.563 99.900 100.286 14.31818 96.136 96.322 96.648 97.045 97.364 97.624 97.841 98.182 98.437 98.636 98.795 98.926 100.227 101.529 101.659 101.818 102.017 102.273 102.614 102.831 103.091 103.409 103.807 104.132 104.318 104.523 105.000 105.597 105.955 106.364
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APPLICATION INFORMATION
Initialization
Bt497/498
Table Pixel Rate Selection Rate (MHz) Diff. w/Reference Crystal 13.50 7.444 7.500 7.556 7.571 7.600 7.625 7.667 7.700 7.714 7.750 7.778 7.800 7.833 7.857 7.875 7.889 7.900 8.000 8.111 8.125 8.143 8.167 8.200 8.222 8.250 8.286 8.333 8.375 8.400 8.429 0.21% 0.75% 0.74% 0.21% 0.38% 0.33% 0.55% 0.43% 0.19% 0.46% 0.36% 0.29% 0.43% 0.30% 0.23% 0.18% 0.14% 1.27% 1.39% 0.17% 0.22% 0.29% 0.41% 0.27% 0.34% 0.43% 0.57% 0.50% 0.30% 0.34% 100.500 101.250 102.000 102.214 102.600 102.938 103.500 103.950 104.143 104.625 105.000 105.300 105.750 106.071 106.313 106.500 106.650 108.000 109.500 109.688 109.929 110.250 110.700 111.000 111.375 111.857 112.500 113.063 113.400 113.786 14.31818 106.591 107.386 108.182 108.409 108.818 109.176 109.773 110.250 110.455 110.966 111.364 111.682 112.159 112.500 112.756 112.955 113.114 114.545 116.136 116.335 116.591 116.932 117.409 117.727 118.125 118.636 119.318 119.915 120.273 120.682
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Bt497/498
APPLICATION INFORMATION
Initialization
Table Pixel Rate Selection Rate (MHz) Diff. w/Reference Crystal 13.50 8.444 8.500 8.556 8.571 8.600 8.625 8.667 8.714 8.750 8.778 8.800 8.833 8.857 8.875 8.889 9.000 9.125 9.143 9.167 9.200 9.250 9.286 9.333 9.375 9.400 9.429 9.500 9.571 9.600 9.625 0.19% 0.66% 0.65% 0.19% 0.33% 0.29% 0.48% 0.55% 0.41% 0.32% 0.25% 0.38% 0.27% 0.20% 0.16% 1.25% 1.39% 0.20% 0.26% 0.36% 0.54% 0.39% 0.51% 0.45% 0.27% 0.30% 0.76% 0.75% 0.30% 0.26% 114.000 114.750 115.500 115.714 116.100 116.438 117.000 117.643 118.125 118.500 118.800 119.250 119.571 119.813 120.000 121.500 123.188 123.429 123.750 124.200 124.875 125.357 126.000 126.563 126.900 127.286 128.250 129.214 129.600 129.938 14.31818 120.909 121.705 122.500 122.727 123.136 123.494 124.091 124.773 125.284 125.682 126.000 126.477 126.818 127.074 127.273 128.864 130.653 130.909 131.250 131.727 132.443 132.955 133.636 134.233 134.591 135.000 136.023 137.045 137.455 137.812
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APPLICATION INFORMATION
Initialization
Bt497/498
Table Pixel Rate Selection Rate (MHz) Diff. w/Reference Crystal 13.50 9.667 9.714 9.750 9.800 9.833 9.857 9.875 10.000 10.143 10.167 10.200 10.250 10.286 10.333 10.400 10.429 10.500 10.571 10.600 10.667 10.714 10.750 10.800 10.833 10.857 11.000 11.143 11.167 11.200 11.250 0.43% 0.49% 0.37% 0.51% 0.34% 0.24% 0.18% 1.27% 1.43% 0.23% 0.33% 0.49% 0.35% 0.46% 0.65% 0.27% 0.68% 0.68% 0.27% 0.63% 0.45% 0.33% 0.47% 0.31% 0.22% 1.32% 1.30% 0.21% 0.30% 0.45% 130.500 131.143 131.625 132.300 132.750 133.071 133.313 135.000 136.929 137.250 137.700 138.375 138.857 139.500 140.400 140.786 141.750 142.714 143.100 144.000 144.643 145.125 145.800 146.250 146.571 148.500 150.429 150.750 151.200 151.875 14.31818 138.409 139.091 139.602 140.318 140.795 141.136 141.392 143.182 145.227 145.568 146.045 146.761 147.273 147.955 148.909 149.318 150.341 151.364 151.773 152.727 153.409 153.920 154.636 155.114 155.455 157.500 159.545 159.886 160.364 161.080
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Bt497/498
APPLICATION INFORMATION
Initial
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