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port 10/100M Fast Ethernet Switching Controller General Description


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DM8108
port 10/100M Fast Ethernet Switching Controller General Description
DM8108 port 10/100Mbit/s nonblocking Ethernet switch with on-chip address-lookup engine. DM8108 provides low-cost, high-performance switch solution with PHYs single SGRAM. DM8108 provides eight 10/100Mbit/s Fast Ethernet interface. half-duplex mode, ports support backpressure capability reduce risk data loss long burst activity. full-duplex mode operation, device uses IEEE std. 802.3 frame-based pause protocol flow control. With full-duplex capability, port support 1.6Gbit/s aggregate bandwidth connections. DM8108 also supports port trunking/load balancing 10/100Mbit ports. This used group ports interswitch links increase effective bandwidth between systems. internal address-lookup engine supports 16.25K unicast unlimited multicast broadcast addresses. This engine performs destination source addresses book-keeping comparison which also forwards unknown destination address packets ports. DM8108 fabricated with .35um technology. Working 3.3V, inputs tolerant outputs capable directly driving levels.
Block Diagram
Control Status
Address Learning
Expansion
Controller Control Unit
Switching Engine
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Features
cost Fast Ethernet Switching Controller. Provide packet switching functions between eight 10/100Mbps, auto-negotiated on-chip Fast Ethernet ports proprietary Full-duplex Expansion port. Cascade max. DM8108s without extra glue logic 64-port configuration. Incorporates three 802.3 compliant 10/100Mbps Media Access Controllers Direct interface (Media Independent Interface) Half/Full Duplex Support individual port (upto 200Mbps/port) IEEE 802.3 100Base-TX, T4.FX compatible Auto-negotiation supported through Serial interface High-performance Distributed Switching Engine Performs packet forwarding filtering full wire-speed 148,800 packets/sec. each Ethernet port Direct support packet buffering Glue-less interface with Mbytes SDRAM (SGRAM) memory configuration 90Mhz memory speed Up-to 1.1K buffers, 1536-byte each, allocated receive ports Support Store Forward switching approach
last-bit first-bit delay Allow mixed speed Ethernet packet switching Allow conversion between different protocols Flow control Support partitioning function Support back-pressure while lack internal resources Support 802.3x PAUSE function full duplex mode Support 4-port trunking 800Mbps bandwidth Advanced Address Learning Searching Self learning mechanism Cache address entries internally Record up-to Uni-cast addresses unlimited Multicast Broadcast addresses Automatic aging scheme Broadcast filtering rate control Expansion Up-to devices cascaded expansion without extra logic Full duplex mode transfer Less overhead Automatic flow control Complete status report simple interface Suitable cost Switch market replace 0.35 process, 3.3V with tolerant 208-pin PQFP package
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Application Example: cost ports 10/100 Mbps auto-sensing switch
DM8108
DM8108
DM8108
10/100 BaseTx Cascaded up-to 10/100Mbps Fast Ethernet ports
Application Example: cost auto-sensing switching implementation
DM8108
with repeater
with repeater
with repeater
with repeater
Module 10/100 BaseTx
Module
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
High density mixed switching ports with collision domains
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Configuration
Preliminary Version: DM8108-DS-P02 November 1999
TXD2[2] TXD2[3] RXER3 RXDV3 COL3 CRS3 RXCLK3 RXD3[0] RXD3[1] RXD3[2] RXD3[3] TXCLK3 TXEN3 TXD3[0] TXD3[1] TXD3[2] TXD3[3] MIICLK MIID RXER4 RXDV4 COL4 CRS4 RXCLK4 RXD4[0] RXD4[1] RXD4[2] RXD4[3] TXCLK4 TXEN4 TXD4[0] TXD4[1] TXD4[2] TXD4[3] RXER5 RXDV5 COL5 CRS5 RXCLK5 RXD5[0] RXD5[1] RXD5[2] RXD5[3] TXCLK5 TXEN5 TXD5[0] TXD5[1] TXD5[2]
LEDCLK LEDSTB LEDD RST# TESTEN RXER0 RXDV0 COL0 CRS0 RXCLK0 RXD0[0] RXD0[1] RXD0[2] RXD0[3] TXCLK0 TXEN0 TXD0[0] TXD0[1] TXD0[2] TXD0[3] RXER1 RXDV1 COL1 CRS1 RXCLK1 RXD1[0] RXD1[1] RXD1[2] RXD1[3] TXCLK1 TXEN1 TXD1[0] TXD1[1] TXD1[2] TXD1[3] RXER2 RXDV2 COL2 CRS2 RXCLK2 RXD2[0] RXD2[1] RXD2[2] RXD2[3] TXCLK2 TXEN2 TXD2[0] TXD2[1]
RXD8[3] RXD8[2] RXD8[1] RXD8[0] RXCLK8 TXD8[3] TXD8[2] TXD8[1] TXD8[0] TXCLK8 DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 SDDQM# DWE# SDCS# CAS# RAS# SCLK DMD0 DMD1 DMD2 DMD3 DMD4 DMD5 DMD6 DMD7 DMD8 DMD9 DMD10 DMD11 DMD12 DMD13 DMD14 DMD15
DM8108
DMD16 DMD17 DMD18 DMD19 DMD20 DMD21 DMD22 DMD23 DMD24 DMD25 DMD26 DMD27 DMD28 DMD29 DMD30 DMD31 TXD7[3] TXD7[2] TXD7[1] TXD7[0] TXEN7 TXCLK7 RXD7[3] RXD7[2] RXD7[1] RXD7[0] RXCLK7 CRS7 COL7 RXDV7 RXER7 TXD6[3] TXD6[2] TXD6[1] TXD6[0] TXEN6 TXCLK6 RXD6[3] RXD6[2] RXD6[1] RXD6[0] RXCLK6 CRS6 COL6 RXDV6 RXER6 TXD5[3]
DM8108
port 10/100M Fast Ethernet Switching Controller Description
Assignment
NAME LEDCLK LEDSTB LEDD RST* TESTEN* RXER0 RXDV0 COL0 CRS0 RXCLK0 RXD0(0) RXD0(1) RXD0(2) RXD0(3) TXCLK0 TXEN0 TXD0(0) TXD0(1) TXD0(2) TXD0(3) RXER1 RXDV1 COL1 CRS1 RXCLK1 RXD1(0) RXD1(1) RXD1(2) RXD1(3) TXCLK1 TXEN1 TXD1(0) TXD1(1) TXD1(2) TXD1(3) RXER2 RXDV2 COL2
NAME CRS2 RXCLK2 RXD2(0) RXD2(1) RXD2(2) RXD2(3) TXCLK2 TXEN2 TXD2(0) TXD2(1) TXD2(2) TXD2(3) RXER3 RXDV3 COL3 CRS3 RXCLK3 RXD3(0) RXD3(1) RXD3(2) RXD3(3) TXCLK3 TXEN3 TXD3(0) TXD3(1) TXD3(2) TXD3(3) MDCLK MDIO RXER4 RXDV4 COL4 CRS4 RXCLK4 RXD4(0) RXD4(1) RXD4(2) RXD4(3) TXCLK1
NAME TXEN4 TXD4(0) TXD4(1) TXD4(2) TXD4(3) RXER5 RXDV5 COL5 CRS5 RXCLK5 RXD5(0) RXD5(1) RXD5(2) RXD5(3) TXCLK5 TXEN5 TXD5(0) TXD5(1) TXD5(2) TXD5(3) RXER6 RXDV6 COL6 CRS6 RXCLK6 RXD6(0) RXD6(1) RXD6(2) RXD6(3) TXCLK6 TXEN6 TXD6(0) TXD6(1) TXD6(2) TXD6(3) RXER7 RXDV7 COL7 CRS7
NAME RXCLK7 RXD7(0) RXD7(1) RXD7(2) RXD7(3) TXCLK7 TXEN7 TXD7(0) TXD7(1) TXD7(2) TXD7(3) MD(31) MD(30) MD(29) MD(28) MD(27) MD(26) MD(25) MD(24) MD(23) MD(22) MD(21) MD(20) MD(19) MD(18) MD(17) MD(16) MD(15) MD(14) MD(13) MD(12) MD(11) MD(10) MD(9) MD(8) MD(7) MD(6) MD(5)
NAME MD(4) MD(3) MD(2) MD(1) MD(0) SCLK SRAS* SDCAS* SDCS* SDWE* SDQM* MA(10) MA(9) MA(8) MA(7) MA(6) MA(5) MA(4) MA(3) MA(2) MA(1) MA(0) TXENCLK TXD8(0) TXD8(1) TXD8(2) TXD8(3) RXDVCLK RXD8(0) RXD8(1) RXD8(2) RXD8(3)
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Description (continued)
Please refer "Strap default value after reset section detail description Strap pins. DRAM Interface 146, 155, 164, 184, 189, Expansion Name RXDVCLK RXD8[3:0] TXENCLK TXD8[3:0] Description Expansion port's receiving data valid Expansion port's receive data input Expansion port's transmit enable output Expansion port's transmit data output Strap pins during reset: TXD8[2:0] device setting TXD8[3] dram timing Name MD(31:0) Description DRAM data lines
MA(10:0)
SRAS* SDCAS* SDWE* SDQM SDCS*
DRAM address lines 10-0; strap pins during reset MA9: enable limit4, 1=disbale limit MA8: DRAM size selection; 1=2M MA7-0: Auto-negotiation enable port 7-0; enabled address strobe SDRAM Column address strobe SDRAM Write cycle indication, internally pulled Data Mask SDRAM Chip select SDRAM
Interface Name LEDCLK LEDD Description data clock data: active low. Data stream that contains indicators port. data shifted should qualified LDSTB* clock into external registers drive LEDs. Strap during reset: expansion port with fast speed expansion port with lower apees data strobe: active high. Used strobe into external register Strap during reset: force link link detection through serial
LDSTB
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Interface 133,117,101, 85,66,50,34,18 Name TXEN(7:0) Description Transmit Enable: Active high, synchronous TXCLK; indicate that transmission data valid. Strap function during reset-TXEN(7:0): port full duplex Transmit Clock: Provides timing reference transfer TXEN, signals. 25MHz 100Mbps 2.5MHz 10Mbps. Transmit data port synchronous TXCLK0. Strap function during reset-TDX0[0]: 0=80Mhz, 1=66Mhz CLOCK operation TXD0[1]: 0=enable partition mode, 1=disable partition mode TXD0[2]: 0=enable expansion port, 1=disable expansion port TXD0[3]: 0=init only, enable BIST Transmit data port synchronous TXCLK1. Strap function during reset -TXD1[2:0]: test mode TXD1[3]: 0=enable CRC, 1=disbale Transmit data port synchronous TXCLK2. Strap function during reset -TXD2[2:0]: device setting TXD2[3]: DRAM timing 0=fast, 1=slow Transmit data port synchronous TXCLK3. Strap function during reset -TXD3[0]: 0=max. packet size 1536, 1=max. packet size 1518(default) TXD3[1]: 0=enable back_pressure, disable (default) TXD3[3:2]: strap pins sec. sec. sec. disbale Transmit data port synchronous TXCLK4. Strap function during reset TXD4[0]: port trunking enable port trunking (default) TXD4[1]: port trunking enable port trunking (default) TXD4[2]: port trunking enable port trunking (default) TXD4[3]: port trunking enable port trunking (default) Transmit data port synchronous TXCLK5. Strap function during reset TXD5[1:0]: broadcast filtering rate selection 8k/sec 16k/sec 64k/sec disable Transmit data port synchronous TXCLK6. Transmit data port synchronous TXCLK7. Receive data port synchronous RXCLK0. Receive data port synchronous RXCLK1. Receive data port synchronous RXCLK2. Receive data port synchronous RXCLK3. Receive data port synchronous RXCLK4.
Preliminary Version: DM8108-DS-P02 November 1999
132,116,100,84, 65,49,33,17
TXCLK(7:0)
TXD0(3:0)
TXD1(3:0)
TXD2(3:0)
TXD3(3:0)
TXD4(3:0)
-102
TXD5(3:0)
-118 -134
TXD6(3:0) TXD7(3:0) RXD0(3:0) RXD1(3:0) RXD2(3:0) RXD3(3:0) RXD4(3:0)
DM8108
port 10/100M Fast Ethernet Switching Controller
127,111,95,79, 60,44,28,12 124,108,92,76, 57,41,25,9 123,107,91,75, 56,40,24,8 126,110,94,78, 59,43,27,11 125,109,93,77, 58,42,26,10 RXD5(3:0) RXD6(3:0) RXD7(3:0) RXCLK(7:0) RXDV(7:0) RXER(7:0) CRS(7:0) COL(7:0) Receive data port synchronous RXCLK5. Receive data port synchronous RXCLK6. Receive data port synchronous RXCLK7. Receive clock port synchronous RXD, RXDV,RXER; same clock rate TXCLK. Receive data valid indication port Receive data error indication port Carrier sense; active high. Indicates that either transmit receive medium Idle. synchronous clock. Collision Detect; active high. Indicates collision been detected wire. This input ignored during full duplex operation half duplex mode while TXEN same port low. Serial management interface clock signal: 1MHz clock MDIO data reference. Connected ports; input device SDRAM mode; else, output pin. Serial management interface data; this bi-direction line used transfer control Information status between DM8108. conforms IEEE-802.3 specifications. This signal connected devices ports. Pulled down used.
MDCLK
MDIO
Miscellaneous Interface pins Name SCLK RST* TESTEN* Description Memory clock: used DRAM state machine. Reset signal chip. Test enable test functions
Power pins 23,55,90,122, 156,185,198 1,7,39,71,74, 106,138,147, 165,174,176, 181,190,196, Name Power Ground Description Connected 3.3V Power plane Connected Ground plane
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Functional Description
Fast Ethernet Ports Functional Overview DM8108 high-performance, low-cost Fast Ethernet Switching Controller which provides packet switching between eight on-chip, 10/100 Mbps ports optional expansion port. suitable auto-sensing 10/100Mbps switch application. Switching Architecture switching architecture based shared memory handshaking signals switch packets between on-chip ports hard-wired. incoming packet, receiving port's stores receiving buffers good packet. same time, switching engine determines which port packet will forward update address table which will used future packet forwarding reference. Fast Ethernet Ports DM8108 integrates eight Fast Ethernet ports, working 10/100Mbps (half-duplex) 20/200Mbps (full-duplex) with off-the-shelf chips. interface glue-less through Media Independent Interfaces (MII). autonegotiation function determines port's operating mode. With auto-negotiation disabled, ports forced operate certain mode, desired. Each port includes Media Access Control function (MAC), signals Link, Collision, Receive/Transmit, Half/Full duplex Receive Buffer Full indications. Address Recognition DM8108 system recognize Uni-cast addresses unlimited Multicast/Broadcast addresses. intelligent address recognition mechanism enables filtering forwarding packets full Ethernet wire speed. DM8108 provides address self-learning mechanism. each DM8108 learns address, updates address table storage.
Fig.1: Typical 10/100 Mbps auto-sensing switching application
optional DM8108 DM8108
10/100 Mbps
10/100 Mbps
Switch Ports
Switch Ports
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Packet Routing port DM8108 receives packet, DM8108 will received data receiving buffer start address recognition same time. destination address pointed local port other than receiving port, DM8108 will update Transmit Descriptor target port with buffer location byte count information wait transmission. destination address pointed port located other devices, DM8108 will update Transmit Descriptor expansion port with receiving buffer location byte count information wait transmission. destination address found Address Table, DM8108 will update Transmit Descriptors, except receiving port, transmission. Multicast/Broadcast addresses, DM8108 simply updates Transmit Descriptors, except receiving port ports that disabled, Transmission. packet, DM8108 simply discards receiving buffer Transmit Descriptor particular port full, packet will lost. DM8108 targeted non-managed Ethernet Switching application. management functions provided.
DRAM Interface DM8108 interfaces bytes SGRAM SDRAM. DRAM used store incoming packets well address table Transmit Descriptors. DRAM operate 90MHz. 256kx32 512kx16 SGRAM required respectively shared memory size.
Expansion expansion contains Receive Port Transmit Port. Each port 4-bit wide. Receive Port takes incoming packet into FIFO that distributed Receiving Buffer immediately. same time, DM8108 will check destination source addresses determine target port update Address Table necessary. Transmit Port dedicated transferring packets other switching members Transmit Descriptor this port saying transmission pending. Total 8-DM8108 cascaded 64-port switching system.
Network Management Features
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Operation Overview
Architecture Family switching devices been defined cost, high performance scalable architecture small switching system packetized data. Various devices will developed. OEMs will able design robust switching configurations based architecture. Architecture Family uses "store-andforward' switching approach. This approach following advantages: Store-and-forward switches allow switching between differing speed media (e.g. 10Mbps 100Mbps). Store-and-forward switches improve overall network performance acting `network cache', effectively buffering packets during times heavy congestion. Store-and-forward switches prevent erroneous packets from forwarding analyzing frame check sequence (FCS) before forwarding destination port. Store-and-forward switches prevent illegal frames (runt oversized) from being forwarded thereby reduce congestion caused packets. DM8108 automatically learns port number attached network devices examining Source address incoming packets. Source Address found Address Table, device adds table (with source port device information). Address Table managed DM8108 individually. Address Learning DM8108 learn unique addresses. Addresses stored Address Table located DRAM which will initialized after RESET. Packet Buffering Incoming packets buffered DRAM array. These buffers provide elastic storage transferring data between low-speed high speed segments. packet buffers managed automatically DM8108. Packet Forwarding Protocol DM8108 updates Transmit Descriptor target port, which learned from Address Table, with received packet buffer location packet length. target port will fetch packet transmission once memory available. Expansion Expansion defined special case normal Fast Ethernet port except running much higher data rate. designer link several DM8108s within switching link several switching boxes.
basic operation DM8108 very simple. DM8108 receives incoming packets from Ethernet ports, searches Address Table destination address, forwards packet appropriate port, which could either local (one DM8108's port) different DM8108 device that resides expansion bus. destination address found, packet will treated multicast packet sent every port (other than source port) other devices expansion bus.
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Theory Operation
Block Diagram
Expansion
Switching Engine
DRAM Controller
Control Registers Status Registers
Management
Control Unit
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Media Access Control Engine incorporates essential protocol requirement Ethernet IEEE-802.3 compliant node, provides interface between FIFO subsystem MII. primary attributes: Transmit receive message data encapsulation will discard illegally short (less than bytes frame data) oversized (greater than 1536 bytes) messages transmitted received. Framing (frame boundary delimitation, frame synchronization) frame terminates suffers collision before 64-bytes (after SFD) have been received, will automatically delete frame from FIFO. Addressing (source destination address handling) intercepts source destination address from incoming frame send them switching engine following purposes: update address table learn switching target detect DM8108 predefined address device control functions.
engine will automatically handle construction transmit frame. Once transmit FIFO been filled predetermined threshold access channel permitted, will commence following transmission: receiving section will detect incoming preamble sequence when RXDV signal activated external PHY. will discard preamble begin searching SFD. Once detected, subsequent nibbles treated part frame. will discard message shorter than 64-bytes longer than 1518 (1536) bytes. received frame will sent Receiving Buffer switching.
Preamble 1010.1010 Bytes
10101011 Bytes
Destination Address Bytes
Source Address Bytes
Error detection (physical medium transmission errors) During transmission, switching engine failed keep transmit FIFO filled sufficiently, cause underflow, engine will guarantee message either sent runt packet (which will detected receiving station) invalid (which will cause receiver reject packet). During reception, generated every nibble (including dribbling bits) coming from cable, although internally saved value only updated eighth each byte boundary). engine will ignore additional bits message (dribbling bits), that occur under normal network operating conditions.
Length Bytes
Data 1500 Bytes
Bytes
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Media access management IEEE 802.3 protocols define media access mechanism that permits stations access channel with equality. node attempt connect channel waiting predefined period time (Inter Packet Gap) after last activity before transmitting media. nodes simultaneously contend channel, their signals will interact causing loss data, defined collision. responsibility attempt avoid recover from end-to-end transmission receiving station. Medium allocation (collision avoidance, except full-duplex operation) time. will complete preamble (64-bit) (32-bit) sequence before ceasing transmission invoking random back-off algorithm.
Contention resolution (collision handling, except full-duplex mode)
will monitor medium traffic watching carrier activity. When carrier detected, media considered busy, should defer existing message. implements IEEE-802.3 defined part deferral algorithm, with Inter-Frame-SpacngPart1 (IFS1) time 64-bit time (6.4 for10-BASE 100-BASE). Inter-FrameSpacing-Part2 (IFS2) interval therefore, 32-bit time. Inter Packet (IPG) timer will start timing 96-bit time Inter-Frame-Spacing after receiving carrier de-asserted. During IFS1, will defer pending transmit frame respond receive message. counter will cleared continuously until carrier de-asserts, which point will resume 96-bit time count again. Once IFS1 period completed IFS2 commenced, will defer receiving frame transmit frame pending. will attempt receive receiving frame, since will start transmit generate collision 96-bit
collision detected through before complete preamble/SFD sequence been transmitted, engine will complete preamble/SFD before appending sequence. collision detected after preamble/SFD been completed, prior bits being transmitted, will abort transmission append sequence immediately. sequences 32-bit "34" pattern. will attempt transmit frame total times (15-retries) normal collisions (those within slot time). Detection collision will cause transmission re-scheduled time determined random back-off algorithm. attempts experienced collisions, transmitting message will flushed from FIFO. collision detected after 512-bit times have been transmitted, collision termed "Late" collision. will abort transmission, append sequence. retry attempt will scheduled detection late collision, transmit message will flushed from FIFO. implements truncated exponential back-off algorithm defined 802.3 standard. full-duplex mode, transmits unconditionally.
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
10/100 Mbps Half-duplex Transmission When frame ready transmission, samples link activity. signal inacive activity link), counter expired, frame transmission begins. data transmitted through TxD(3:0) transmitting port, clocked rising edge TxCLK. TxEN asserted same time. case collision, asserts signal MAC, which will then stop transmission will perform contention resolution. retry policy based the: Transmit Exception Conditions Under normal operating conditions will ensure that collisions that occurred within times from start transmission (including preamble) automatically retried with switching engine intervention. transmit FIFO ensures this guaranteeing that data contained within FIFO will overwritten until least bytes (512 bits) preamble plus address, length, data fields have been transmitted onto network without encountering collision. fullduplex mode, data FIFO overwritten soon transmitted. Under abnormal operating conditions Late collision
TxCLK TxEN, TxD(3:0)
25ns
10/100 Mbps Half-duplex Reception Frame reception starts with assertion RxDV (while transmitting) PHY. Once RxDV asserted, will begin sampling incoming data pins RxD(3:0) rising edge RxCLK. Reception ends when RxDV
asserted PHY. last nibble sampled nibble present RxD(3:0) last RxCLK rising edge which RxDV still asserted. detected assertion RxER while RxDV asserted, will designate this packet corrupted. following figure shows receive signals timing.
10ns min.
RxCLK RxDV, RxER, RxD(3:0)
10ns min.
Preliminary Version: DM8108-DS-P02 November 1999
will abandon transmit process that frame, process next transmit frame ring. Frame experiencing late collision will retried.
DM8108
port 10/100M Fast Ethernet Switching Controller
Receive Exceptional Conditions Abnormal network operating conditions Abnormal network conditions include: During reception, will ensure that collision occurs during packet reception, packet will automatically deleted from receive FIFO. Receive FIFO also will delete frame that composed fewer than bytes (Runt Packet). errors Normal network operating conditions
error occurred, will discard packet. Late Collision Late Collision collision being detected after 512-bit times while receiving. FIFO transfer error also monitors FIFO overflow status, which will force most recent receiving packet (not finished) FIFO discarded. Back-pressure DM8108 will generate "jam pattern" force collision media finds that internal resources meet demands.
10/100 Mbps Full-Duplex Operation When operating Full-duplex mode, signal associated with received frames only effect transmitted frames. signal ignored while Full-duplex mode. Transmission starts when TxEN goes active; regardless state RxDV. Reception starts when RxDV signal asserted indicating traffic receiving port. DM8108 supports IEEE 802.3x PAUSE function full duplex mode operation. During receiving, DM8108 will issues PAUSE command with largest timer value stop transmitter receiving buffer pointer above full threshold value (high water mark). When receiving buffer pointer below not-full threshold value (low water mark), will issue another PAUSE command with zero timer value start transmitter. DM8108 able monitor PAUSE command stop transmitting accordingly timer value specified command packet.
Preliminary Version: DM8108-DS-P02 November 1999
Reception checking received performed automatically MAC. equation
DM8108
port 10/100M Fast Ethernet Switching Controller
Functional Blocks
Collision, Recovery Timing
Protocol
Address Recognition Logic
Command Status Registers
Transfer Control Logic
Transfer Counters
Receive Control Logic
FIFO
FIFO
FIFO Control Logic
Generator Checker Transmit Control Logic
Preamble/Synch Pattern Gen.
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Management Management Registers Serial Access specification defines 16bit status control registers that addressable through serial data interface pins MDCLK MDIO. Please refer device's spec definition registers. DM8108 will initialize management registers accessing after RESET. memory configuration mode, DM8108 acts Serial initiator. SDRAM memory configuration, only DM8108 whose device equals initiator. Other devices cascaded will listener extract auto-negotiation information from stream. MDCLK maximum clock rate 2.5MHz. MDIO line bi-directional shared devices. protocol access waveform shown below:
MDCLK MDIO (DM8108) MDIO (PHY)
adle start code address Register address Register Data
Figure MDCLK
Typical MDIO Read Operation
MDIO (DM8108)
idle
start
code address
Register address
Write Data
Figure
Protocol Read Operation Write Operation
Typical MDIO Write Operation
<idle><start><op code><device address><register addr.><Turnaround>< data ><idle> xxxxx xxxxx ><xxxxh><idle> xxxxx xxxxx ><xxxxh><idle>
Table
Management Serial Protocol
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Auto-Negotiation Enabling Partition Mode Auto-negotiation disabled Partitioned mode enabled always. When ANEG* (MA[7:0]) strap high, autonegotiation disabled, corresponding port selected half- full- duplex mode respectively. Following RESET port duplex mode state sampled TXEN(7:0) pins. speed that each port operates (10Mbps 100Mbps) determined frequency TxCLK(7:0) RxCLK(7:0) generated PHY. generates 25MHz clock both TxCLK RxCLK 100Mbps operation 2.5MHz clock 10Mbps operation. Auto-negotiation enabled When ANEG* (MA[7:0]) pins tied low, decodes duplex mode from values Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-negotiation process. Once duplex mode resolved, DM8108 updates port control registers. DM8108 will continuously perform following operations each port (PHY address alternatively), implemented READ commands issued MDCLK/MDIO interface: Link Detection Link Detection Bypass (FLNK*) DM8108 will continuously query devices their link status associated with Auto-Negotiation Process. DM8108 will alternatively read registers from address update internal link bits according value register case link down (bit 1.2=0), that port will enter "link test fail state". this state, port's logic reset state. port will enter "link state" FLNK* (force link, LEDSTB* strobed during reset) sampled during reset. Partition Mode port enters partition mode when more than consecutive collisions seen port. partition mode port continuous transmit will receive. port returned normal operation mode when good packet seen wire.
Entering Partition State port will enter Partition state when PAEN* strap sampled during reset when either following conditions occurs: port detects collision every consecutive re-transmit attempts same packet. port detects single collision which occurs more than times.
expansion operates Full-Duplex mode that provides up-to 7200Mbps bandwidth device device connection. Several DM8108 cascaded pipe provide robust Ethernet Switching system. itself very simple. transmit receive ports contain independent data, valid handshake signals. arbitration involved.
Preliminary Version: DM8108-DS-P02 November 1999
While Partition state: port will continue transmit pending packet, regardless collision detection, will allow usual Back-off Algorithm. Additional packets pending transmission, will transmitted, while ignoring internal collision indication. This frees port's transmit buffers which would otherwise filled expense other ports buffers. assumption that partition signifying system failure situation (bad connection/cable/station), thus dropping packets small price cost halting switch buffer full condition. partition indication available interface.
Exiting from Partition State Port exits from Partition State, following successful packet transmission. successful packet transmission defined collisions were detected first bits transmission. Expansion
DM8108
port 10/100M Fast Ethernet Switching Controller
receive port utilizes RDVCLK clock received data into FIFO uses RXTOG requests Receiving Buffer block. switching engine will execute similar process Ethernet Ports. transmit port appends Sync. field normal Ethernet packet sends packet through TD(3:0) rising edge TXENCLK.
TXENCLK
TD(3:0)
Switching Engine packet switching processed Switching Engine, which following functions: Address Learning Process DM8108 self-learning mechanism learning addresses attached Fast Ethernet devices real time. DM8108 searches source address incoming packet Address Table acts follows: source address found Address Table, DM8108 waits until packet error) updates Address Table. source address found Address Table, DM8108 waits good packet received indication. Address Recognition DM8108 forwards incoming packets appropriate port(s) according Destination Address follows: packet from local port-1) Unicast address address found Address Table, DM8108 will: port number recorded matched port number which packet received, packet discarded. port numbers different, packet forwarded appropriate port. Unicast address address found Address Table, DM8108 acts
Preliminary Version: DM8108-DS-P02 November 1999
packet Multicast packet forwards Expansion Transmit port local ports except incoming port, Multicast/Broadcast address, packet forwarded Expansion Transmit port local ports (except port which packet received).
packet from Expansion Bus- Unicast address specified Destination Address Ethernet Packet, DM8108 will: recorded port pointed local port, packet will forwarded that port. destination address found (not recorded address learning process), packet will forwarded local ports Expansion Transmit port. Multicast/Broadcast address (destination device should invalid), packet will forwarded local ports Expansion Transmit port.
Address Aging DM8108 includes hardware support automatic address aging. Buffers Queues DM8108 incorporates transmit queues common receive buffer area Fast Ethernet ports Expansion Port, queues buffers located DRAM along with Address Table.
DM8108
port 10/100M Fast Ethernet Switching Controller
DM8108 data structure components following: Receiving Buffer common receive buffer allocated each Fast Ethernet Receiving Port Expansion Receiving Port. size receiving buffer defined 642KB (448 blocks) 1728KB (1152 blocks) (depending DRAM size) 1.5K Bytes each. DM8108 allocates buffers Ethernet ports Expansion port. Transmit Descriptors (TxDR) transmit descriptor rings. Each ring contains descriptors. Descriptor's size 32-bit contains Receiving Buffer's Block Number, packet length packet type (Multicast Uni-cast). Transmit Descriptors reside DRAM. Read/Write Pointers pairs pointers Transmit Descriptors.
Read Pointer
Write Pointer
Next Empty Block
Empty List
Descriptors:
Byte Count
1211
Block Number
Frame
Frame Frame Frame
Receive Buffer
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
DM8108 DRAM Address Mapping
Queue Buffers Receive Buffer Count Reserved queue Address Table Description 864KB blocks) 1872KB (1248blocks) unused 20KB 128KB Memory Size Byte 028000 0FFFFF 026000 027FFF 025000 025FFF 020000 024FFF 000000 01FFFF Byte 028000 1FFFFF 027000 027FFF 025000 025FFF 020000 024FFF 000000 01FFFF
Address Table Address Table structure occupies 128K bytes memory controlled initialized DM8108. Following RESET, DM8108 initializes
Field Address (47:0) Port Reserved Device Time Stamp
Address Table invalidating Valid entries.
Description Valid Indicates valid entry; Valid, valid. Source address. Unicast address only Port Number indicates which 3-port DM8108 associated with this source address. Port -Port Ethernet ports); Expansion Port. Device number-indicate which device switching system associated with this source address 4-bit Tag-used identify update sequence. entry-block(4-entry) pointed address index occupied, entry that oldest time stamp will replaced.
Packet Forwarding following sections describe procedures forwarding packets under different situations:
address entry. will point entry that specifies local port's number. reception error-free packet, packet information written appropriate port's transmit descriptor. This information includes Byte Count, Receive block address which points Write Pointer, Priority indication. Write Pointer outgoing port's transmit descriptor incremented. target port prepare transmission whenever Write Pointer Read pointer equal. engine resolves priority issue fills FIFO before starting transmission. FIFO under situation happens, force packet "Bad" inform engine retry. good transmit process, target port increments Read Pointer. Engine clears appropriate Empty List.
Forwarding Uni-cast packet local Ethernet port incoming packet FIFO transferred empty block Receive Buffer area DRAM. switching engine will claim block setting Empty List empty. case collision FIFO overflow, transfer error engine reset Empty List associated with block. parallel, address recognition cycle will performed both destination source address. DM8108 will learn changed
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Forward Multicast, Broadcast "Unknown" packet received packet's found Address Table, packet Multicast Broadcast packet, will treated Multicast packet, switching engine will perform most steps mentioned above forwards packet ports. Following RESET, DRAM controller will perform DRAM testing write/read several patterns invalidate entries Address Table. DRAM test result sent through status outputs. interface DM8108 provides data bus, address strobe signals DRAM Controller DM8108 includes direct support Synchronous DRAM. DRAM interface entirely glue-less. accesses performed 32-bit. memory controller designed targeting 90-MHz. DM8108 refreshes DRAM automatically. following timing diagram shows interface while displaying signals. Display chip ports' configuration transfer status, Display critical state signals debug purpose.
LDCLK LDSTB
signals having dynamic characteristics, DM8108 will maintain signal minimum
Dynamic signal
signals definition
before sending state triggered.
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
following table shows multiplexed signals.
Signals Primary_port status (link Primary_port status (link Primary_port status (link Primary_port status (link Primary_port status (link Primary_port status (link Primary_port status (link Primary_port status (link Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Signals Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Transmit Receiving Collision buffer full Reserved Reserved Full duplex Port Speed Partition Partition Partition Partition Partition Partition Partition Partition
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Runt packet Runt packet Runt packet Runt packet Runt packet Runt packet Runt packet Runt packet packet packet packet packet packet packet packet packet Under_flow(0) Under_flow(1) Under_flow(2) Under_flow(3) Under_flow(4) Under_flow(5) Under_flow(6) Under_flow(7) Link fail Link fail Link fail Link fail Link fail Link fail Link fail Link fail Pure_port_status(0) Pure_port_status(1) Pure_port_status(2) Pure_port_status(3) Pure_port_status(4) Pure_port_status(5) Pure_port_status(6) Pure_port_status(7) DRAM test status Internal SRAM test status
125-128
Expansion Port buf. full Dynamic allocation buf. full Reserved
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Strap Pins during Reset
following table shows strap pins during RESET. Symbol LEDSTB LEDD TXD0[3:0] Description Strap during reset: force link, link detection through serial (default) Strap TXENCLK frequency expansion port: 0=fast, slow (default) TXD0[0]: Strap operating frequency 0=88Mhz; 66Mhz (default) TXD0[1]: Strap enable partition mode 0=enable; 1=disable (default) TXD0[2]: Strap enable expansion port 0=enable; 1=disable (default) TXD0[3]: Strap enable BIST 0=init only; 1=enable (default) TXD1[2:0]: test function TXD1[3]: disable checking disable; 1=enable (default) Strap pins during reset: TXD2[2:0] device setting TXD2[3] strapped DRAM timing: 0=fast, normal (default) Strap during reset: TXD3[0] packet size selection: 1536 bytes, 1=1518 bytes (default) TXD3[1] Back pressure flow control enable: enable, disable (default) TXD3[3:2] aging timing selection: 64sec. sec. sec. disable (default) Strap during reset: TXD4[0] port trunking selection: enable, 1=disable (default) TXD4[1] port trunking selection: enable, 1=disable (default) TXD4[2] port trunking selection: enable, 1=disable (default) TXD4[3] port trunking selection: enable, 1=disable (default) Strap during reset: TXD5[1:0] broadcast filtering rate selection: packets/sec. packets/sec. packets/sec. disable (default) Strap pins during reset ports' operating mode: full duplex, 1=half duplex (default) Strap during reset: limit4 enabled, disabled (default) Strap during reset memory size selection: 2MB, (default) Strap pins during reset: MA7-0: Auto-negotiation enable port0: enabled (default), disabled
TXD1[3:0]
TXD2[3:0]
TXD3[3:0]
TXD4[3:0]
TXD5[1:0]
TXEN(7:0) MA(7:0)
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Absolute Maximum Ratings
Absolute Maximum Ratings 25°C Symbol Tstg Parameter Supply voltage Input voltage Output voltage Output Current Input protection diode current Output protection diode current Operating temperature Storage temperature Static Discharge voltage Min. -0.3 -0.3 -0.3 Max. 5.25 Unit Conditions
2000
Operating Conditions Symbol Cout Parameter Supply voltage Input voltage Output voltage Operating temperature Input Capacitance Output Capacitance Min. Max. Unit Conditions
Comments Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Electrical Characteristics (0°C<TA<70°C, 3.135<VCC<3.465, unless otherwise noted)
Symbol Parameter Input high voltage Input voltage Output high voltage Output voltage Input high current Input current Output high impedence current Operating Current Min. Max. Unit Conditions
Thermal Information Symbol Parameter Thermal resistance: junction ambient; ft/s airflow Thermal resistance: junction case; 0ft/s airflow Operating junction temperature Input Capacitance Value °C/W
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Electrical Characteristics Timing Waveforms
3.3V Symbol Signals SCLK SCLK RST* CAS*, RAS*,DWE*, SDQM, SCS*,SRAS*, SCAS* RXD8 RXD8 TXD8 Parameter System Clock frequency Rise/Fall time Reset pulse width Delay from SCLK rising falling edge Min. Max. Unit SCLK Conditions
Setup time Hold time Float delay Drive delay
Notes: related SCLK; RXD8 related RXDVCLK. related SCLK; TXD8 related TXENCLK. Delays, Setup, Hold times referred SCLK rising edge unless stated otherwise. outputs specified load. inputs outputs also refer signal behavior.
Output Delay from Rising Edge
SCLK
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Setup Hold time from Rising Edge
SCLK RXDVCLK
Drive Float Delay from Rising Edge
SCLK TXENCLK
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Package Information
208L Outline Dimensions
unit: inches/mm
Detail Seating Plane
DETAIL
Symbol
Dimensions inches 0.145 Max. 0.004 Min. 0.127 0.005 0.008 0.006 +0.002 -0.002 +0.004 -0.002 1.102 0.005 1.102 0.005 0.020 0.004 1.004 NOM. 1.185 NOM. 1.185 NOM. 1.205 0.012 1.205 0.012 0.019 0.008 0.051 0.008 0.004 Max.
Dimensions 3.68 Max. 0.10 Min. 3.23 0.13 0.20 0.15 +0.05 -0.05 +0.10 -0.05 28.00 0.13 28.00 0.13 0.50 0.10 25.5 NOM. 30.10 NOM. 30.10 NOM. 30.60 0.30 30.60 0.30 0.50 0.20 1.30 0.20 0.10 Max.
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Appendix: Cascade Three DM8108s 24-port Switch Illustration
SGRAM
SDRAM DM8108 DM8108
DRAM
SDRAM DM8108
DRAM
DRAM
rxd2 txd2 rxdvclk txenclk
rxd2 txd2 rxdvclk txenclk
rxd2 txd2 rxdvclk txenclk
Preliminary Version: DM8108-DS-P02 November 1999
DM8108
port 10/100M Fast Ethernet Switching Controller Ordering Information
Part Number DM8108 Count Package DAVICOM's terms conditions printed order acknowledgment govern sales DAVICOM. DAVICOM will bound terms inconsistent with these unless DAVICOM agrees otherwise writing. Acceptance buyer's orders shall based these terms.
Disclaimer
information appearing this publication believed accurate. Integrated circuits sold DAVICOM Semiconductor covered warranty patent indemnification provisions stipulated terms sale only. DAVICOM makes warranty, express, statutory, implied description regarding information this publication regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, DAVICOM MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. DAVICOM deserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing DAVICOM such applications. Please note that application circuits illustrated this document reference purposes only.
Company Overview
DAVICOM Semiconductor, Inc. develops manufactures integrated circuits integration into data communication products. mission design produce products that industry's best value Data, Audio, Video, Internet/Intranet applications. achieve this goal, have built organization that able develop chipsets response evolving technology requirements customers while still delivering products that meet their cost requirements.
Products
offer only products that satisfy high performance requirements which compatible with major hardware software standards. currently available soon released products based proprietary designs deliver high quality, high performance chipsets that comply with modem communication standards Ethernet networking standards.
Contact Windows
additional information about DAVICOM products, contact sales department Headquarters Hsin-chu Office: 7-2, Industry Scienced-based Industrial Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-579-8797 FAX: 886-3-579-8858 Taipei Sales Marketing Office: Lane 235, Bao-chiao Rd., Hsin-tien City, Taipei, Taiwan, R.O.C. TEL: 886-2-2915-3030 FAX: 886-2-2915-7575 Email: sales@davicom.com.tw
WARNING
Conditions beyond those listed absolute maximum destroy damage products. addition, conditions sustained periods near limits operating ranges will stress temporarily (and permanently) affect damage structure, performance and/or function.
Preliminary Version: DM8108-DS-P02 November 1999

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