EBE51AD8AGFA (64M words bits, Rank) Density: 512MB Organization w

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

EBE51AD8AGFA (64M words bits, Rank) Density: 512MB Organization w

Datasheet Thumbnail

Top Searches for this datasheet

512MB Registered DDR2 SDRAM DIMM
EBE51AD8AGFA (64M words bits, Rank)
Density: 512MB Organization words bits, rank Mounting pieces 512M bits DDR2 SDRAM sealed FBGA Package: 240-pin socket type dual line memory module (DIMM) height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) Power supply: 1.8V 0.1V Data rate: 667Mbps/533Mbps/400Mbps (max.) Four internal banks concurrent operation (components) Interface: SSTL_18 Burst lengths (BL): /CAS Latency (CL): Precharge: auto precharge option each burst access Refresh: auto-refresh, self-refresh Refresh cycles: 8192 cycles/64ms Average refresh period 7.8µs +85°C 3.9µs +85°C +95°C Operating case temperature range +95°C
Features
Double-data-rate architecture; data transfers clock cycle high-speed data transfer realized bits prefetch pipelined architecture Bi-directional differential data strobe (DQS /DQS) transmitted/received with data capturing data receiver edge-aligned with data READs; centeraligned with data WRITEs Differential clock inputs /CK) aligns transitions with transitions Commands entered each positive edge; data referenced both edges Data mask (DM) write data Posted /CAS programmable additive latency better command data efficiency Off-Chip-Driver Impedance Adjustment On-DieTermination better signal quality /DQS disabled single-ended Data Strobe operation piece clock driver, piece register driver piece serial EEPROM bits EEPROM) Presence Detect (PD)
Document E0864E11 (Ver. 1.1) Date Published February 2006 Japan Printed Japan URL: http://www.elpida.com Elpida Memory, Inc. 2006
EBE51AD8AGFA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed bin* (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) 240-pin DIMM (lead-free) Gold Contact
Part number EBE51AD8AGFA-6E-E EBE51AD8AGFA-5C-E EBE51AD8AGFA-4A-E
Package
Mounted devices EDE5108AGSE-6E-E EDE5108AGSE-6E-E EDE5108AGSE-5C-E EDE5108AGSE-6E-E EDE5108AGSE-5C-E EDE5108AGSE-4A-E
Note: Module /CAS latency component
Configurations
Front side
Back side
name VREF /DQS0 DQS0 /DQS1 DQS1 /RESET DQ10 DQ11 DQ16 DQ17
name Par_In /CAS DQ32 DQ33 /DQS4 DQS4 DQ34
name DM0/DQS9 /DQS9 DQ12 DQ13 DM1/DQS10 /DQS10 DQ14 DQ15 DQ20 DQ21 DM2/DQS11
name /CK0 /RAS /CS0 ODT0 DQ36 DQ37 DM4/DQS13 /DQS13 DQ38 DQ39
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
name /DQS2 DQS2 DQ18 DQ19 DQ24 DQ25 /DQS3 DQS3 DQ26 DQ27 /DQS8 DQS8 CKE0 /Err_Out name DQ35 DQ40 DQ41 /DQS5 DQS5 DQ42 DQ43 DQ48 DQ49 /DQS6 DQS6 DQ50 DQ51 DQ56 DQ57 /DQS7 DQS7 DQ58 DQ59 name /DQS11 DQ22 DQ23 DQ28 DQ29 DM3/DQS12 /DQS12 DQ30 DQ31 DM8/DQS17 /DQS17 name DQ44 DQ45 DM5/DQS14 /DQS14 DQ46 DQ47 DQ52 DQ53 DM6/DQS15 /DQS15 DQ54 DQ55 DQ60 DQ61 DM7/DQS16 /DQS16 DQ62 DQ63 VDDSPD
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Description
name (AP) BA0, DQ63 /RAS /CAS /CS0 CKE0 /CK0 DQS0 DQS17, /DQS0 /DQS17 VDDSPD VREF ODT0 /RESET Par_In*
Function Address input address Column address Auto precharge Bank select address Data input/output Check (Data input/output) address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input output data strobe Input mask Clock input serial Data input/output serial Serial address input Power internal circuit Power serial EEPROM Input reference voltage Ground control Reset (forces register inputs low) connection Parity address control Parity error found address control usable
/Err_Out*
Note: Reset connected both reset register. /Err_Out (Pin Par_In (Pin optional function check address command parity.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Serial Matrix
Byte Function described Number bytes utilized module manufacturer Total number bytes serial device Memory type Number address Number column address Number DIMM ranks Module data width Module data width continuation Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value Comments bytes bytes DDR2 SDRAM SSTL 1.8V 3.0ns*
Voltage interface level this assembly SDRAM cycle time,
3.75ns* 5.0ns*
SDRAM access from clock (tAC)
0.45ns* 0.5ns* 0.6ns*
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width Reserved SDRAM device attributes: Burst length supported SDRAM device attributes: Number banks SDRAM device SDRAM device attributes: /CAS latency DIMM Mechanical Characteristics DIMM type information SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time -6E,
ECC, Address/ Command Parity 7.8µs 4.00mm max. Registered Normal Weak Driver Support 3.75ns* 5.0ns* 0.5ns* 0.6ns* 5.0ns* 0.6ns* 15ns
Maximum data access time (tAC) from clock -6E,
Minimum clock cycle time
Maximum data access time (tAC) from clock Minimum precharge time (tRP)
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Byte
Function described Minimum active active delay (tRRD) Minimum /RAS /CAS delay (tRCD) Minimum active precharge time (tRAS) -6E,
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
value
Comments 7.5ns 15ns 45ns 40ns 512M byte 0.20ns* 0.25ns* 0.35ns* 0.28ns* 0.38ns* 0.48ns* 0.10ns* 0.15ns* 0.18ns* 0.23ns* 0.28ns* 15ns*
Module rank density Address command setup time before clock (tIS)
Address command hold time after clock (tIH)
Data input setup time before clock (tDS) -6E, Data input hold time after clock (tDH)
Write recovery time (tWR) Internal write read command delay (tWTR) -6E, Internal read precharge command delay (tRTP)
7.5ns* 10ns*
7.5ns*
Memory analysis probe characteristics Extension Byte Active command period (tRC) -6E, Auto refresh active/ Auto refresh command cycle (tRFC) SDRAM cycle max. (tCK max.) Dout skew
Undefined 60ns* 55ns*
105ns* 8ns*
0.24ns* 0.30ns* 0.35ns* 0.34ns* 0.40ns* 0.45ns* 15µs
Data hold skew (tQHS)
relock time
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Byte
Function described Revision Checksum bytes
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
value
Comments Rev.
Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturer's JEDEC code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number
Continuation code Elpida Memory
(ASCII-8bit code) (Space) Initial (Space) Year code (BCD) Week code (BCD)
Module part number
Module part number Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacture specific data
Note: These specifications defined based component specification, module.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Block Diagram
/RCS0 /DQS0 DQS0 /DQS9 DM0/DQS9 /DQS1 DQS1 /DQS10 DM0/DQS10 DQ15 /DQS2 DQS2 /DQS11 DM2/DQS11 DQ16 DQ23 /DQS3 DQS3 /DQS12 DM3/DQS12 DQ24 DQ31 /DQS8 DQS8 /DQS17 DM0/DQS17 /DQS /RDQS /RDQS /DQS /RDQS RDQS DQS7 /DQS16 DM0/DQS16 DQ56 DQ63 /CSDQS /DQS /RDQS /RDQS /DQS7 /DQS /RDQS RDQS /DQS /RDQS RDQS DQS5 /DQS14 DM5/DQS14 DQ40 DQ47 /DQS6 DQS6 /DQS15 DM0/DQS15 DQ48 DQ55 /DQS /RDQS /RDQS /DQS /RDQS /RDQS /DQS5 /DQS /RDQS RDQS /DQS4 DQS4 /DQS13 DM4/DQS13 DQ32 DQ39 /DQS /RDQS RDQS
Serial
VDDSPD VREF
Serial
/CS0*2 /RAS /CAS CKE0 ODT0
/RCS0 /CS: SDRAMs RBA0 RBA1 BA1: SDRAMs RA13 A13: SDRAMs /RRAS /RAS: SDRAMs /RCAS /CAS: SDRAMs RCKE0 CKE: SDRAMs /RWE /WE: SDRAMs RODT0 ODT0: SDRAMs
512M bits DDR2 SDRAM bits EEPROM PLL: CUA877 Register: SSTUA32866
Signals Address Command Parity Function Par_In 100k Register PAR_IN /QERR /Err_Out
/RST /RESET PCK7
/PCK7 Notes: wiring changed within byte. /CS0 connects D/CS connects /CSR register.
/CK0 /RESET
PCK0 PCK6, PCK8, PCK9 SDRAMs /PCK0 /PCK6, /PCK8, /PCK9 /CK: SDRAMs PCK7 register /PCK7 /CK: register
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Differential Clock Wiring (CK0, /CK0)
(nominal)
OUT1
SDRAM
/CK0
Register
Feedback
OUT'N'
Feedback
Notes: clock delay from input clock input SDRAM register willl (nominal). Input, output feedback clock lines terminated from line line shown, from line ground. Only output shown output type. additional outputs will wired similar manner. Termination resistors feedback path clocks located close input possible.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Electrical voltages referenced (GND). Absolute Maximum Ratings
Parameter Voltage relative Supply voltage relative Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol Tstg Value -0.5 +2.3 -0.5 +2.3 +100 Unit Note
Note: DDR2 SDRAM component specification. Supporting +85°C being able extend +95°C with doubling auto-refresh commands frequency 32ms period (tREFI 3.9µs) higher temperature self-refresh entry control EMRS required. Caution Exposing device stress above those listed Absolute Maximum Ratings could cause permanent damage. device meant operated under conditions outside limits described operational section this specification. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Operating Conditions +85°C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VDDSPD Input reference voltage Termination voltage input logic high input input logic high -5C, input -5C, VREF (DC) (DC) (AC) (AC) (AC) (AC) min. 0.49 VDDQ VREF 0.04 VREF 0.125 -0.3 VREF 0.200 VREF 0.250 typ. max. Unit Notes
0.50 VDDQ 0.51 VDDQ VREF VREF 0.04 VDDQ VREF 0.125 VREF 0.200 VREF 0.250
Notes: value VREF selected user provide optimum noise margin system. Typically value VREF expected about VDDQ transmitting device VREF expected track variations VDDQ. Peak peak noise VREF exceed VREF (DC). transmitting device must track VREF receiving device. VDDQ must equal VDD.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Characteristics +85°C, 1.8V 0.1V,
Parameter Symbol Grade max. 1570 1480 1310 Unit Test condition bank; (IDD), (IDD), tRAS tRAS min.(IDD); between valid commands; Address inputs SWITCHING; Data inputs SWITCHING bank; IOUT 0mA; CL(IDD), (IDD), (IDD), tRAS tRAS min.(IDD); tRCD tRCD (IDD); between valid commands; Address inputs SWITCHING; Data pattern same IDD4W banks idle; (IDD); Other control address inputs STABLE; Data inputs FLOATING banks idle; (IDD); Other control address inputs STABLE; Data inputs FLOATING banks idle; (IDD);CKE Other control address inputs SWITCHING; Data inputs SWITCHING banks open; (IDD); Other control address inputs STABLE; Data inputs FLOATING Fast Exit MRS(12)
Operating current (ACT-PRE)
IDD0
Operating current (ACT-READ-PRE)
IDD1
1760 1680 1470
Precharge power-down standby current
IDD2P
Precharge quiet standby current
IDD2Q
Idle standby current
IDD2N
IDD3P-F Active power-down standby current IDD3P-S
Slow Exit MRS(12)
Active standby current
IDD3N
1160 1100
Operating current (Burst read operating)
IDD4R
2660 2270 1830
Operating current (Burst write operating)
IDD4W
2570 2270 1830
banks open; (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING banks open, continuous burst reads, IOUT 0mA; CL(IDD), (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Address inputs SWITCHING; Data pattern same IDD4W banks open, continuous burst writes; CL(IDD), (IDD), tRAS tRAS max.(IDD), (IDD); between valid commands; Address inputs SWITCHING; Data inputs SWITCHING
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Parameter
Symbol
Grade
max. 2950 2730 2510
Unit
Test condition (IDD); Refresh command every tRFC (IDD) interval; between valid commands; Other control address inputs SWITCHING; Data inputs SWITCHING Self Refresh Mode; 0.2V; Other control address inputs FLOATING; Data inputs FLOATING bank interleaving reads, IOUT 0mA; CL(IDD), tRCD (IDD) (IDD); (IDD), (IDD), tRRD tRRD(IDD), tRCD (IDD); between valid commands; Address inputs STABLE during DESELECTs; Data pattern same IDD4W;
Auto-refresh current
IDD5
Self-refresh current
IDD6
Operating current (Bank interleaving)
IDD7
3720 3610 3330
Notes:
specifications tested after device properly initialized. Input slew rate specified Input Test Condition. parameters specified with disabled. Data consists DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, /UDQS. values must with combinations EMRS bits Definitions defined (AC) (max.) defined (AC) (min.) STABLE defined inputs stable level FLOATING defined inputs VREF VDDQ/2 SWITCHING defined inputs changing between every other clock cycle (once clocks) address control signals, inputs changing between every other data transfer (once clock) signals including masks strobes. Refer Timing Test Conditions.
Timing Test Conditions purposes testing, following parameters utilized.
DDR2-667 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD) 5-5-5 70000 DDR2-533 4-4-4 3.75 70000 DDR2-400 3-3-3 70000 Unit
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol Value 0.603 0.603 VDDQ +13.4 -13.4 Unit Notes VDDQ VOUT
Minimum required output pull-up under test load Maximum required output pull-down under test load Output timing measurement reference level VOTR Output minimum sink current Output minimum source current
Notes:
VDDQ device under test referenced. VDDQ 1.7V; VOUT 1.42V. VDDQ 1.7V; VOUT 0.28V. value VREF applied receiving device expected VTT. After calibration 25°C, VDDQ 1.8V.
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter differential input voltage differential cross point voltage differential cross point voltage Symbol (AC) (AC) (AC) min. VDDQ 0.175 VDDQ 0.125 max. VDDQ VDDQ 0.175 VDDQ 0.125 Unit Notes
Notes: VID(AC) specifies input differential voltage |VTR -VCP| required switching, where true input signal (such DQS, LDQS UDQS) complementary input signal (such /CK, /DQS, /LDQS /UDQS). minimum value equal VIH(AC) VIL(AC). typical value VIX(AC) expected about VDDQ transmitting device VIX(AC) expected track variations VDDQ VIX(AC) indicates voltage which differential input signals must cross. typical value VOX(AC) expected about VDDQ transmitting device VOX(AC) expected track variations VDDQ VOX(AC) indicates voltage which differential output signals must cross.
VDDQ
VSSQ
Crossing point
Differential Signal Levels*1,
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Electrical Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter effective impedance value EMRS (A6, effective impedance value EMRS (A6, effective impedance value EMRS (A6, Deviation with respect VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) min. typ. max. Unit Note
Note: Test condition measurements. Measurement Definition Rtt(eff) Apply (AC) (AC) test separately, then measure current I(VIH(AC)) I(VIL(AC)) respectively. VIH(AC), VDDQ values defined SSTL_18.
Rtt(eff)
VIH(AC) VIL(AC) I(VIH(AC)) I(VIL(AC))
Measurement Definition Measure voltage (VM) test (midpoint) with load.
VDDQ
100%
Default Characteristics +85°C, VDD, VDDQ 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Output impedance Pull-up pull-down mismatch Output slew rate min. 12.6 typ. max. 23.4 Unit V/ns Notes
Notes: Impedance measurement condition output source current: VDDQ 1.7V; VOUT 1420mV; (VOUT-VDDQ)/IOH must less than 23.4 values VOUT between VDDQ VDDQ-280mV. Impedance measurement condition output sink current: VDDQ 1.7V; VOUT 280mV; VOUT/IOL must less than 23.4 values VOUT between 280mV. Mismatch absolute value between pull pull down, both measured same temperature voltage. Slew rate measured from VIL(AC) VIH(AC). absolute value slew rate measured from equal greater than slew rate measured from This guaranteed design characterization.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Capacitance 25°C, 1.8V 0.1V)
Parameter Input capacitance Input capacitance Data input/output capacitance -5C, Symbol Pins Address, /RAS, /CAS, /WE, /CS, CKE, DQS, /DQS, min. max. Unit Notes
Notes: Register component specification. component specification. DDR2 SDRAM component specification.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Characteristics +85°C, VDD, VDDQ 1.8V 0.1V, (DDR2 SDRAM Component Specification)
Frequency (Mbps) Parameter /CAS latency Active read write command delay Precharge command period Symbol tRCD min. max. +450 +400 0.55 0.55 8000 max. max. min. -500 -450 0.45 0.45 min. (tCL, tCH) 3750 0.35 min. max. +500 +450 0.55 0.55 8000 max. max. min. -600 -500 0.45 0.45 min. (tCL, tCH) 5000 0.35 min. max. +600 +500 0.55 0.55 8000 max. max. Unit Notes
Active active/auto refresh command time output access time from -450 output access time from tDQSCK -400 high-level width low-level width half period Clock cycle time input hold time 0.45 0.45 min. (tCL, tCH) 3000 0.35 min.
input setup time Control Address input pulse width each input input pulse width each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew associated signals hold skew factor DQ/DQS output hold time from Write command first latching transition input high pulse width input pulse width tIPW tDIPW tDQSQ tQHS tDQSS tDQSH tDQSL
tQHS 0.25 0.35 0.35 0.35 0.25
tQHS 0.25 0.35 0.35 0.35 0.25
tQHS 0.25 0.35 0.35 0.35 0.25
falling edge setup tDSS time falling edge hold time tDSH from Mode register command tMRD cycle time Write postamble Write preamble Address control input hold time Address control input setup time Read preamble Read postamble tWPST tWPRE tRPRE tRPST
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Frequency (Mbps) Parameter Active precharge command Active auto-precharge delay Active bank active bank command period Write recovery time Auto precharge write recovery precharge time Internal write read command delay Internal read precharge command delay Exit self refresh non-read command Exit self refresh read command Exit precharge power down non-read command Exit active power down read command Exit active power down read command (slow exit/low power mode) minimum pulse width (high pulse width) Output impedance test driver delay Auto refresh active/auto refresh command time Average periodic refresh interval (0°C +85°C) (+85°C +95°C) Symbol tRAS tRAP tRRD tDAL tWTR tRTP tXSNR tXSRD tXARD min. tRCD min. max. 70000 min. tRCD min. max. 70000 min. tRCD min. max. 70000 Unit Notes
(tWR/tCK)+ (tRP/tCK) tRFC
(tWR/tCK)+ (tRP/tCK) tRFC
(tWR/tCK)+ (tRP/tCK) tRFC
tXARDS tCKE tOIT tRFC tREFI tREFI
Minimum time clocks remains after tDELAY asynchronously drops
Notes:
each terms above, already integer, round next higher integer. Additive Latency. defines which active power down exit timing applied. figures Input Waveform Timing referenced from input signal crossing VIH(AC) level rising signal VIL(AC) falling signal applied device under test. figures Input Waveform Timing referenced from input signal crossing VIH(DC) level rising signal VIL(DC) falling signal applied device under test.
/DQS
VDDQ (AC)(min.) (DC)(min.) VREF (DC)(max.) (AC)(max.)
VDDQ (AC)(min.) (DC)(min.) VREF (DC)(max.) (AC)(max.)
Input Waveform Timing (tDS, tDH)
Input Waveform Timing (tIS, tIH)
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter turn-on delay turn-on -5C, turn-on (power down mode) turn-off delay turn-off turn-off (power down mode) power down entry latency power down exit latency Symbol tAOND tAON tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min. tAC(min) tAC(min) tAC(min) 2000 tAC(min) tAC(min) 2000 max. tAC(max) tAC(max) 1000 2tCK tAC(max) 1000 tAC(max) 2.5tCK tAC(max) 1000 Unit Notes
Notes: turn time when device leaves high impedance resistance begins turn turn time when resistance fully Both measured from tAOND. turn time when device starts turn resistance. turn time when high impedance. Both measured from tAOFD.
Input Test Conditions
Parameter Input reference voltage Input signal maximum peak peak swing Input signal maximum slew rate Symbol VREF VSWING(max.) SLEW Value VDDQ Unit V/ns Notes
Notes: Input waveform timing referenced input signal crossing through VREF level applied device under test. input signal minimum slew rate maintained over range from VIL(DC) (max.) VIH(AC) (min.) rising edges range from VIH(DC) (min.) VIL(AC) (max.) falling edges shown below figure. timings referenced with input waveforms switching from VIL(AC) VIH(AC) positive transitions VIH(AC) VIL(AC) negative transitions.
Start falling edge input timing Start rising edge input timing
VDDQ (AC)(min.) (DC)(min.)
VSWING(max.)
VREF (DC)(max.) (AC)(max.)
Falling slew (DC)(min.) (AC)(max.)
Rising slew
(AC) min. (DC)(max.)
Input Test Signal Wave forms
Measurement point
Output Load
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Functions
(input pin) master clock inputs. inputs except DMs, DQSs referred cross point rising edge VREF level. When read operation, DQSs referred cross point /CK. When write operation, referred cross point VREF level. DQSs write operation referred cross point /CK. (input pin) When low, commands data input. When high, inputs ignored. However, internal operations (bank active, burst operations, etc.) held. /RAS, /CAS, (input pins) These pins define operating commands (read, write, etc.) depending combinations their voltage levels. "Command operation". (input pins) address (AX0 AX13) determined level cross point rising edge VREF level bank active command cycle. Column address (AY0 AY9) loaded cross point rising edge VREF level read write command cycle. This column address becomes starting address burst operation. (AP) (input pin) defines precharge mode when precharge command, read command write command issued. high when precharge command issued, banks precharged. when precharge command issued, only bank that selected BA1, precharged. high when read write command, auto-precharge function enabled. While low, auto-precharge function disabled. BA0, (input pin) BA0, bank select signals (BA). memory array divided into bank bank bank bank (See Bank Select Signal Table) [Bank Select Signal Table]
Bank Bank Bank Bank
Remark: VIH. VIL. (input pin) controls power down self-refresh. power down self-refresh commands entered when driven exited when resumes high. level must kept cycle least, that changes cross point rising edge VREF level with proper setup time tIS, next rising edge level must kept with proper hold time tIH. (input output pins) Data input output from these pins. (input output pin) /DQS provide read data strobes output) write data strobes input).
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
(input pins) reference signal data input mask function. sampled cross point /DQS. function will disabled when RDQS (DQS9 toDQS17 /DQS9 /DQS17) function enabled EMRS. (power supply pins) 1.8V applied. (VDD internal circuit.) VDDSPD (power supply pin) 1.8V applied (For serial EEPROM). (power supply pin) Ground connected. /RESET(input pin) LVCMOS reset input. When /RESET Low, registers reset. Par_IN (Parity input pin) Parity address control bus. /Err_Out (Error output pin) Parity error found address control bus.
Detailed Operation Part Timing Waveforms
Refer EDE5104AGSE, EDE5108AGSE datasheet (E0715E). DIMM /CAS latency component registered type.
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
Physical Outline
Unit:
4.00 (DATUM -A-)
Component area (Front)
63.00 133.35 55.00
1.27 0.10
10.00
17.80
4.00
Component area (Back)
4.00
FULL
3.00
Detail
2.50 0.20
Detail 1.00 4.00
0.20 0.15
(DATUM -A-)
2.50 FULL
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
Preliminary Data Sheet E0864E11 (Ver. 1.1)
30.00
EBE51AD8AGFA
CAUTION HANDLING MEMORY MODULES
When handling inserting memory modules, sure touch components modules, such memory ICs, chip capacitors chip resistors. necessary avoid undue mechanical stress these components prevent damaging them. particular, push module cover drop modules order protect from mechanical defects, which would electrical defects. When re-packing memory modules, sure modules touching each other. Modules contact with other modules cause excessive mechanical stress, which damage modules.
MDE0202
NOTES CMOS DEVICES
PRECAUTION AGAINST DEVICES
Exposing devices strong electric field cause destruction gate oxide ultimately degrade devices operation. Steps must taken stop generation static electricity much possible, quickly dissipate when once occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS DEVICES
connection CMOS devices input pins cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. unused pins must handled accordance with related specifications.
STATUS BEFORE INITIALIZATION DEVICES
Power-on does necessarily define initial status devices. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee output levels, settings contents registers. devices initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
CME0107
Preliminary Data Sheet E0864E11 (Ver. 1.1)
EBE51AD8AGFA
information this document subject change without notice. Before using this document, confirm that this latest version.
part this document copied reproduced form means without prior written consent Elpida Memory, Inc. Elpida Memory, Inc. does assume liability infringement intellectual property rights (including limited patents, copyrights, circuit layout licenses) Elpida Memory, Inc. third parties arising from products information listed this document. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights Elpida Memory, Inc. others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. Elpida Memory, Inc. assumes responsibility losses incurred customers third parties arising from these circuits, software information. [Product applications] Elpida Memory, Inc. makes every attempt ensure that products high quality reliability. However, users instructed contact Elpida Memory's sales office before using product aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment life support, other such application which especially high quality reliability demanded where failure malfunction directly threaten human life cause risk bodily injury. [Product usage] Design your application that product used within ranges conditions guaranteed Elpida Memory, Inc., including maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions other related characteristics. Elpida Memory, Inc. bears responsibility failure damage when product used beyond guaranteed ranges conditions. Even within guaranteed ranges conditions, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Elpida Memory, Inc. products does cause bodily injury, fire other consequential damage operation Elpida Memory, Inc. product. [Usage environment] This product designed resistant electromagnetic waves radiation. This product must used non-condensing environment. export products technology described this document that controlled Foreign Exchange Foreign Trade Japan, must follow necessary procedures accordance with relevant laws regulations Japan. Also, export products/technology controlled U.S. export control regulations, another country's export control laws regulations, must follow necessary procedures accordance with such laws regulations. these products/technology sold, leased, transferred third party, third party granted license these products, that third party must made aware that they responsible compliance with relevant laws regulations.
M01E0107
Preliminary Data Sheet E0864E11 (Ver. 1.1)

EBE51AD8AGFA (64M words bits, Rank) Density: 512MB Organization w

Top Searches for this datasheet

Other recent searches