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AIP-8d
Channel Analogue Input Board
AIP-8d Document Part Document Reference Document Issue Level Manual covers PCBs identified 0127-1004.doc AIP-8d\.\0127-1004.doc AIP-8d Rev.
rights reserved. part this publication reproduced, stored retrieval system, transmitted, form means, electronic, mechanical, photocopied, recorded otherwise, without prior permission, writing, from publisher. permission contact Blue Chip Technology. Information offered this manual correct time printing. Blue Chip Technology accepts responsibility inaccuracies. This information subject change without notice. trademarks registered names acknowledged.
Blue Chip Technology Ltd. Chowley Oak, Tattenhall Chester, Cheshire 9EX. Telephone 01829 5772000 Facsimile 01829 772001.
Amendment History
Issue Level
Issue Date 10/08/95 19/12/95
Author
Amendment Details First approved issue, front sheet. Addition information Technical Section. Errors corrected. Earlier part 127-036. Filename .\User_g.doc. window front cover logo.
07/05/98
Contents
INTRODUCTION. ABOUT MANUAL. CHAPTER Installing AIP-8d. Base Address. Interrupt Selection. Selecting Range. Fitting Card CHAPTER Making Right Connections. Input Mode. Input Noise. Typical Connection AIP-8d Analogue Connector (25-Way D-type Plug). CHAPTER Hardware Description. µPD71054. Timer Modes. Mapping Function Control Register. Starting Conversions. Pacer Conversions. CHAPTER Technical Specifications. APPENDIX NUMBERING SYSTEMS Binary Hexadecimal Numbers Base Address Selection APPENDIX MAPS. PC/XT/AT Address PC/XT Interrupt PC/AT Interrupt Channels.
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Introduction
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INTRODUCTION
Thank purchasing AIP-8d analogue input card. card provides user with eight channels analogue inputs. inputs range from ±50mV volts, volts full scale. card features user selectable base address, interrupt source, interrupt level on-board timer. timer used pacer clock control conversion cycles.
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About Manual
ABOUT MANUAL
This manual organised into four chapters appendices. Each chapter covers different aspect using AIP-8d. order best results from product, user urged read chapters, paying particular note Chapter which deals with initial installation card. appendices used reference time. Chapter Explains configure card your computer user selectable links. Details connections from card provides information regarding type signals that card suitable with. Gives details card's address mapping internal register details allowing user write custom software control card. Presents card's technical specification. this section determine card's suitability particular application. Gives brief introduction Binary Hexadecimal numbering systems those unfamiliar with concepts. Lists IBM-PC address map, interrupt allocations should used along with Chapter when first installing card.
Chapter
Chapter
Chapter
Appendix
Appendix
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Chapter
Installation
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CHAPTER Installing AIP-8d
Before installing card into your computer system, there number user-configurable links that must set. positioning these links will depend upon computer system into which card being fitted. Before fitting links card please read next section. unfamiliar with binary hexadecimal systems primer included appendix.
Base Address
correct communication between card host computer, range addresses that card will occupy must base address represents first address that card will use. AIP-8d requires total addresses (including base address) correct operation. Blue Chip Technology boards factory default address hex. Check ensure that base address full range addresses free use. addresses free another range must chosen. guide, please information contained appendix assist choosing suitable base address. sure refer your computer system handbook information relating other peripheral devices possibly already installed (additional communications card, parallel ports games ports etc). addresses available then proceed follows: Locate header pins (JP1). These pins marked "BASE" start with pair pins marked with "08H". This pair pins represents LOWEST single base address selection. Subsequent pins represent addresses increasing value. HIGHEST single base address link hex.
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Installation
Chapter
select address, link position must left OPEN. Placing link pair pins DE-SELECTS that particular address. Example: select base address 300, links follows:
BASE ADDRESS (JP1)
base address selected
Figure Example Base Address Selection
Interrupt Selection
part communication link between AIP-8d host computer, interrupt signal occur whenever valid data available user. interrupts essential greatly enhances functionality card. order this mode data transfer operate correctly, user must select INTERRUPT CHANNEL card use. with selection base addresses, chosen interrupt channel must free use. appendix used identify Interrupt channels that normally already most systems which ones will probably free use. AIP-8d allows interrupt selections from Check that Interrupt channel free use. sure refer your computer system handbook information relating other peripheral devices possibly already installed (additional communications cards, parallel ports games ports etc.). interrupt channel chosen available AIP-8d then card Locate header pins labelled "JP2". These pins marked "IRQ" start with Interrupt Signal pins marked with rrow.
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Installation
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select interrupt place link pair pins corresponding chosen Interrupt Signal. other pins must left OPEN. Example: select Interrupt Signal IRQ-5 links follows:-
INTERRUPT (JP2)
INTERRUPT SELECTED IRQ5
Figure Example Interrupt Signal Selection
Selecting Range
full scale measurement range analogue inputs combination user configurable links. mode operation A-D. table below determine jumper settings required input scaling range.
Gain Setting (J4) volts volts volts volts volts volts volts volts volts Full Scale Range volts volts volts 500mV volt ±500 +50mV +100mV
Figure Configuring
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Installation
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SETTINGS (JP4)
VOLTS
VOLTS
VOLTS
SETTINGS (JP3)
GAIN
GAIN
GAIN
Figure Setting Input Gain Configuration
Fitting Card
Once links have been set, card installed into host computer. Ensure that power turned follow manufacturer's instructions opening computer. Locate free expansion slot machines plug card firmly into Screw bracket place reassemble computer. NOTE: avoid interference from other cards computer, possible locate card away from "noisy" cards such hard disk controllers network cards.
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Chapter
Making Right Connections
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CHAPTER Making Right Connections
This chapter explains input configuration AIP-8d, provides typical connection examples gives pin-outs analogue connector.
Input Mode
input circuitry AIP-8d configurable handle signals ranging from ±50mV Volts bipolar modes Volts uni-polar mode. modes single ended. single ended input configuration measures voltage applied input with reference signal ground connection. This ground connection common input signals. With this input configuration maximum voltage range that card measure volts.
Input Noise
When using 50mV full scale, special care should exercised sheilding input cables against spurious noise. converter used AIP-8d extremely fast, requiring mere complete conversion. addition 50mV range, sensitivity input terminals will approximately 12µV bit. card therefore very susceptible interference, noisy environment within host computer some noise lower order bits will present acquired signal. This noise will present, lesser degree, ranges high speed A-D.
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Making Right Connections
Chapter
Typical Connection AIP-8d
voltage source
single ended input channel connector
Figure Typical Connection KFA8I
Analogue Connector (25-Way D-type Plug)
This connector located front card protrudes through rear bracket. analogue inputs presented this connector.
SIGNAL Channel Input Channel Input Channel Input Channel Input Channel Input Channel Input Channel Input Channel Input Connection Connection Digital Grid Connection Analogue Grid SIGNAL Analogue Grid Analogue Grid Analogue Grid Analogue Grid Analogue Grid Analogue Grid Analogue Grid Analogue Grid Connection Digital Grid Conversion Start/Stop Digital Grid
Conversion Start/Stop Signal Input: enables conversion process disables conversions
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Chapter
Hardware Description
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CHAPTER Hardware Description
This chapter presents details AIP-8d mapping along with internal register details. Details registers µPD71054 timer chip given detail, only brief functional description provided. full details, user referred manufacturer's data book.
µPD71054
µPD71054 timer chip contains three independent counters which operated variety modes. Presented here brief summary some modes possible programming timers internal registers. There five basic modes operation each providing different output signal from "Tout" device. AIP-8d timers connected series provide longer delay period.
Timer Modes
following modes operation possible programming control register within µPD71054 MODE When programme, output will LOW. When counter decrements from value loaded into count registers zero, output will HIGH. will remain high until count re-programmed into count registers. MODE When count registers programmed, output will HIGH. When going signal applied gate input, count starts output will immediately fall LOW. After time period programmed into count registers elapsed, output will return HIGH.
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MODE This mode operates frequency divider with roughly mark-space ratio. When programme output will toggle HIGH alternatively each. count value programmed number then counter will reach zero before output toggles. MODE This mode similar Mode output pulses when count reaches zero instead MODE Mode except count sequence triggered gate line.
Mapping
Address Base Base Base Base Base Base Base Base Function Timer Count Register Timer Count Register Timer Count Register Timer Control Register Function Control Register Start Convert Read Data Status Register
Figure Mapping AIP-8d
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Function Control Register
This register controls various aspects AIP-8d operations such input channel selection, conversion mode etc. Bits
Selects Channel Channel Channel Channel Channel Channel Channel Channel Used Used Used Used Used Used Used Used None
Don't care Analogue Input Channel Selection Bits used. It's programmed value does affect operation. controls Pacer Clock. clock disabled enabled when HIGH. must high order program timer with values run. Setting this prevents conversions from occurring also stops timer from being loaded with values.
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determines whether input channels automatically scanned data conversions occur whether channel selection software command. automatic mode, conversion occurs every eighth pacer clock "tick" followed generation interrupt from data ready signal. this point host computer reads data from A-D. read operation that selects next channel ready next start convert signal from pacer. Setting selects "manual" software selection input channel, setting HIGH selects automatic channel selection.
NOTE: When using pacer timer conversions auto scanning, interrupt service routine data reading sub-routine must execute less time than period between pacer "ticks". selects whether conversions should occur automatically ecert pacer clock ticks only when commanded software. Setting selects conversion using pacer clock. Setting HIGH selects software controlled conversions. software signal required start conversion write Base Address Upon receipt write signal, bits pacer clock allowed occur complete conversion cycle.
Starting Conversions
conversions started either pacer clock software WRITE Base Address Pacer driven conversion straightforward provided that data service routine MUST completed within pacer clock timer periods. software start conversions, also necessary program timer. data timer loaded with function control register high. specific details programming timer device AIP-8d next section.
Pacer Conversions
internal logic AIP-8d provides conversion result every ticks pacer clock. When working sampling rates important remember this detail this program pacer clock times desired sampling rate.
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Start Convert
When issuing start convert signals note that from point issuing start convert command point where valid data available pacer clock periods. start convert signal this mode enables burst pacer clocks drive conversion cycle. When using this mode therefore, pacer clock time values should short possible avoid unduly long times between start convert signal data ready flag.
Reading
Once conversion cycle complete user choice signals flag that data ready read from card. Interrupts Using interrupt line represents most efficient acquire data from card since controlling software required remain loop reading card waiting data become available use. interrupt facility, interrupt handler routine must written installed prior running main acquisition software. Data Ready Flag When valid data, "Data Ready Flag" goes logic condition. flag will stay until both bytes value have been read whereupon will return high. This polled order determine when data should read. This method operation ties machine most time looking data ready flag change state.
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Data Format
resolution device although card occupies only slot. Because this, reads required retrieve data. Both reads same address Base Address provide value BYTE first followed HIGH BYTE. necessary mask upper nibble high byte since this always returns value zero.
Channel Scanning
When scanning through input channels, there limit quickly channel selected then read. allow settling times various components, scan rate faster than 12µS recommended. scan rate quick, data values returned will expected since input will have time settle proper value before starts converting.
Programming Pacer Clock
Irrespective whether conversions driven solely pacer command, µPD71054 timer must programmed. timer chip driven 4MHz clock signal which gives timer resolution 250nS. most timer modes, however, minimum count period clock cycles. This means effective minimum time single counter 500nS. AIP-8d, three timers cascaded such that only first timer (Timer chain from 4MHz clock. Timer clock input signal output from Timer Timer clock input signal output from Timer minimum time period therefore pacer clock system whole 2µS, with maximum being 2.23 years.
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calculate time period pacer clock, work each three timer sections individually, taking clock value each output from preceding one.
Timer Timer Timer [CLOCK MHz)/n] [CLOCK(out from Timer 0)/n] [CLOCK(out from Timer 1)/n] [CLOCK(out from Timer 1)/n] seconds decimal value loaded counter
pacer clock value value obtained Timer calculation. sampling TIME system times calculated time period pacer. NOTE: pacer rate less than permitted since this approaches conversion time A-D.
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Technical Specifications
Chapter
CHAPTER Technical Specifications ANALOGUE INPUTS
Number Analogue Input Channels Voltage Input Range (Single Ended) From Volts Volts x10, x100 12µS
Programmable Gains System Conversion Time: Conversion Time: Resolution Measurement Accuracy Range +10V Range Range Input Common Mode Range Data Transfer Modes Data Ready Flags Interrupt Channels
0.1% Counts 0.1% Counts 0.1% Counts Volts Port Interrupt Polling IRQ-2
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TIMERS
Number Timer Channels Timer Timer Timer Feeds Timer Feeds Timer Pacer Conversions TIMER (Output Feeds TIMER Clock) 250nS 500nS 16.384mS 500nS 32.768mS 65.535mS
Timer Resolution Minimum Time Interval Maximum Time Interval Timer Resolution, (Cascaded from TIMER Minimum Time Interval Maximum Time Interval Timer Resolution, (Cascade From Timer Minimum Time Interval Maximum Time Interval Combined Timer Limits (Time Between Start Converts) Minimum Time Period Maximum Time Period
2.23 years
BOARD CONNECTIONS Analogue Input Signals
male D-type 8-bit
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Electromagnetic Compatibility (EMC)
This product meets requirements European Directive (89/336/EEC) eligible bear mark. been assessed operating Blue Chip Technology Icon industrial However, because board installed variety computers, certain conditions have applied ensure that compatibility maintained. meets requirements industrial environment Class product) subject those conditions. board must installed computer system which provides screening suitable industrial environment. recommendations made computer system manufacturer/supplier must complied with regarding earthing installation boards. board must installed with backplate securely screwed chassis computer ensure good metal-to-metal (i.e. earth) contact. Most problems caused external cabling boards. With analogue boards particular attention must paid this aspect. imperative that external cabling board totally screened, that screen cable connects metal bracket board hence earth. recommended that round screened cables with braided wire screen used preference those with foil screen drain wire. metal connector shells which connect around full circumference screen; they superior those which earth screen simple "pig-tail". Standard ribbon cable will adequate unless contained wholly within cabinetry housing industrial difficulty with interference experienced cable should also fitted with ferrite clamp close possible connector. preferred type Chomerics clip-on style, type H8FE-1004-AS. recommended that cables kept short possible, particularly when dealing with level signals.
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Ensure that screen external cable bonded good earth remote cable. Failure observe these recommendations invalidate compliance.
Warning This Class product. domestic environment this product cause radio interference which case user required take adequate measures.
Specification Blue Chip Technology Icon industrial fitted with this card meets following specification: Emissions 55022:1995 Radiated Class Conducted Class 50082-1:1992 incorporating: Electrostatic Discharge Radio Frequency Susceptibility Fast Burst Transients
Immunity
801-2:1984 Performance Criteria 801-3:1984 Performance Criteria 801-4:1988 Performance Criteria
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Numbering Systems
Appendix
APPENDIX NUMBERING SYSTEMS Binary Hexadecimal Numbers
normal numbering system termed DECIMAL because there possible digits single column numbers. Decimal numbers also referred numbers having Base When counting, numbers increment units column from next increment resets units column carries over into next column. This indicates that there been full (the base number) counts units column. second column therefore termed "tens" column. more convenient when programming number system that provides clearer picture hardware operational register level. most common number systems used BINARY HEXADECIMAL. These systems provide alternative representation decimal numbers. binary number there only possible values result binary numbering often known Base When counting binary numbers, number increments units column from next increment units column reset carried over next column. This column indicates that full counts have occurred units column. second column termed "twos" column. Hexadecimal numbers have values followed letters also known system with Base With this counting system units increment from with decimal system, next count units column increments from then After units column resets next column increments from This indicates that sixteen counts have occurred units column. second column termed "sixteens" column. following table shows three systems indicate successive numbers
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Appendix Decimal Base
Numbering Systems Binary Base Hexadecimal Base
Page
Notice next higher column does increment until lesser right overflowed. Binary representation ideally suited where visual representation computer register data needed. Each column termed (from Binary digIT). Only five Bits shown above table. With larger numbers, more Bits required. Normally Bits arranged groups eight termed BYTES. definition there BITS BYTE. Each column) value. binary table above rightmost least significant column each digit value Each digit next column value next then following diagram illustrates this.
DECIMAL VALUE
determine decimal value binary pattern, decimal number each column containing binary "1".
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Numbering Systems
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DECIMAL VALUE BINARY NUMBER
above example shows binary pattern that equivalent Decimal.
binary string defining Byte unwieldy. make less error prone, bits forming byte divided into groups bits, known NIBBLES. With four bits there possible numeric combinations (including zero). convenient method representing each nibble hexadecimal base system. When converting binary hex, byte divided into nibbles each represented single digit. This technique applied selection base address circuit board. following diagram illustrates construction number.
NIBBLE VALUE BINARY NUMBER
HEXADECIMAL: Hexadecimal upper nibble lower nibble resulting value Hex, since Decimal equals Hex.
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Appendix
Numbering Systems
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Base Address Selection
Each column physically represented board pair pins. practice, boards cover range addresses (usually Decimal). Therefore order four bits included, higher order bits added. This gives address range following diagram shows typical pins.
Here link fitted denote binary logic "0", left open indicate binary logic "1". example shows base address setting Hex.
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Maps
Appendix
APPENDIX MAPS PC/XT/AT Address
Address 000-01F 020-03F 040-05F 060-06F 070-07F 080-09F 0A0-0BF 0F8-0FF 1F0-1F8 200-207 278-27F 2F8-2FF 300-31F 360-36F 378-37F 380-38F 3A0-3AF 3B0-3BF 3C0-3CF 3D0-3DF 3F0-3F7 3F8-3FF Allocated Controller (8237A-5) Interrupt Controller (8259A) Timer (µPD71054) Keyboard Controller (8742) Control Port CMOS RAM, Mask (Write) Page Register (Memory Mapper) Interrupt Controller (8259) Clear (80287) Busy Reset (80287) Numeric Processor Extension (80287) Hard Disk Drive Controller Reserved Reserved Parallel Printer Port Reserved Serial Port Reserved Reserved Parallel Printer Port Reserved SDLC Communications, Bisync Reserved Bisync Reserved Reserved Display Controller Diskette Drive Controller Serial Port
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Appendix
Maps
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PC/XT Interrupt
Number Allocated Parity Timer Keyboard Reserved Asynchronous Communications (Secondary) SDLC Communications Asynchronous Communications (Primary) SDLC Communications Fixed Disk Diskette Parallel Printer
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Maps
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PC/AT Interrupt
Level CTLR CTLR Allocated Parity Channel Check (Interrupt Controllers) Timer Output Keyboard (Output Buffer Full) Interrupt from CTLR Real-time Clock Interrupt Redirected (IRQ Reserved Reserved Reserved Co-processor Fixed Disk Controller Reserved Serial Port Serial Port Parallel Port Diskette Controller Parallel Port
Channels
Memory Refresh Spare Floppy Disk Drive Spare
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Channel Analogue Input Board AIP-8d Document Part Document Refere

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