128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION CAT24C128 128-Kb Ser

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128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION CAT24C128 128-Kb Ser

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CAT24C128
128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION
CAT24C128 128-Kb Serial CMOS EEPROM, internally organized pages bytes each, total 16,384 bytes bits each. features 64-byte page write buffer supports both Standard (100 kHz) well Fast (400 kHz) protocol. Write operations inhibited taking High (this protects entire memory). CAT24C128 available RoHS compliant "Green" "Gold" 8-lead PDIP SOIC packages.
Supports Standard Fast Protocol Supply Voltage Range 64-Byte Page Write Buffer Hardware Write Protection entire memory Schmitt Triggers Noise Suppression Filters
Inputs (SCL SDA).
power CMOS technology 1,000,000 program/erase cycles year data retention RoHS compliant
8-pin PDIP SOIC packages
Industrial temperature range
CONFIGURATION
FUNCTIONAL SYMBOL
PDIP SOIC
CAT24C128
location please consult corresponding package drawing.
FUNCTIONS
Device Address Serial Data Serial Clock Write Protect Power Supply Ground
Catalyst carries protocol under license from Philips Corporation.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. 1103, Rev.
CAT24C128
ABSOLUTE MAXIMUM RATINGS* Storage Temperature Voltage with Respect Ground(1) -65°C +150°C -0.5 +6.5
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability.
RELIABILITY CHARACTERISTICS(2) Symbol NEND(*) Parameter Endurance Data Retention 1,000,000 Units Program/ Erase Cycles Years
Page Mode, 25°C
D.C. OPERATING CHARACTERISTICS -40°C 85°C, unless otherwise specified. Symbol VOL1 VOL2 Parameter Supply Current Standby Current Leakage Input Voltage Input High Voltage Output Voltage Output Voltage Test Conditions Read Write Pins -0.5 Units
IMPEDANCE CHARACTERISTICS 25°C, kHz, Symbol CIN(2) CIN(2) ZWPL ILWPH
Note: input voltage should lower than -0.5 higher than During transitions, voltage undershoot less than -1.5 overshoot more than periods less than These parameters tested initially after design process change that affects parameter according appropriate AEC-Q100 JEDEC test methods.
Parameter Capacitance Input Capacitance (other pins) Input Impedance Input High Leakage
Conditions
Units
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
A.C. CHARACTERISTICS -40°C 85°C, unless otherwise specified. Symbol FSCL TI(1) tAA(2) tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF(1) tSU:STO tPU(1),
Note: This parameter tested initially after design process change that affects parameter. timing measurements line capacitance input driven with rise fall times pulled-up current source; input driving signals swing from VCC. Output level reference levels respectively VCC. delay required from time stable until device ready accept commands.
Units
Parameter Clock Frequency Noise Suppression Time Constant SCL, Inputs Data Time Must Free Before Transmission Start Start Condition Hold Time Clock Period Clock High Period Start Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time Write Cycle Time Power-up Ready Mode
0.25
Power-On Reset (POR) CAT24C128 incorporates Power-On Reset (POR) circuitry which protects internal logic against powering wrong state. CAT24C128 will power into Standby mode after exceeds trigger level will power down into Reset mode when drops below trigger level. This bi-directional feature protects device against `brown-out' failure following temporary loss power. circuitry triggers minimum level required proper initialization internal state machines. trigger level automatically tracks internal CMOS device thresholds, naturally well below minimum recommended supply voltage.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
DESCRIPTION
SCL: Serial Clock input accepts Serial Clock generated Master. SDA: Serial Data receives input data transmits data stored EEPROM. transmit mode, this open drain. Data acquired positive edge, delivered negative edge SCL. Address pins accept device address. These pins have on-chip pull-down resistors. Write Protect input inhibits write operations, when pulled HIGH. This on-chip pull-down resistor.
START START condition precedes commands. consists HIGH transition while HIGH. START acts `wake-up' call receivers. Absent START, Slave will respond commands. STOP STOP condition completes commands. consists HIGH transition while HIGH. STOP starts internal Write cycle (when following Write command) sends Slave into standby mode (when following Read command). Device Addressing Master initiates data transfer creating START condition bus. Master then broadcasts 8-bit serial Slave address. first bits Slave address 1010, normal Read/Write operations (Figure next bits, select possible Slave devices. last bit, R/W, specifies whether Read Write operation performed. Acknowledge After processing Slave address, Slave responds with acknowledge (ACK) pulling down line during clock cycle (Figure Slave will also acknowledge byte address every data byte presented Write mode. Read mode Slave shifts data byte, then releases line during clock cycle. Master acknowledges data, then Slave continues transmitting. Master terminates session acknowledging last data byte (NoACK) sending STOP Slave. timing illustrated Figure
FUNCTIONAL DESCRIPTION
CAT24C128 supports Inter-Integrated Circuit (I2C) data transmission protocol, which defines device that sends data transmitter device receiving data receiver. Data flow controlled Master device, which generates serial clock START STOP conditions. CAT24C128 acts Slave device. Master Slave alternate either transmitter receiver. devices connected determined device address inputs
PROTOCOL
consists `wires', SDA. wires connected supply pull-up resistors. Master Slave devices connect 2wire their respective pins. transmitting device pulls down line `transmit' releases `transmit' `1'. Data transfer initiated only when busy (see A.C. Characteristics). During data transfer, line must remain stable while line HIGH. transition while HIGH will interpreted START STOP condition (Figure
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Figure Start/Stop Timing
START STOP
Figure Slave Address Bits
DEVICE ADDRESS
Figure Acknowledge Timing
FROM MASTER
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
Figure Timing
tLOW
tHIGH
tLOW
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
WRITE OPERATIONS
Byte Write Byte Write mode Master sends START, followed Slave address, byte address data written (Figure Slave acknowledges bytes, Master then follows with STOP, which turn starts internal Write operation (Figure During internal Write, Slave will acknowledge Read Write request from Master. Page Write CAT24C128 contains 16,384 bytes data, arranged pages bytes each. byte address word, following Slave address, points first byte written. most significant bits address word `don't care', next bits identify page last bits identify byte within page. bytes written Write cycle (Figure internal byte address counter automatically incremented after each data byte loaded. Master transmits more than data bytes, then earlier bytes will overwritten later bytes `wrap-around' fashion (within selected page). internal Write cycle starts immediately following STOP. Acknowledge Polling Acknowledge polling used determine CAT24C128 busy writing ready accept commands. Polling implemented interrogating device with `Selective Read' command (see READ OPERATIONS). CAT24C128 will acknowledge Slave address, long internal Write progress. Hardware Write Protection With held HIGH, entire memory protected against Write operations. left floating grounded, impact operation CAT24C128.
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Figure Byte Write Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
DATA
Don't Care
Figure Write Cycle Timing
Byte
STOP CONDITION
START CONDITION ADDRESS
Figure Page Write Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
DATA
DATA
DATA n+63
Don't Care
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
READ OPERATIONS
Immediate Address Read standby mode, CAT24C128 internal address counter points data byte immediately following last byte accessed previous operation. that `previous' byte last byte memory, then address counter will point memory byte, etc. When, following START, CAT24C128 presented with Slave address containing position (Figure will acknowledge (ACK) clock cycle, will then transmit data being pointed internal address counter. Master stop further transmission issuing NoACK, followed STOP condition. Selective Read Read operation also started address different from stored internal address counter. address counter initialized performing `dummy' Write operation (Figure Here START followed Slave address (with `0') desired byte address. Instead following with data, Master then issues START, followed `Immediate Address Read' sequence, described earlier. Sequential Read Master acknowledges data byte transmitted CAT24C128, then device will continue transmitting long each data byte acknowledged Master (Figure 10). memory reached during sequential Read, then address counter will `wrap-around' beginning memory, etc. Sequential Read works with either `Immediate Address Read' `Selective Read', only difference being starting byte address.
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Figure Immediate Address Read Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
DATA
DATA STOP
Figure Selective Read Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
BYTE ADDRESS A7-A0 A15-A8
SLAVE ADDRESS
DATA
Don't Care
Figure Sequential Read Timing
ACTIVITY: MASTER LINE
SLAVE ADDRESS
DATA
DATA
DATA
DATA
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
8-LEAD WIDE PLASTIC
SYMBOL
0.120 0.015 0.115 0.014 0.045 0.355 0.300 0.300 0.240
0.210
0.130 0.018 0.060 0.365 0.310 0.250 0.100 0.130
0.195 0.022 0.070 0.400 0.325 0.325 0.280 0.430 0.150
0.115
24C128_8-LEAD_DIP_(300P).eps
Notes: Complies with JEDEC Standard MS001. dimensions inches. Dimensioning tolerancing ANSI Y14.5M-1982
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
8-LEAD WIDE SOIC
SYMBOL
0.0040 0.0532 0.013 0.0075 0.1890 02284 0.149
0.0098 0.0688 0.020 0.0098 0.1968 0.2440 0.1574
0.050 0.0099 0.0196
24C128_8-LEAD_SOIC.eps
Notes: Complies with JEDEC specification MS-012 dimensions. linear dimensions millimeters.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
ORDERING INFORMATION
Prefix
Device 24C128
Suffix
Company
Product Number
Temperature Range Industrial (-40°C +85°C)
Package PDIP (Lead-free, Halogen-free) SOIC, JEDEC (Lead-free, Halogen-free)
Lead Finish/Tape Reel NiPdAu Lead Plating Tape Reel 3000/Reel
Notes: device used above example CAT24C128WI-GT3 (TSSOP, Industrial Temperature, Volt Volt Operating Voltage, Tape Reel)
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
PACKAGE MARKING
8-Lead PDIP 8-Lead SOIC
24C128LI YYWWA
24C128WI YYWWA
24C128L
Catalyst Semiconductor, Inc. Device Code Temperature Range Production Year Production Week Product Revision
Catalyst Semiconductor, Inc. 24C128W Device Code Temperature Range Production Year Production Week Product Revision
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
TAPE REEL
Direction Feed Device Orientation
SPROKET HOLE
COVER TAPE THICKNESS (t1) 0.10mm (0.004) THICK EMBOSSED CARRIER EMBOSSMENT
DEVICE ORIENTATION
TDFN
SOIC
TSSOP
Reel Dimensions(1)
40mm (1.575) MIN. ACCESS HOLE SLOT LOCATION
FULL RADIUS*
TAPE SLOT CORE TAPE START. 2.5mm (0.098) WIDTH 10mm (0.394) DEPTH (MEASURED HUB)
DRIVE SPOKES OPTIONAL, USED ASTERISKED DIMENSIONS APPLY.
Embossed Carrier Dimensions Tape Size 12MM (13.00) Qty/Reel 3000 (0.059) 12.80 (0.504) 13.20 (0.5200) 20.2 (0.795) (1.969) (0.328) (1.389) 12.4 (0.488) 14.4 (0.558) 14.4 (0.566) 18.4 (0.724)
Embossed Carrier Dimensions Component SOIC TDFN 2x3mm Package Type SP2, Tape Size 12mm Part Pitch
Note: Metric dimensions will govern; English measurements rounded, reference only parentheses.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. 1103, Rev.
CAT24C128
Embossed Carrier Dimensions Tape Only)
PITCHES CUMULATIVE TOLERANCE TAPE 0.2mm( 0.008) COVER TAPE
EMBOSSMENT MACHINE REFERENCE ONLY INCLUDING DRAFT RADII CONCENTRIC ABOUT
CENTER LINES CAVITY
COMPONENTS 2.0mm 1.2mm LARGER
USER DIRECTION FEED
Embossed Tape-Constant Dimensions Tape Sizes 12mm (0.059) (0.063) 1.65 (0.065) 1.85 (0.073) (0.153) (0.161) Max. (0.016) Min. (0.059) K0(2)
Embossed Carrier Dimensions Tape Only) Tape Sizes 12mm Max. (0.0323) 5.45 (0.0215) 5.55 (0.219) Max. (0.177) 1.95 (0.077) 2.05 (0.081) Min. (1.181) 11.7 (0.460) 12.3 (0.484) (0.275) (0.355)
Note: Metric dimensions will govern; English measurements rounded, reference only parentheses. determined component size. clearance between component cavity must within 0.05 (0.002) min. 0.65 (0.026) max. 12mm tape, 0.05 (0.002) min. 0.90 (0.035) max. 16mm tape, 0.05 (0.002) min. 1.00 (0.039) max. 24mm tape larger. component cannot rotate more than within determined cavity, Component Rotation.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
REVISION HISTORY
Date 10/07/05 11/16/05 Revision Comments Initial Issue Update Ordering Information Tape Reel Specifications
Doc. 1103, Rev.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Copyrights, Trademarks Patents Trademarks registered trademarks Catalyst Semiconductor include each following: MiniPot
Catalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. complete list patents issued Catalyst Semiconductor contact Company's corporate office 408.542.1000. CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES. Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
2005 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com
Publication Revison: Issue date:
1103 11/16/05

128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION CAT24C128 128-Kb Ser

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