96kHz 24Bit with AK4364 GENERAL DESCRIPTION AK4364 stereo CM

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96kHz 24Bit with AK4364 GENERAL DESCRIPTION AK4364 stereo CM

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[AK4364]
96kHz 24Bit with
AK4364
GENERAL DESCRIPTION AK4364 stereo CMOS Converter Phase Locked Loop digital video broadcast set-top applications DVD. signal outputs single-ended analog filtered remove band noise. Therefore external filters required. provides selectable sampling clock frequencies locked 27MHz recovered MPEG clock. AK4364 also Digital Audio Interface Transmitter. FEATURES Stereo S/(N+D): 90dB@5V 102dB@5V S/N: 102dB@5V Multiple Sampling Frequencies: 16kHz, 22.05kHz, 24kHz (Half speed) 32kHz, 44.1kHz, 48kHz (Normal speed) 64kHz, 88.2kHz, 96kHz (Double speed) On-Chip Jitter Analog PLL: Multiple Master Clock Frequencies generated from 27MHz Half speed 256fs/384fs/512fs/768fs Normal speed 128fs/192fs/256fs/384fs Double speed Master Clock: External Data Input Formats: justified justified selectable Selectable Function: Soft Mute Digital Attenuator (256 Steps) Digital De-emphasis (44.1kHz/48kHz/32kHz) Output Mode: Stereo, Mono, Reverse, Mute On-Chip Digital Audio Interface Transmitter: Compatible with S/PDIF, IEC958, AES/EBU EIAJ CP1201 consumer mode Input Level:TTL/CMOS Selectable Output Level: 3.0Vpp@5V Control mode: 3-wire Serial Power Dissipation: 80mW@5V Small 24pin VSOP Package Power Supply: 2.75.5V -4085°C
MS0014-E-02
2001/05
[AK4364]
Block Diagram
CAD1 CAD0 CCLK CDTI MCKI MCKO
AVDD
LRCK BICK SDTI
Serial Input Interface
Clock Generator
AVSS VCOM
DVDD DVSS
Interpolator Interpolator
Modulator Modulator
AOUTL
Mixer
AOUTR
Figure 3-wire Serial Control Mode (I2C "L")
CAD1 CAD0 MCKI MCKO
AVDD
LRCK BICK SDTI
Serial Input Interface
Clock Generator
AVSS VCOM
DVDD DVSS
Interpolator Interpolator
Modulator Modulator
AOUTL
Mixer
AOUTR
Figure Control Mode (I2C "H")
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[AK4364]
Ordering Guide
AK4364VF AKD4364 -40+85°C Evaluation Board 24pin VSOP
Layout
MCKO DVDD DVSS MCKI BICK SDTI LRCK SCL/CCLK SDA/CDTI
AVDD AVSS VCOM AOUTL AOUTR CAD1 CAD0
View
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[AK4364]
PIN/FUNCTION
Name MCKO Description Master Clock Output "0": System clock output from circuit (PLL mode), "1": Same frequency MCKI output (External mode) Transmit Channel Output Digital Power Supply Pin, +2.7+5.5V Digital Ground Pin, System Clock Input "0": 27MHz (PLL mode), "1": Other frequency (External mode) Serial Data Clock Serial Data Input Serial Input Channel Clock Power-Down When "L", circuit power-down mode. AK4364 should always reset upon power-up. Chip Select 3-wire Serial control mode This should connected DVDD control mode. Control Clock control mode Control Clock 3-wire serial control mode Control Data Input/Output control mode Control Data Input 3-wire serial control mode Test This should connected DVSS. Digital Input Level Select "L": CMOS, "H": Control Mode Select "L": 3-wire Serial, "H": Chip Address Select Chip Address Select Analog Output Analog Output Common Voltage Output Pin, AVDD/2 Used analog common voltage. Large external capacitor used reduce power supply noise. Analog Ground Analog Power Supply Output Loop Filter Circuit This should connected AVSS with resister capacitor series. "SYSTEM DESIGN".) Zero Input Detect When SDTI follows total 8192 LRCK cycles with input data RSTN "0", this goes "H".
DVDD DVSS MCKI BICK SDTI LRCK
CCLK CDTI CAD0 CAD1 AOUTR AOUTL VCOM
AVSS AVDD
Note: input pins should left floating.
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[AK4364]
ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note Parameter Symbol Power Supplies Analog AVDD -0.3 Digital DVDD -0.3 |AVSS-DVSS| (Note Input Current (any pins except supplies) Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature Storage Temperature Tstg
Note:1. voltages with respect ground. AVSS DVSS must connected same analog ground plane.
AVDD+0.3 DVDD+0.3
Units
WARNING: Operation beyond these limits results permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note Parameter Symbol Power Supplies operation (TTL "L") (Note Analog AVDD Digital DVDD operation (TTL "H") Analog AVDD Digital DVDD
Note:1. voltages with respect ground. power sequence between AVDD DVDD critical.
AVDD AVDD
Units
*AKM assumes responsibility usage beyond conditions this datasheet.
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[AK4364]
ANALOG CHARACTERISTICS (fs=44.1kHz) (Ta=25°C; AVDD, DVDD=5V; fs=44.1kHz; "1"; FS1-0 "00"; DFS1-0 "00"; CKS2-0 "000"; DIF2-0 "101"; Signal Frequency =1kHz; Measurement frequency=20Hz20kHz; unless otherwise specified) Parameter Units Dynamic Characteristics Resolution Bits S/(N+D) AVDD=5V AVDD=3V (-60dB input, A-weighted) AVDD=5V AVDD=3V (A-weighted) AVDD=5V AVDD=3V Interchannel Isolation Accuracy Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage AOUT=0.6x(AVDD-AVSS) AVDD=5V AVDD=3V 1.66 1.94 Load Resistance (Note Load Capacitance Power Supplies Power Supply Current Normal Operation (PDN "H") (Note AVDD DVDD Power-Down-Mode (PDN "L") AVDD+DVDD
Note:4. load. AVDD 9mA(typ) "0". DVDD drops DVDD=3V.
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[AK4364]
ANALOG CHARACTERISTICS (fs=96kHz) (Ta=25°C; AVDD, DVDD=5V; fs=96kHz; "1"; FS1-0 "01"; DFS1-0 "01"; CKS2-0 "001"; DIF2-0 "101"; Signal Frequency =1kHz; Measurement frequency=20Hz40kHz; unless otherwise specified) Parameter Units Dynamic Characteristics Resolution Bits S/(N+D) AVDD=5V AVDD=3V (-60dB input) AVDD=5V AVDD=3V AVDD=5V AVDD=3V Interchannel Isolation Accuracy Interchannel Gain Mismatch Gain Drift ppm/°C Output Voltage AOUT=0.6x(AVDD-AVSS) AVDD=5V AVDD=3V 1.66 1.94 Load Resistance (Note Load Capacitance Power Supplies Power Supply Current Normal Operation (PDN "H") (Note AVDD DVDD Power-Down-Mode (PDN "L") AVDD+DVDD
Note:4. load. AVDD 9mA(typ) "0". DVDD drops DVDD=3V.
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[AK4364]
FILTER CHARACTERISTICS (fs=44.1kHz) (Ta=25°C; AVDD, DVDD=2.75.5V; fs=44.1kHz; DEM=OFF) Parameter Symbol Digital Filter Passband (Note -0.02dB -6.0dB 22.05 Stopband (Note 24.1 Passband Ripple Stopband Attenuation Group Delay (Note 20.1 Digital Filter Analog Filter Frequency Response: 020.0kHz ±0.2
20.0 ±0.02
Units 1/fs
Note:7. passband stopband frequencies scale with example, PB=0.4535*fs(@±0.02dB), SB=0.546*fs. calculating delay time which occurred digital filtering. This time from setting 24bit data both channels input register output analog signal.
FILTER CHARACTERISTICS (fs=96kHz) (Ta=25°C; AVDD, DVDD=2.75.5V; fs=96kHz; DEM=OFF) Parameter Symbol Digital Filter Passband (Note -0.02dB -6.0dB 48.0 Stopband (Note 52.5 Passband Ripple Stopband Attenuation Group Delay (Note 20.1 Digital Filter Analog Filter Frequency Response: 020.0kHz ±0.2 40.0kHz ±0.2
43.5 ±0.02
Units 1/fs
Note:7. passband stopband frequencies scale with example, PB=0.4535*fs(@±0.02dB), SB=0.546*fs. calculating delay time which occurred digital filtering. This time from setting 24bit data both channels input register output analog signal.
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[AK4364]
DIGITAL CHARACTERISTICS (CMOS level input) (Ta=25°C; AVDD=2.75.5V; DVDD=2.73.6V; "L") Parameter Symbol High-Level input voltage 0.7xDVDD Low-Level input voltage High-Level Output Voltage (TX, MCKO pins: Iout=-100µA) DVDD-0.5 (DZF pin: Iout=-100µA) AVDD-0.5 Low-Level Output Voltage (TX, MCKO, pins: Iout= 100µA) (SDA pin: Iout= 3mA) Input leakage current
0.3xDVDD
Units
DIGITAL CHARACTERISTICS (TTL level input; except pin) (Ta=25°C; AVDD, DVDD=4.55.5V; "H") Parameter Symbol Units High-Level input voltage (TTL pin) 0.7xDVDD (All pins except pin) Low-Level input voltage (TTL pin) 0.3xDVDD (All pins except pin) High-Level Output Voltage (TX, MCKO pins: Iout=-100µA) DVDD-0.5 (DZF pin: Iout=-100µA) AVDD-0.5 Low-Level Output Voltage (TX, MCKO, pins: Iout= 100µA) (SDA pin: Iout= 3mA) Input leakage current
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[AK4364]
SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.75.5V; CL=20pF) Parameter Symbol 27MHz Input (PLL mode): Frequency f27M Pulse Width t27ML Pulse Width High t27MH Master Clock Input (External mode): Frequency 128fs/256fs/512fs/1024fs fCLK 4.096 192fs/384fs/768fs/1536fs fCLK 6.144 Duty Cycle dCLK MCKO Output (PLL mode): Frequency fMCKO 4.096 Duty Cycle dMCKO Rise time (20% DVDD) trMCKO Fall time (80% DVDD) tfMCKO LRCK: (Note Frequency Half Speed Mode (DFS1-0 "11") Normal Speed Mode (DFS1-0 "00") Double Speed Mode (DFS1-0 "01") Duty Duty Cycle Serial Interface Timing: BICK Period Half Speed Mode tBCK 1/128fs Normal Speed Mode tBCK 1/128fs Double Speed Mode tBCK 1/64fs BICK Pulse Width tBCKL BICK Pulse Width High tBCKH tBLR BICK LRCK Edge (Note tLRB LRCK Edge BICK (Note tSDH SDTI Hold Time tSDS SDTI Setup Time Power-down Reset Timing Pulse Width (Note tPDW
Units
24.576 36.864 36.864
Note: sampling speed mode (DFS0-1) changes, please reset RSTN bit. BICK rising edge must occur same time LRCK edge. AK4364 reset upon power CKS0-2 DFS0-1 changes, AK4364 should reset RSTN bit.
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[AK4364]
Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Pulse Width High CDTI Setup Time CDTI Hold Time Time CCLK CCLK Control Interface Timing (I2C mode): Clock Frequency Free Time Between Transmissions Start Condition Hold Time (prior first clock pulse) Clock Time Clock High Time Setup Time Repeated Start Condition Hold Time from Falling (Note Setup Time from Rising Rise Time Both Lines Fall Time Both Lines Setup Time Stop Condition Pulse Width Spike Noise suppressed Input Filter
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tSU:STO
0.25
Units
Note:12. Data must held sufficient time bridge transition time SCL.
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[AK4364]
Timing Diagram
1/f27M t27MH t27ML
1/fCLK tCLKH tCLKL dCLK=tCLKH*fCLK*100 =tCLKL*fCLK*100
MCKI
1/fMCKO
MCKO
50%DVDD
1/fs
LRCK
1/fBCK tBCKH tBCKL
BICK
Clock Timing
tBLR tLRB tSDS tSDH
LRCK
BICK
SDTI
Serial Interface Timing
tPDW
Power-down Reset Timing
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[AK4364]
tCSS tCCKL tCCKH tCDS tCDH
CCLK
CDTI
WRITE Command Input Timing (3-wire Serial mode)
tCSW tCSH CCLK
CDTI
WRITE Data Input Timing (3-wire Serial mode)
tBUF tLOW tHIGH tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start tSU:STO Stop
mode Timing
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[AK4364]
OPERATION OVERVIEW System Clock Input
mode (EXT "0") fully integrated analog phase locked loop generates MCKO which locked 27MHz reference input. frequency MCKO output selectable register data CKS2-0, DFS1-0 FS1-0 defined Table 1-3. requires 20ms lock time whenever MCKO frequency selection changes MCKO source changes from mode mode, 100ms upon power-up after 27MHz system clock stabilizes. While unlocked, serial input data zeroed internally prevent spurious output outputs wrong data (not "L"). When 27MHz clock present, internal frequency pulled minimum value. LRCK input must synchronous with MCKO, however phase critical. Internal timing synchronized LRCK input upon power-up. When MCKO frequency changes register data CKS2-0, DFS1-0 FS1-0 during normal operation, AK4364 should reset RSTN "0". Serial input data zeroed internally until locked after exiting resetting. External mode (EXT "1") When "1", master clock input MCKI pin. this case, MCKO frequency same MCKI necessary change register data FS1-0. external clocks which required operate AK4364 MCKI, LRCK BICK. master clock (MCKI) should synchronized with sampling clock (LRCK) phase critical. MCKI used operate digital interpolation filter delta-sigma modulator. frequency MCKI CKS2-0, selected half, normal double speed mode DFS1-0 (See Table this case, internal powered down. Therefore, external clocks should always present whenever AK4364 normal operation mode (PDN "H"). these clock provided, AK4364 draw excess current possibly operate properly because device utilizes dynamic refreshed logic internally. external clocks present, AK4364 should power-down mode (PDN "L") reset mode (RSTN "0"). After exiting reset power-up etc., AK4364 power-down mode until MCKI LRCK input. When register data CKS2-0 DFS1-0 changed during normal operation, AK4364 should reset RSTN "0".
DFS1-0 "11" "00" "01" (Half speed) (Normal speed) (Double speed) 22.05 88.2 default (DFS1-0 "00") 44.1 Table Sampling Frequency [kHz] (FS1-0 "11", DFS1-0 "10": reserved)
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[AK4364]
CKS2
CKS1
DFS1-0 "11" "00" "01" (Half speed) (Normal speed) (Double speed) 512fs 128fs 256fs 256fs 256fs 256fs 768fs 384fs 192fs 384fs 384fs 384fs 1024fs 512fs 256fs 512fs 512fs 1536fs 768fs 384fs 768fs 768fs Table System Clock (DFS1-0 "10": reserved) CKS0
default (DFS1-0 "00")
[kHz] 22.05 44.1 88.2
Mode Half Normal Double Half Normal Double Half Normal Double
128fs 8.1920 11.2896 12.2880
192fs 256fs 384fs 512fs 4.0960 6.1440 8.1920 8.1920 12.2880 16.3840 12.2880 16.3840 24.5760 5.6448 8.4672 11.2896 11.2896 16.9344 22.5792 16.9344 22.5792 33.8688 6.1440 9.2160 12.2880 12.2880 18.4320 24.5760 18.4320 24.5760 36.8640 Table Example System Clock [MHz]
768fs 12.2880 24.5760 16.9344 33.8688 18.4320 36.8640
1024fs 16.3840 22.5792 24.5760
1536fs 24.5760 33.8688 36.8640
Audio Serial Interface Format
Data shifted SDTI using BICK LRCK inputs. serial data modes supported selected register data DIF2-0 shown Table modes serial data MSB-first, compliment format latched rising edge BICK. Mode used justified formats zeroing unused LSBs. Mode DIF2 DIF1 DIF0 SDTI 16bit, justified 18bit, justified 20bit, justified 24bit, justified 24bit, justified Reserved Reserved Table Audio Data Format BICK 32fs 36fs 40fs 48fs 48fs 48fs
default
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[AK4364]
LRCK
BICK (32fs) SDTI Mode
BICK (64fs) SDTI Mode SDTI Mode
Don't care 15:MSB, 0:LSB Don't care 17:MSB, 0:LSB
Don't care
Don't care
BICK (64fs) SDTI Mode SDTI Mode
Don't care 19:MSB, 0:LSB Don't care 23:MSB, 0:LSB Don't care Don't care
Data
Data
Figure Mode Timing
LRCK
BICK (64fs) SDTI
Don't care Don't care
23:MSB, 0:LSB
Data
Figure Mode Timing
Data
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[AK4364]
LRCK
BICK (64fs) SDTI
Don't care Don't care
23:MSB, 0:LSB
Data Figure Mode Timing
Data
Output Format
Data input SDTI formatted digital interface format output pin. Data transmitted output formatted blocks shown figure Each block consists frames. frame data contains sub-frames. sub-frame consists bits information. Each data received coded using bi-phase mark encoding binary state symbol. preambles violate bi-phase encoding they differentiated from data. bi-phase encoding, first state input symbol always inverse last state previous data symbol. logic second state symbol same first state. second state opposite first. Figure illustrates sample stream data bits encoded symbol states.
Channel Channel Channel Channel Channel Channel Sub-frame Frame Sub-frame Frame
Frame Figure Block format
Figure biphase-encoded stream
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[AK4364]
sub-frame defined figure below: Bits sub-frame represent preamble synchronization. There three preambles: block preamble, contained first sub-frame Frame channel preamble, contained first sub-frame other frames. channel preamble, contained second sub-frames. Table defines symbol encoding each preambles. Bits 4-27 sub-frame contain audio sample complement format with most significant (MSB). mode, Bits 4-11 validity flag. This equal register. user data bit. This always AK4364. channel status bit. Frame contains first word with last frame 191. even parity bits 4-31 sub-frame.
Sync
Audio sample
Figure Sub-frame format
block data contains consecutive frames transmitted rate times sample frequency, Preamble Preceding state 11101000 11100010 11100100 Preceding state 00010111 00011101 00011011
Table Sub-frame preamble encoding Figure shows relation between input data SDTI audio data sub-frame.
Sub-frame Mode Mode Mode
Audio sample
Mode 3,4,5
Figure Relation between input data SDTI audio data sub-frame
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[AK4364]
De-emphasis filter
digital de-emphasis filter available 44.1 48kHz sampling speed (tc=50/15µs). enabled disabled with control register data DEM1-0 DFS1-0. de-emphasis filter disabled half/double sampling mode. DEM1 DEM0 De-emphasis 44.1kHz default 48kHz 32kHz Table De-emphasis filter control with DEM1-0 (DFS1-0 "00") DFS1 DFS0 De-emphasis Table default Table De-emphasis filter control with DFS1-0
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[AK4364]
Zero detection
When input data both channels continuously zeros 8192 LRCK cycles, goes "H". immediately goes input data zero after going "H". RSTN becomes "0", goes "H". goes 45/fs after RSTN returns "1".
Soft mute operation
Soft mute operation performed digital domain. When serial control register data SMUTE goes "1", output signal attenuated during 1024 LRCK cycles. When SMUTE returned "0", mute cancelled output attenuation gradually changes during 1024 LRCK cycles. soft mute cancelled within 1024 LRCK cycles after starting operation, attenuation discontinued returned 0dB. soft mute effective changing signal source without stopping signal transmission.
SMUTE 1024/fs Attenuation 1024/fs
AOUT 8192/fs
Notes: output signal attenuated during 1024 LRCK cycles (1024/fs). Analog output corresponding digital input have group delay (GD). soft mute cancelled within 1024 LRCK cycles, attenuation discontinued returned 0dB. When input data both channels continuously zeros 8192 LRCK cycles, goes "H". immediately goes input data zero after going "H". Figure Soft mute zero detection
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[AK4364]
Power-down
placed power-down mode bringing digital filter also reset same time. internal register values initialized "L". This reset should always done after power-up. Because some click noise occurs edge PDN, analog output should muted externally click noise influences system application.
Internal State (Digital)
Normal Operation
Power-down
Normal Operation
data
(Analog)
Clock
MCKI, LRCK, BICK
Don't care
External MUTE
Mute
Notes: analog output corresponding digital input group delay (GD). Analog outputs floating power-down mode. Click noise occurs edge signal. This noise output even data input. external clocks (MCKI, BICK LRCK) stopped power-down mode (PDN "L"). Please mute analog output externally click noise influences system application. timing example shown this figure. power-down mode (PDN "L"). Figure Power-down/up sequence example
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[AK4364]
Reset function
When RSTN "0", powered down internal register values initialized. analog outputs VCOM voltage goes "H". Figure shows sequence reset RSTN bit. RSTN
2~3/fs
Internal RSTN Internal State (Digital) (Analog)
Clock
MCKI,LRCK,BICK
Normal Operation
Digital Block Power-down
Normal Operation
data
Don't care
2/fs(5)
Notes: analog output corresponding digital input group delay (GD). Analog outputs VCOM voltage. Click noise occurs edges(" internal timing RSTN bit. This noise output even data input. external clocks (MCKI, BICK LRCK) stopped reset mode (RSTN "L"). goes when RSTN becomes "0", goes 4~5/fs after RSTN becomes "1". There delay, 2~3/fs from RSTN internal RSTN "1". Figure Reset sequence example
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[AK4364]
Serial Control Interface
AK4364 control functions registers. Internal registers written types control mode. chip address determined state CAD0 CAD1 inputs. initializes registers their default values. Writing RSTN initialize internal timing circuit. this case, register data initialized. 3-wire Serial Control Mode (I2C "L") Internal registers written wire interface pins (CSN,CCLK CDTI). data this interface consists Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed "1"; Write only), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge CCLK data clocked falling edge. write operations, data latched after low-to-high transition CSN. clock speed CCLK 5MHz(max). CCLK pins should held except access.
CCLK
CDTI
C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: Read/Write (Fixed Write only) A4-A0: Register Address D7-D0: Control Data Control Mode (I2C "H") Internal registers written interface pins: SDA. data this interface consists Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed "0"; Write only), Register address (MSB first, 5bits) Control data (MSB first, 8bits). Address data clocked rising edge data clocked falling edge. Data written after high-to-low transition when "H"(start condition), latched after low-to-high transition when "H"(stop condition). clock speed 100kHz(max). should connected DVDD control mode. AK4364 does have register address auto increment capability.
Start
Stop
C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: Read/Write (Fixed Write only) A4-A0: Register Address D7-D0: Control Data ACK: Acknowledge When AK4364 power down mode (PDN "L") MCLK provided, writing into control register inhibited.
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[AK4364]
Mapping Program Registers
Addr Register Name Control Control Control Channel Status Channel Status ATT7 ATT7 CS15 ATT6 ATT6 CS29 CS14 DFS1 ATT5 ATT5 CS28 CS13 DFS0 ATT4 ATT4 CS25 CS12 DIF2 CKS2 DEM1 ATT3 ATT3 CS24 CS11 DIF1 CKS1 DEM0 ATT2 ATT2 CS10 DIF0 CKS0 ATT1 ATT1 RSTN RSTN SMUTE ATT0 ATT0
Note: addresses from 1FH, data should written. When goes "L", registers initialized their default values. When RSTN goes "0", internal timing reset, goes registers initialized their default values.
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[AK4364]
Register Definitions
Addr Register Name Control Default DIF2 DIF1 DIF0 RSTN
RSTN: Internal timing reset Reset. goes registers initialized. Normal operation When states DIF2-0,EXT,CKS2-0,DFS1-0 FS1-0 changes, AK4364 should reset RSTN bit. Some click noise occur that timing. DIF2-0: Audio data interface modes (See Table Initial: "101", Mode EXT: Master clock select mode (27MHz clock input) External clock mode. Internal powered down.
Addr
Register Name Control Default
DFS1
DFS0
CKS2
CKS1
CKS0
RSTN
RSTN: Internal timing reset Reset. goes registers initialized. Normal operation When states DIF2-0,EXT,CKS2-0,DFS1-0 FS1-0 changes, AK4364 should reset RSTN bit. Some click noise occur that timing. CKS2-0: Clock select (See Table Initial: "000" DFS1-0: Half/Normal/Double sampling modes (See Table 1,2), De-emphasis response (See Table Initial: "00" FS1-0: Sampling frequency modes (See Table Initial: "00"
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[AK4364]
Addr
Register Name Control Default
DEM1
DEM0
SMUTE
SMUTE: Soft Mute Enable Normal operation outputs soft-muted ATC: Attenuation Control attenuation data each register applied separately left right channels. attenuation data loaded addr=03H used both left right channels. DEM1-0: De-emphases response (See Table 6,7.) Initial: "01", PL3-0: Mixing mode
Output Output Note MUTE MUTE MUTE MUTE MUTE MUTE (L+R)/2 MUTE REVERSE (L+R)/2 MUTE STEREO (L+R)/2 (L+R)/2 MUTE (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2 MONO Table Programmable Output Format
default
STEREO: REVERSE: MONO: MUTE:
Normal stereo output Reverse output Monaural output Soft mute operation
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[AK4364]
Addr
Register Name Default
ATT7 ATT7
ATT6 ATT6
ATT5 ATT5
ATT4 ATT4
ATT3 ATT3
ATT2 ATT2
ATT1 ATT1
ATT0 ATT0
Equation attenuation level: Log10 (Binary level 255) [dB] FFH: 01H: -48.1dB 00H: Mute transition between values same soft mute operation. When current value ATT1 value ATT2, ATT1 gradually becomes ATT2 with same operation soft mute. value ATT3 before reaching ATT2, value gradually becomes ATT3 from transition. Cycle time soft mute: Ts=1024/fs When goes "L", values 00H. values fade FFH(0dB) during after returns "H". When RSTN goes "0", values 00H. values fade their current values after RSTN returns "1". Digital attenuator independent soft mute function.
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Addr
Register Name Default
TXE:
output Normal Operation Validity Flag Valid Invalid Register Name Channel Status Default Audio Non-Audio Copyright Non-Copyright Pre-emphasis 50/15µsec Pre-emphasis CS29 CS28 CS25 CS24
Addr
CS24,25: Sampling Frequency 44.1kHz 48kHz Reserved 32kHz CS28,29: Clock Accuracy Standard mode Variable pitch mode High accuracy mode Reserved
Addr
Register Name Channel Status Default
CS15
CS14
CS13
CS12
CS11
CS10
CS8-15: Category code (See Standard EIAJ.) 00100000: Digital Audio Broadcast Reception Japan (default)
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[AK4364]
Channel Status Explanation (from Standard EIAJ IEC958)
CS15 CS23 CS31 CS14 CS22 CS30 CS13 CS12 CS11 CS10 CS21 CS20 CS19 CS18 CS17 CS16 CS29 CS28 CS27 CS26 CS25 CS24 (Bold type: Programmable, Normal type: fixed this device)
Byte Byte Byte Byte
Consumer (fixed) Audio Non-audio Copyright Non-copyright CS3-5 000: pre-emphasis 100: 50/15µsec pre-emphasis (CS4-5: fixed CS6-7: Mode Mode (fixed) CS8-15: Category code (See next page. more detail information, please Standard EIAJ.) CS16-19: Source number regulated (fixed) CS20-23: Channel (fixed) 1000: Left 0100: Right CS24-27: Sampling frequency 0000: 44.1kHz 0100: 48kHz 1100: 32kHz others: regulated CS28-29: Clock accuracy Standard mode Variable pitch mode High accuracy mode regulated CS30- Reserved (fixed
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[AK4364]
Category code (bit 8-15)
bit15 bit): indicates generation digital audio signal. General regulated recorded software issued business Optical disc machine ("100 xxxxL"), Broadcast reception ("001 xxxxL" "011 1xxxL") recorded software issued business regulated "000 00000": General (Digital audio reception without copyright information Japan) "100 xxxxL":Optical disc machine "100 0000L":Compact disc adapted IEC908 "100 1000L":Optical disc adapted IEC908 "100 1001L":Mini disc system "100 1100L":Digital video disc "010 xxxxL" "011 1xxxL": Digital/digital converting machine signal process machine "010 0000L":PCM encoder/decoder "010 0100L":Digital signal mixer "010 1100L":Sampling rate converter "010 0010L":Digital sound sampler "110 xxxxL":Magnetic tape magnetic disc machine "110 0000L":Digital audio tape "110 1000L":Video tape recorder with digital voice "110 0001L":Digital compact cassette "001 xxxxL":Digital audio broadcast reception "001 0000L":in Japan ("001 00000": default) "001 1000L":in Europe "001 0011L":in U.S.A "001 0001L":Software electronics delivery "101 xxxxL: Music instrument, microphone source processing original signal "101 0000L":Synthesizer "101 1000L":Microphone "011 00xxx": converter without copyright information "011 0000x": converter "011 01xxL":A/D converter with copyright information "011 0100L":A/D converter "000 1xxxL":Solid memory machine "000 0001L":Experimental machine used business "111 xxxxL":Not regulated "000 0xxxL":Not regulated (except "000 00000" "000 0001L")
MS0014-E-02
2001/05
[AK4364]
SYSTEM DESIGN
Figure shows system connection diagram. evaluation board available which demonstrates application circuits, optimum layout, power supply arrangements measurement results. Condition: AVDD=DVDD=5V(TTL mode), mode, mode, Chip Address "00"
Analog
Optical
0.1u MCKO DVDD DVSS MCKI BICK SDTI LRCK
AVDD AVSS 5.1k (Note) 0.1u 0.1u 0.22u
27MHz
AK4364
VCOM AOUTL AOUTR
Decoder
MUTE
View
CAD1 CAD0
Reset
MUTE
System Ground
Analog Ground
Figure Typical Connection Diagram Note:This resister changed distortion frequency (around 1kHz) critical. However distortion high frequency degrades this case.
MS0014-E-02
2001/05
[AK4364]
Digital Ground
Analog Ground
MCKO DVDD DVSS MCKI BICK SDTI LRCK
AVDD AVSS VCOM
System Controller
AK4364
AOUTL AOUTR CAD1 CAD0
Figure Ground Layout Note: AVSS DVSS must connected same analog ground plane.
Grounding Power Supply Decoupling
AK4364 requires careful attention power supply grounding arrangements. AVDD DVDD usually supplied from analog supply system. Alternatively AVDD DVDD supplied separately, power sequence critical. AVSS DVSS AK4364 must connected analog ground plane. System analog ground digital ground should connected together near where supplies brought onto printed circuit board. Decoupling capacitors should near AK4364 possible, with small value ceramic capacitors being nearest.
Voltage Reference Inputs
differential voltage between AVDD AVSS sets analog output range. VCOM AVDD/2 normally connected AVDD with 0.1µF ceramic capacitor. electrolytic capacitor 10µF parallel with 0.1µF ceramic capacitor attached VCOM eliminates effects high frequency noise. load current drawn from these pins. signals, especially clocks, should kept away from VCOM order avoid unwanted coupling into AK4364.
Analog Outputs
analog outputs single-ended outputs 0.6x(AVDD-AVSS) (typ) centered around VCOM voltage. internal switched-capacitor filter continuous-time filter attenuate noise generated delta-sigma modulator beyond audio passband. input data format complement. output voltage positive full scale 7FFFFF(@24bit) negative full scale 800000H(@24bit). ideal output 000000H(@24bit).
MS0014-E-02
2001/05
[AK4364]
PACKAGE
24pin VSOP (Unit:
*7.8±0.15 1.25±0.2
7.6±0.2 0.15±0.05 0.1±0.1 Detail 0-10° 0.5±0.2 0.10
Epoxy Solder plate 2001/05
0.22±0.1
0.65
Seating Plane
NOTE: Dimension does include mold flash.
Package Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
MS0014-E-02
*5.6±0.2
[AK4364]
MARKING
AK4364VF AAXXXX
Contents AAXXXX Lot# XXXX: Date Code
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS0014-E-02
2001/05

96kHz 24Bit with AK4364 GENERAL DESCRIPTION AK4364 stereo CM

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