AT91 ARM® Thumb®-based Microcontrollers AT91SAM7X256/ AT91SAM7X128 Pre
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High-performance 32-bit RISC Architecture High-density 16-bit Instruction Leader MIPS/Watt Embedded ICEIn-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash Kbytes (AT91SAM7X256) Organized 1024 Pages Bytes Kbytes (AT91SAM7X128) Organized Pages Bytes Single Cycle Access Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution Maximum Speed Page Programming Time: Including Page Auto-erase, Full Erase Time: 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Fast Flash Programming Interface High Volume Production Internal High-speed SRAM, Single-cycle Access Maximum Speed Kbytes (AT91SAM7X256) Kbytes (AT91SAM7X128) Memory Controller (MC) Embedded Flash Controller, Abort Status Misalignment Detection Reset Controller (RSTC) Based Power-on Reset Cells Low-power Factory-calibrated Brownout Detector Provides External Reset Signal Shaping Reset Source Status Clock Generator (CKGR) Low-power Oscillator, On-chip Oscillator Power Management Controller (PMC) Power Optimization Capabilities, Including Slow Clock Mode (Down Idle Mode Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART Support Debug Communication Channel interrupt, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) 12-bit key-protected Programmable Counter Provides Reset Interrupt Signals System Counter Stopped While Processor Debug State Idle Mode Real-time Timer (RTT) 32-bit Free-running Counter with Alarm Runs Internal Oscillator Parallel Input/Output Controllers (PIO) Sixty-two Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up Resistor Synchronous Output
AT91 ARM® Thumb®-based Microcontrollers AT91SAM7X256/ AT91SAM7X128 Preliminary
6120C-ATARM-25-Oct-05
Thirteen Peripheral Controller (PDC) Channels Full Speed Mbits second) Device Port
On-chip Transceiver, 1352-byte Configurable Integrated FIFOs
Ethernet 10/100 base-T Media Independent Interface (MII) Reduced Media Independent Interface (RMII) Integrated 28-byte FIFOs Dedicated Channels Transmit Receive Part 2.0A Part 2.0B Compliant Controller Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Synchronous Serial Controller (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Line Support USART1 Master/Slave Serial Peripheral Interfaces (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three-channel 16-bit Timer/Counter (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Power Width Modulation Controller (PWMC) Two-wire Interface (TWI) Master Mode Support Only, Two-wire Atmel EEPROMs Supported 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BABoot Assistance Default Boot program Interface with SAM-BA Graphic User Interface IEEE 1149.1 JTAG Boundary Scan Digital Pins 5V-tolerant I/Os, Including Four High-current Drive lines, Each Power Supplies Embedded 1.8V Regulator, Drawing Core External Components 3.3V VDDIO Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: 1.65V Worst Case Conditions Available 100-lead LQFP Green Package
AT91SAM7X256/128 Preliminary
6120C-ATARM-25-Oct-05
AT91SAM7X256/128 Preliminary
Description
Atmel's AT91SAM7X256/128 member series highly integrated Flash microcontrollers based 32-bit RISC processor. features 256/128 Kbyte high-speed Flash 64/32 Kbyte SRAM, large peripherals, including 802.3 Ethernet controller. complete system functions minimizes number external components. embedded Flash memory programmed in-system JTAG-ICE interface parallel interface production programmer prior mounting. Built-in lock bits security protect firmware from accidental overwrite preserve confidentiality. AT91SAM7X256/128 system controller includes reset controller capable managing power-on sequence microcontroller complete system. Correct device operation monitored built-in brownout detector watchdog running integrated oscillator. combining ARM7TDMI processor with on-chip Flash SRAM, wide range peripheral functions, including USART, SPI, Controller, Ethernet MAC, Timer Counter, Analog-to-Digital Converters monolithic chip, AT91SAM7X256/128 powerful device that provides flexible, cost-effective solution many embedded control applications requiring communication over, example, Ethernet, wired Zigbee wireless networks.
Configuration Summary AT91SAM7X256 AT91SAM7X128
AT91SAM7X256 AT91SAM7X128 differ only memory sizes. Table summarizes configurations devices.
Table 2-1.
Device AT91SAM7X256 AT91SAM7X128
Configuration Summary
Flash 256K bytes 128K bytes SRAM bytes bytes
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AT91SAM7X256/128 Block Diagram
Figure 3-1.
JTAGSEL
AT91SAM7X256/128 Block Diagram
JTAG SCAN
ARM7TDMI Processor
Voltage Regulator
VDDIN VDDOUT VDDCORE
System Controller
IRQ0-IRQ1
Memory Controller
VDDIO
DRXD DTXD
DBGU
Embedded Flash Controller Abort Status
SRAM
64/32 Kbytes
Address Decoder Misalignment Detection
PCK0-PCK3 PLLRC XOUT
VDDFLASH
RCOSC Peripheral Bridge
Flash
256/128 Kbytes
ERASE
VDDCORE VDDFLASH VDDCORE NRST
Reset Controller
Peripheral Controller
Channels
Fast Flash Programming Interface
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1
PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADTRG ADVREF
SAM-BA
FIFO Ethernet 10/100
PIOB
USART0
FIFO
Transceiver
ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL, ECRSDV ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 VDDFLASH
USART1
Device
PWMC
SPI0
Timer Counter SPI1
PWM0 PWM1 PWM2 PWM3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWCK CANRX CANTX
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Signal Description
Table 4-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL
Voltage Regulator Power Supply Input Voltage Regulator Output Flash Power Supply Lines Power Supply Core Power Supply Ground
Power Power Power Power Power Power Ground
3.6V 1.85V 3.6V 3.6V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT PLLRC PCK0 PCK3 Main Oscillator Input Main Oscillator Output Filter Programmable Clock Output Input Output Input Output JTAG JTAGSEL Test Clock Test Data Test Data Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory ERASE Flash Configuration Bits Erase Command Reset/Test NRST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input PA30 PB30 Parallel Controller Parallel Controller Pulled-up input reset Pulled-up input reset Input Input Input Output Input High Pull-Up resistor, Open Drain Output Pull-down resistor Input High Pull-down resistor pull-up resistor. Pull-down resistor. pull-up resistor pull-up resistor.
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Table 4-1.
Signal Name
Signal Description List (Continued)
Function Type Device Port Active Level Comments
Device Port Data Device Port Data USART
Analog Analog
SCK0 SCK1 TXD0 TXD1 RXD0 RXD1 RTS0 RTS1 CTS0 CTS1 DCD1 DTR1 DSR1
Serial Clock Transmit Data Receive Data Request Send Clear Send Data Carrier Detect Data Terminal Ready Data Ready Ring Indicator
Input Output Input Input Output Input Input Synchronous Serial Controller
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input Timer/Counter
TCLK0 TCLK2 TIOA0 TIOA2 TIOB0 TIOB2
External Clock Inputs Line Line
Input Controller
PWM0 PWM3
Channels
Output Serial Peripheral Interface SPIx
SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select
Output
Two-wire Interface TWCK Two-wire Serial Data Two-wire Serial Clock
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Table 4-1.
Signal Name
Signal Description List (Continued)
Function Type Analog-to-Digital Converter Active Level Comments
AD0-AD3 AD4-AD7 ADTRG ADVREF
Analog Inputs Analog Inputs Trigger Reference
Analog Analog Input Analog Fast Flash Programming Interface
Digital pulled-up inputs reset Analog Inputs
PGMEN0-PGMEN1 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD
Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command
Input Input Output Output Input Input Input Controller High
CANRX CANTX
Input Output
Input Output Ethernet 10/100
EREFCK ETXCK ERXCK ETXEN ETX0 ETX3 ETXER ERXDV ECRSDV ERX0 ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force Mbits/sec.
Input Input Input Output Output Output Input Input Input Input Input Input Output Output High
RMII only only only
ETX0 ETX1 only RMII only only RMII only ERX0 ERX1 only RMII
only only
RMII only
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Package
AT91SAM7X256/128 available 100-lead LQFP package.
100-lead LQFP Mechanical Overview
Figure shows orientation 100-lead LQFP package. detailed mechanical description given Mechanical Characteristics section full datasheet. Figure 5-1. 100-lead LQFP Package Pinout (Top View)
AT91SAM7X256/128 Pinout
Pinout 100-lead TQFP Package
PA18/PGMD6 PB14 PB13 VDDIO PB15 PB17 VDDCORE PB12 PB10 PB11 PA19/PGMD7 PA20/PGMD8 VDDIO PA21/PGMD9 PA22/PGMD10 PB16 PA23/PGMD11 PA24/PGMD12 NRST PA25/PGMD13 PA26/PGMD14 VDDIO VDDCORE PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PA27/PGMD15 PA28 PA29 JTAGSEL PA30 PA0/PGMEN0 PA1/PGMEN1 VDDIO VDDCORE PA4/PGMNCMD PA5/PGMRDY PA6/PGMNOE PA7/PGMNVALID ERASE VDDFLASH XIN/PGMCK XOUT PLLRC VDDPLL
Table 5-1.
ADVREF VDDOUT VDDIN PB27/AD0 PB28/AD1 PB29/AD2 PB30/AD3 PA8/PGMM0 PA9/PGMM1 VDDCORE VDDIO PA10/PGMM2 PA11/PGMM3 PA12/PGMD0 PA13/PGMD1 PA14/PGMD2 PA15/PGMD3 PA16/PGMD4 PA17/PGMD5
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Power Considerations
Power Supplies
AT91SAM7X256/128 types power supply pins integrates voltage regulator, allowing device supplied with only voltage. power supply types are: VDDIN pin. powers voltage regulator ADC; voltage ranges from 3.0V 3.6V, 3.3V nominal. order decrease current consumption voltage regulator used, VDDIN, ADVREF, AD5, should connected GND. this case, VDDOUT should left unconnected. VDDOUT pin. output 1.8V voltage regulator. VDDIO pin. powers lines; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDFLASH pin. powers transceivers part Flash required Flash operate correctly; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDCORE pins. They power logic device; voltage ranges from 1.65V 1.95V, 1.8V typical. connected VDDOUT with decoupling capacitor. VDDCORE required device, including embedded Flash, operate correctly. VDDPLL pin. powers oscillator PLL. connected directly VDDOUT pin. separate ground pins provided different power supplies. Only pins provided should connected shortly possible system ground plane.
Power Consumption
AT91SAM7X256/128 static current less than VDDCORE 25°C, including oscillator, voltage regulator power-on reset when brownout detector deactivated. Activating brownout detector adds static current. dynamic power consumption VDDCORE less than full speed when running Flash. Under same conditions, power consumption VDDFLASH does exceed
Voltage Regulator
AT91SAM7X256/128 embeds voltage regulator that managed System Controller. Normal Mode, voltage regulator consumes less than static current draws output current. voltage regulator also Low-power Mode. this mode, consumes less than static current draws output current. Adequate output supply decoupling mandatory VDDOUT reduce ripple avoid oscillations. best achieve this capacitors parallel: external capacitor should connected between VDDOUT close chip possible. external capacitor should connected between VDDOUT GND.
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Adequate input supply decoupling mandatory VDDIN order improve startup stability reduce source voltage drop. input decoupling capacitor should placed close chip. example, capacitors used parallel: X7R.
Typical Powering Schematics
AT91SAM7X256/128 supports 3.3V single supply mode. internal regulator input connected 3.3V source output feeds VDDCORE VDDPLL. Figure shows power schematics used bus-powered systems. Figure 6-1. 3.3V System Single Power Supply Schematic
VDDFLASH Power Source ranges from 4.5V (USB)
DC/DC Converter
VDDIO
VDDIN 3.3V VDDOUT Voltage Regulator
VDDCORE
VDDPLL
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Lines Considerations
JTAG Port Pins
TMS, schmitt trigger inputs tolerant. TMS, integrate pull-up resistor. output, driven VDDIO, pull-up resistor. JTAGSEL used select JTAG boundary scan when asserted high level. JTAGSEL integrates permanent pull-down resistor about GND, that left unconnected normal operations.
Test
used manufacturing test fast programming mode AT91SAM7X256/128 when asserted high. integrates permanent pull-down resistor about GND, that left unconnected normal operations. enter fast programming mode, pins should tied high tied low. Driving high level while driven leads unpredictable results.
Reset
NRST bidirectional with open drain output buffer. handled on-chip reset controller driven provide reset signal external components asserted externally reset microcontroller. There constraint length reset pulse, reset controller guarantee minimum pulse length. This allows connection simple push-button NRST system user reset, signal NRST reset components system. NRST integrates permanent pull-up resistor VDDIO.
ERASE
ERASE used re-initialize Flash content some bits. integrates permanent pull-down resistor about GND, that left unconnected normal operations. This debounced oscillator improve glitch tolerance. Minimum debouncing time
Controller Lines
lines, PA30 PB30, 5V-tolerant integrate programmable pull-up resistor. Programming this pull-up resistor performed independently each line through controllers. 5V-tolerant means that lines drive voltage level according VDDIO, driven with voltage 5.5V. However, driving line with voltage over VDDIO while programmable pull-up resistor enabled lead unpredictable results. Care should taken, particular reset, lines default input with pull-up resistor enabled reset.
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Lines Current Drawing
lines high-drive current capable. Each these lines drive permanently. remaining lines draw only However, total current drawn lines cannot exceed
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Processor Architecture
ARM7TDMI Processor
RISC processor based ARMv4T Neumann architecture Runs MHz, providing MIPS/MHz instruction sets ARM® high-performance 32-bit instruction Thumb® high code density 16-bit instruction Three-stage pipeline architecture Instruction Fetch Instruction Decode Execute
Debug Test Integrated Embedded ICE(embedded in-circuit emulator) watchpoint units Test access port accessible through JTAG protocol Debug communication channel Debug Unit Two-pin UART Debug communication channel interrupt handling Chip Register IEEE1149.1 JTAG Boundary-scan digital pins
Memory Controller
Programmable Arbiter Handles requests from ARM7TDMI, Ethernet Peripheral Controller Address decoder provides selection signals Three internal Mbyte memory areas Mbyte embedded peripheral area Abort Status Registers Source, Type parameters access leading abort saved Facilitates debug detection pointers Misalignment Detector Alignment checking data accesses Abort generation case misalignment Remap Command Remaps SRAM place embedded non-volatile memory Allows handling dynamic exception vectors
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Embedded Flash Controller Embedded Flash interface, three programmable wait states Prefetch buffer, buffering anticipating 16-bit requests, reducing required wait states Key-protected program, erase lock/unlock sequencer Single command erasing, programming locking operations Interrupt generation case forbidden operation
Peripheral Controller
Handles data transfer between peripherals memories Thirteen channels each USART Debug Unit Serial Synchronous Controller each Serial Peripheral Interface Analog-to-digital Converter arbitration overhead Master Clock cycle needed transfer from memory peripheral Master Clock cycles needed transfer from peripheral memory Next Pointer management reducing interrupt latency requirements
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Memory
AT91SAM7X256
Kbytes Flash Memory 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, each protecting sectors pages Protection Mode secure contents Flash Kbytes Fast SRAM Single-cycle access full speed
AT91SAM7X128
Kbytes Flash Memory pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, each protecting sectors pages Protection Mode secure contents Flash Kbytes Fast SRAM Single-cycle access full speed
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9.3.1
Memory Mapping
Internal AT91SAM7X256 embeds high-speed 64-Kbyte SRAM bank AT91SAM7X128 embeds high-speed 32-Kbyte SRAM bank. After reset until Remap Command performed, SRAM only accessible address 0x0020 0000. After Remap, SRAM also becomes available address 0x0.
9.3.2
Internal AT91SAM7X256/128 embeds Internal ROM. time, mapped address 0x30 0000. contains FFPI SAM-BA program.
9.3.3
Internal Flash AT91SAM7X256 features bank Kbytes Flash AT91SAM7X128 features bank Kbytes Flash. time, Flash mapped address 0x0010 0000. also accessible address after reset before Remap Command. general purpose (GPNVM) used boot either (default) from Flash. This GPNVM cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. Setting GPNVM selects boot from Flash. Asserting ERASE clears GPNVM thus selects boot from default. Figure 9-1. Internal Memory Mapping with GPNVM (default)
0x0000 0000
0x000F FFFF
Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Figure 9-2. Internal Memory Mapping with GPNVM
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal FLASH
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes Bytes Bytes
Internal
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
9.4.1
Embedded Flash
Flash Overview Flash AT91SAM7X256 organized 1024 pages bytes. reads 65,536 32-bit words. Flash AT91SAM7X128 organized pages bytes. reads 32,768 32-bit words. Flash contains 256-byte write buffer, accessible through 32-bit interface. Flash benefits from integration power reset cell from brownout detector. This prevents code corruption during power supply changes, even worst conditions. When Flash used (read write access), automatically placed into standby mode.
9.4.2
Embedded Flash Controller Embedded Flash Controller (EFC) manages accesses performed masters system. enables reading Flash writing write buffer. also contains User Interface, mapped within Memory Controller APB. User Interface allows: programming access parameters Flash (number wait states, timings, etc.) starting commands such full erase, page erase, page program, set, clear, etc. getting status last command getting error status programming interrupts last commands errors Embedded Flash Controller also provides dual 32-bit Prefetch Buffer that optimizes 16-bit access Flash. This particularly efficient when processor running Thumb mode.
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9.4.3 9.4.3.1
Lock Regions AT91SAM7X256 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7X256 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash.
9.4.3.2
AT91SAM7X128 Embedded Flash Controller manages lock bits protect regions flash against inadvertent flash erasing programming commands. AT91SAM7X128 contains lock regions each lock region contains pages bytes. Each lock region size Kbytes. locked-region's erase program command occurs, command aborted trigs interrupt. bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash.
9.4.4
Security Feature AT91SAM7X256/128 features security bit, based specific NVM-Bit. When security enabled, access Flash, either through interface through Fast Flash Programming Interface, forbidden. This ensures confidentiality code programmed Flash. This security only enabled, through Command "Set Security Bit" User Interface. Disabling security only achieved asserting ERASE after full flash erase performed. When security deactivated, accesses flash permitted. important note that assertion ERASE should always longer than ERASE integrates permanent pull-down, left unconnected during normal operation. However, safer connect directly final application.
9.4.5
Non-volatile Brownout Detector Control general purpose (GPNVM) bits used controlling brownout detector (BOD), that even after power loss, brownout detector operations remain their state. These GPNVM bits cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface.
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
GPNVM used brownout detector enable bit. Setting GPNVM enables BOD, clearing disables BOD. Asserting ERASE clears GPNVM thus disables brownout detector default. GPNVM used brownout reset enable signal reset controller. Setting GPNVM enables brownout reset when brownout detected, Clearing GPNVM disables brownout reset. Asserting ERASE disables brownout reset default. 9.4.6 Calibration Bits Eight bits used calibrate brownout detector voltage regulator. These bits factory configured cannot changed user. ERASE effect calibration bits.
Fast Flash Programming Interface
Fast Flash Programming Interface allows programming device through either serial JTAG interface through multiplexed fully-handshaked parallel port. allows gang-programming with market-standard industrial programmers. FFPI supports read, page program, page erase, full erase, lock, unlock protect commands. Fast Flash Programming Interface enabled Fast Programming Mode entered when pins tied high.
SAM-BA Boot Assistant
SAM-BA Boot Assistant default Boot Program that provides easy program insitu on-chip Flash memory. SAM-BA Boot Assistant supports serial communication DBGU Device Port. Communication DBGU supports wide range crystals from software auto-detection. Communication Device Port limited 18.432 crystal. SAM-BA Boot provides interface with SAM-BA Graphic User Interface (GUI). SAM-BA Boot mapped Flash address when GPNVM
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System Controller
System Controller manages vital blocks microcontroller: interrupts, clocks, power, time, debug reset. Figure 10-1. System Controller Block Diagram
System Controller
jtag_nreset
Boundary Scan Controller
irq0-irq1 periph_irq[2.19]
nirq
Advanced Interrupt Controller
nfiq proc_nreset debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset gpnvm[0] gpnvm[1] flash_wrdis ice_nreset jtag_nreset bod_rst_en dbgu_irq force_ntrst dbgu_txd
ice_nreset force_ntrst
Debug Unit
security_bit
Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC
pit_irq
flash_poe rtt_irq flash_wrdis wdt_irq gpnvm[0.2]
Embedded Flash
efc_irq proc_nreset
Memory Controller
Reset Controller
periph_nreset proc_nreset
flash_poe rstc_irq SLCK
NRST
Voltage Regulator Mode Controller
standby
Voltage Regulator
RCOSC
SLCK
periph_clk[2.18] pck[0-3]
UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend
XOUT
MAINCK
Power Management Controller
UDPCK
Device Port
PLLRC
PLLCK pmc_irq idle periph_clk[4.19] periph_nreset
periph_nreset usb_suspend
periph_nreset periph_clk[2-3] dbgu_rxd
periph_irq{2-3] irq0-irq1
Embedded Peripherals
periph_irq[4.19]
Controller
dbgu_txd
PA0-PA30 PB0-PB30 enable
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
10.1 System Controller Mapping
System Controller peripherals mapped highest Kbytes address space, between addresses 0xFFFF F000 0xFFFF FFFF. Figure 10-2 shows mapping System Controller. Note that Memory Controller configuration user interface also mapped within this address space. Figure 10-2. System Controller Mapping
Address
0xFFFF F000
Peripheral
Peripheral Name
Size
0xFFFF F1FF 0xFFFF F200
Advanced Interrupt Controller
Bytes/128 registers
DBGU
0xFFFF F3FF 0xFFFF F400
Debug Unit
Bytes/128 registers
PIOA
0xFFFF F5FF 0xFFFF F600
Controller
Bytes/128 registers
PIOB
0xFFFF F7FF 0xFFFF F800
Controller
Bytes/128 registers
Reserved
0xFFFF FBFF 0xFFFF FC00
0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00
Power Management Controller Reset Controller Real-time Timer Periodic Interval Timer Watchdog Timer Voltage Regulator Mode Controller
Bytes/64 registers Bytes/4 registers Bytes/4 registers Bytes/4 registers Bytes/4 registers Bytes/1 register
RSTC Reserved Reserved VREG Reserved
0xFFFF FFFF
Memory Controller
Bytes/64 registers
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10.2
Reset Controller
Based power-on reset cell brownout detector Status last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset Controls internal resets NRST output Allows shape signal NRST line, guaranteeing that length pulse meets requirement.
10.2.1
Brownout Detector Power-on Reset AT91SAM7X256/X128 embeds brownout detection circuit power-on reset cell. power-on reset supplied with monitors VDDCORE. Both signals provided Flash prevent code corruption during power-up powerdown sequences brownouts occur power supplies. power-on reset cell limited-accuracy threshold around 1.5V. output remains during power-up until VDDCORE goes over this voltage level. This signal goes reset controller allows full re-initialization device. brownout detector monitors VDDCORE VDDFLASH levels during operation comparing them fixed trigger level. secures system operations most difficult environments prevents code corruption case brownout VDDCORE VDDFLASH. When brownout detector enabled VDDCORE decreases value below trigger level (Vbot18-, defined Vbot18 hyst/2), brownout output immediately activated. When VDDCORE increases above trigger level (Vbot18+, defined Vbot18 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDCORE threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 1.68V with accuracy factory calibrated. When brownout detector enabled VDDFLASH decreases value below trigger level (Vbot33-, defined Vbot33 hyst/2), brownout output immediately activated. When VDDFLASH increases above trigger level (Vbot33+, defined Vbot33 hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. VDDFLASH threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 2.80V with accuracy 3.5% factory calibrated. brownout detector low-power, consumes less than static current. However, deactivated save static current. this case, consumes less than 1µA. deactivation configured through GPNVM Flash.
AT91SAM7X256/128 Preliminary
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10.3 Clock Generator
Clock Generator embeds low-power Oscillator, Main Oscillator with following characteristics: Oscillator ranges between Main Oscillator frequency ranges between Main Oscillator bypassed output ranges between provides SLCK, MAINCK PLLCK. Figure 10-3. Clock Generator Block Diagram
Clock Generator
Embedded Oscillator
Slow Clock SLCK
XOUT
Main Oscillator
Main Clock MAINCK
PLLRC
Divider
Clock PLLCK
Status
Control
Power Management Controller
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10.4
Power Management Controller
Power Management Controller uses Clock Generator outputs provide: Processor Clock Master Clock Clock UDPCK peripheral clocks, independently controllable four programmable clock outputs Master Clock (MCK) programmable from hundred maximum operating frequency device. Processor Clock (PCK) switches when entering processor idle mode, thus allowing reduced power consumption while waiting interrupt. Figure 10-4. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64 Peripherals Clock Controller ON/OFF Idle Mode
periph_clk[2.18]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64
pck[0.3]
Clock Controller ON/OFF PLLCK Divider /1,/2,/4
UDPCK
10.5
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control peripheral interrupts external interrupts Programmable edge-triggered level-sensitive internal sources Programmable positive/negative edge-triggered high/low level-sensitive external sources 8-level Priority Controller Drives normal interrupt nIRQ processor Handles priority interrupt sources
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Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes interrupt service routine branch execution 32-bit vector register interrupt source Interrupt vector register reads corresponding current interrupt vector Protect Mode Easy debugging preventing automatic operations Fast Forcing Permits redirecting interrupt source fast interrupt General Interrupt Mask Provides processor synchronization events without triggering interrupt
10.6
Debug Unit
Comprises: two-pin UART Interface Debug Communication Channel (DCC) support Chip Registers Interface providing Access Prevention Two-pin UART USART-compatible User Interface Programmable Baud Rate Generator Parity, Framing Overrun Error Automatic Echo, Local Loopback Remote Loopback Channel Modes Debug Communication Channel Support Offers visibility COMMRX COMMTX signals from Processor Chip Registers Identification device revision, sizes embedded memories, peripherals Chip 0x275B 0940 (VERSION AT91SAM7X256 Chip 0x275A 0740 (VERSION AT91SAM7X128
10.7
Period Interval Timer
20-bit programmable counter plus 12-bit interval counter
10.8
Watchdog Timer
12-bit key-protected Programmable Counter running prescaled SLCK Provides reset interrupt signals system Counter stopped while processor debug state idle mode
10.9
Real-time Timer
32-bit free-running counter with alarm running prescaled SLCK Programmable 16-bit prescaler SLCK accuracy compensation
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10.10 Controllers
Controllers, each controlling lines Fully programmable through set/clear registers Multiplexing peripheral functions line each line (whether assigned peripheral used general-purpose I/O) Input change interrupt Half clock period glitch filter Multi-drive option enables driving open drain Programmable pull-up each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
10.11 Voltage Regulator Controller
purpose this controller select Power Mode Voltage Regulator between Normal Mode (bit cleared) Standby Mode (bit set).
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Peripherals
11.1 Peripheral Mapping
Each peripheral allocated Kbytes address space. Figure 11-1. User Peripheral Mapping
Peripheral Name
0xF000 0000
Size
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
TC0, TC1,
Timer/Counter
Kbytes
0xFFFA 4000 Reserved
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF 0xFFFB 4000
Device Port
Kbytes
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
Two-Wire Interface
Kbytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART0
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter
Kbytes Kbytes
0xFFFC 4000 USART1
0xFFFC 7FFF
0xFFFC 8000 Reserved
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF
Controller
Kbytes
0xFFFD 0000
0xFFFD 3FFF
Controller
Kbytes
0xFFFD 4000
0xFFFD 7FFF
Serial Synchronous Controller Analog-to-Digital Converter
Kbytes Kbytes
0xFFFD 8000
0xFFFD BFFF
0xFFFD C000
0xFFFD FFFF
EMAC
Ethernet Serial Peripheral Interface
Kbytes Kbytes
0xFFFE 0000
0xFFFE 3FFF
SPI0
0xFFFE 4000
0xFFFE 7FFF 0xFFFE 8000
SPI1
Serial Peripheral Interface
Kbytes
Reserved
0xFFFE FFFF
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11.2
Peripheral Multiplexing Lines
AT91SAM7X256/128 features controllers, PIOA PIOB, that multiplex lines peripheral set. Each Controller controls lines. Each line assigned peripheral functions, Some them also multiplexed with analog inputs Controller. Table 11-1 page Table 11-2 page defines lines peripherals analog inputs multiplexed Controller Controller columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. Note that some peripheral functions that output only, duplicated table. reset, lines automatically configured input with programmable pull-up enabled, that device maintained static state soon reset detected.
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11.3 Controller Multiplexing
Table 11-1.
Multiplexing Controller
Controller Application Usage Comments High-Drive High-Drive SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 High-Drive High-Drive Function Comments
Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30
Peripheral RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 TWCK SPI_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK CANRX CANTX DRXD DTXD IRQ0
Peripheral
SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3
PCK1 IRQ1 TCLK2
SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 PCK3
SPI1_NPCS3 PCK2
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11.4
Controller Multiplexing
Table 11-2.
Multiplexing Controller
Controller Application Usage Comments Function Comments
Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30
Peripheral ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS ERX0 ERX1 ERXER EMDC EMDIO ETX2 ETX3 ETXER ERX2 ERX3 ERXDV/ECRSDV ECOL ERXCK EF100 PWM0 PWM1 PWM2 PWM3 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 PCK1 PCK2
Peripheral PCK0
SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2
SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 PWM0 PWM1 PWM2 PWM3
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11.5 Peripheral Identifiers
AT91SAM7X256/128 embeds wide range peripherals. Table 11-3 defines Peripheral Identifiers AT91SAM7X256/128. Unique peripheral identifiers defined both Advanced Interrupt Controller Power Management Controller.
Table 11-3.
Peripheral
Peripheral Identifiers
Peripheral Mnemonic SYSIRQ PIOA PIOB SPI0 SPI1 PWMC EMAC
Peripheral Name Advanced Interrupt Controller
External Interrupt
Parallel Controller Parallel Controller Serial Peripheral Interface Serial Peripheral Interface USART USART Synchronous Serial Controller Two-wire Interface Pulse Width Modulation Controller device Port Timer/Counter Timer/Counter Timer/Counter Controller Ethernet Analog-to Digital Converter
Reserved Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1
Note:
Setting SYSIRQ bits clock set/clear registers effect. System Controller continuously clocked.
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11.6
Ethernet
Master Receive Transmit Channels Compatible with IEEE Standard 802.3 Mbit/s operation Full- half-duplex operation Statistics Counter Registers MII/RMII interface physical layer Interrupt generation signal receive transmit completion 28-byte transmit FIFO 28-byte receive FIFO Automatic generation transmitted frames Automatic discard frames received with errors Address checking logic supports four specific 48-bit addresses Support Promiscuous Mode where valid received frames copied memory Hash matching unicast multicast destination addresses Physical layer management through MDIO interface Half-duplex flow control forcing collisions incoming frames Full-duplex flow control with recognition incoming pause frames Support 802.1Q VLAN tagging with recognition incoming VLAN priority tagged frames Multiple buffers receive transmit frame Jumbo frames 10240 bytes supported
11.7
Serial Peripheral Interface
Supports communication with external serial devices Four chip selects with external decoder allow communication with peripherals Serial memories, such DataFlash® 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays chip select, between consecutive transfers between clock data Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency Master Clock
11.8
Two-wire Interface
Master Mode only Compatibility with standard two-wire serial memories
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One, three bytes slave address Sequential read/write operations
11.9
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection first Optional break generation detection over-sampling receiver frequency Hardware handshaking Modem Signals Management DTR-DSR-DCD-RI USART1 Receiver time-out transmitter timeguard Multi-drop Mode with address generation detection RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo
11.10 Serial Synchronous Controller
Provides serial synchronous communication links used audio telecom applications Contains independent receiver transmitter common clock divider Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal
11.11 Timer Counter
Three 16-bit Timer Counter Channels Three output compare input capture Wide range functions including: Frequency measurement Event counting Interval measurement Pulse generation
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Delay timing Pulse Width Modulation Up/down capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs, defined Table 11-4 Table 11-4. Timer Counter Clocks Assignment
Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5
multi-purpose input/output signals global registers that three channels
11.12 Pulse Width Modulation Controller
Four channels, 16-bit counter channel Common clock generator, providing thirteen different clocks Modulo counter providing eleven clocks independent linear dividers working modulo counter outputs Independent channel programming Independent enable/disable commands Independent clock selection Independent period duty cycle, with double buffering Programmable selection output waveform polarity Programmable center left aligned output waveform
11.13 Device Port
V2.0 full-speed compliant,12 Mbits second Embedded V2.0 full-speed transceiver Embedded 1352-byte dual-port endpoints endpoints Endpoint bytes Endpoint bytes ping-pong Endpoint bytes Endpoint bytes ping-pong Ping-pong Mode (two memory banks) bulk endpoints Suspend/resume logic
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11.14 Controller
Fully compliant with 2.0A 2.0B rates 1Mbit/s Eight object oriented mailboxes each with following properties: Specification Part Part Programmable each Message Object configurable receive (with overwrite not) transmit Local mask filters 29-bit identifier/channel 32-bit access data registers each mailbox data object Uses 16-bit time stamp receive transmit message Hardware concatenation unmasked bitfields speedup family processing 16-bit internal timer time stamping network synchronization Programmable reception buffer length mailbox objects Priority management between transmission mailboxes Autobaud listening mode power mode programmable wake-up activity application Data, remote, error overload frame handling
11.15 Analog-to-Digital Converter
8-channel 10-bit Ksamples/sec. Successive Approximation Register -3/+3 Integral Linearity, -2/+2 Differential Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs External voltage reference better accuracy voltage inputs Individual enable disable each channel Multiple trigger sources Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 trigger Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Four eight analog inputs shared with digital signals
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ARM7TDMI Processor Overview
12.1 Overview
ARM7TDMI core executes both 32-bit ARM® 16-bit Thumb® instruction sets, allowing user trade between high performance high code density.The ARM7TDMI processor implements Neuman architecture, using three-stage pipeline consisting Fetch, Decode, Execute stages. main features ARM7tDMI processor are: ARM7TDMI Based ARMv4T Architecture Instruction Sets ARM® High-performance 32-bit Instruction Thumb® High Code Density 16-bit Instruction Three-Stage Pipeline Architecture Instruction Fetch Instruction Decode Execute
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12.2
ARM7TDMI Processor
further details ARM7TDMI, refer following documents: Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B)
12.2.1
Instruction Type Instructions either bits long state) bits long THUMB state).
12.2.2
Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) word (32-bit) data types. Words must aligned four-byte boundaries half words two-byte boundaries. Unaligned data access behavior depends which instruction used where.
12.2.3
ARM7TDMI Operating Mode ARM7TDMI, based architecture v4T, supports seven processor modes: User: normal program execution state FIQ: Designed support high-speed data transfer channel process IRQ: Used general-purpose interrupt handling Supervisor: Protected mode operating system Abort mode: Implements virtual memory and/or memory protection System: privileged user mode operating system Undefined: Supports software emulation hardware coprocessors Mode changes made under software control, brought about external interrupts exception processing. Most application programs execute User mode. non-user modes, privileged modes, entered order service interrupts exceptions, access protected resources.
12.2.4
ARM7TDMI Registers ARM7TDMI processor total 37registers: general-purpose 32-bit registers status registers These registers accessible same time. processor state operating mode determine which registers available programmer. time registers visible user. remainder synonyms used speed exception processing. Register Program Counter (PC) used instructions reference data relative current instruction. holds return address after subroutine call. used software convention) stack pointer.
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Table 12-1.
User System Mode
ARM7TDMI Modes Registers Layout
Supervisor Mode
R13_SVC R14_SVC
Abort Mode
R13_ABORT R14_ABORT
Undefined Mode
R13_UNDEF R14_UNDEF
Interrupt Mode
R13_IRQ R14_IRQ
Fast Interrupt Mode
R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABORT
CPSR SPSR_UNDEF
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
Registers unbanked registers. This means that each them refers same 32bit physical register processor modes. They general-purpose registers, with special uses managed architecture, used wherever instruction allows generalpurpose register specified. Registers banked registers. This means that each them depends current mode processor. 12.2.4.1 Modes Exception Handling exceptions have banked registers R13. After exception, holds return address exception processing. This address used return after exception processed, well address instruction that caused exception. banked across exception modes provide each exception handler with private stack pointer. fast interrupt mode also banks registers that interrupt processing begin without having save these registers.
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seventh processing mode, System Mode, does have banked registers. uses User Mode registers. System Mode runs tasks that require privileged processor mode allows them invoke classes exceptions. 12.2.4.2 Status Registers other processor states held status registers. current operating processor status Current Program Status Register (CPSR). CPSR holds: four flags (Negative, Zero, Carry, Overflow) interrupt disable bits (one each type interrupt) indicate Thumb execution five bits encode current processor mode five exception modes also have Saved Program Status Register (SPSR) that holds CPSR task immediately preceding exception. 12.2.4.3 Exception Types
ARM7TDMI supports five types exception privileged processing mode each type.
types exceptions are: fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used implement memory protection virtual memory) attempted execution undefined instruction software interrupts (SWIs) Exceptions generated internal external sources. More than exception occur same time. When exception occurs, banked version SPSR exception mode used save state. return after handling exception, SPSR moved CPSR, moved This done ways: using data-processing instruction with S-bit set, destination using Load Multiple with Restore CPSR instruction (LDM) 12.2.5 Instruction Overview instruction divided into: Branch instructions Data processing instructions Status register transfer instructions Load Store instructions Coprocessor instructions Exception-generating instructions instructions executed conditionally. Every instruction contains 4-bit condition code field (bit[31:28]). Table 12-2 gives instruction mnemonic list.
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Table 12-2.
Mnemonic
SMULL SMLAL LDRSH LDRSB LDRH LDRB LDRBT LDRT
Instruction Mnemonic List
Operation
Move Subtract Reverse Subtract Compare Test Logical Logical Exclusive Multiply Sign Long Multiply Signed Long Multiply Accumulate Move Status Register Branch Branch Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move Coprocessor Load Coprocessor
Mnemonic
UMULL UMLAL STRH STRB STRBT STRT SSWPB
Operation
Coprocessor Data Processing Move with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Clear Logical (inclusive) Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor
12.2.6
Thumb Instruction Overview Thumb instruction re-encoded subset instruction set. Thumb instruction divided into: Branch instructions Data processing instructions Load Store instructions Load Store Multiple instructions Exception-generating instruction Thumb mode, eight general-purpose registers, available that same physical registers when executing instructions. Some Thumb instructions also access Program Counter (ARM Register 15), Link Register (ARM Register
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Stack Pointer (ARM Register 13). Further instructions allow limited access registers Table 12-3 gives Thumb instruction mnemonic list. Table 12-3.
Mnemonic
LDRH LDRB LDRSH LDMIA PUSH
Thumb Instruction Mnemonic List
Operation
Move Subtract Compare Test Logical Logical Exclusive Logical Shift Left Arithmetic Shift Right Multiply Branch Branch Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register stack STRH STRB LDRSB STMIA Branch Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Register from stack
Mnemonic
Operation
Move with Carry Subtract with Carry Compare Negated Negate Clear Logical (inclusive) Logical Shift Right Rotate Right
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Debug Test 13.1 Description
AT91SAM7X Series features number complementary debug test capabilities. common JTAG/ICE (In-Circuit Emulator) port used standard debugging functions, such downloading code single-stepping through programs. Debug Unit provides two-pin UART that used upload application into internal SRAM. manages interrupt handling internal COMMTX COMMRX signals that trace activity Debug Communication Channel. dedicated debug test input/output pins gives direct access these capabilities from PC-based test environment.
13.2
Block Diagram
Figure 13-1. Debug Test Block Diagram
Boundary
ICE/JTAG
JTAGSEL
Reset Test
ARM7TDMI
DTXD DRXD
DBGU
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13.3
13.3.1
Application Examples
Debug Environment Figure 13-2 shows complete debug environment example. ICE/JTAG interface used standard debugging functions, such downloading code single-stepping through program. Figure 13-2. Application Debug Environment Example
Host Debugger ICE/JTAG Interface
ICE/JTAG Connector
AT91SAM7Xxx
RS232 Connector
Terminal
AT91SAM7Xxx-based Application Board
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13.3.2 Test Environment Figure 13-3 shows test environment example. Test vectors sent interpreted tester. this example, "board test" designed using number JTAG-compliant devices. These devices connected form single scan chain. Figure 13-3. Application Test Environment Example
Test Adaptor
Tester
JTAG Interface
ICE/JTAG Connector
Chip
Chip
AT91SAM7Xxx
Chip
AT91SAM7Xxx-based Application Board Test
13.4
Debug Test Description
Table 13-1.
Name
Debug Test List
Function Reset/Test Type Active Level
NRST
Microcontroller Reset Test Mode Select JTAG
Input/Output Input
High
JTAGSEL
Test Clock Test Data Test Data Test Mode Select JTAG Selection Debug Unit
Input Input Output Input Input
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
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13.5
13.5.1
Functional Description
Test dedicated pin, TST, used define device operating mode. user must make sure that this tied level ensure normal operating conditions. Other values associated with this reserved manufacturing test.
13.5.2
Embedded ICE(Embedded In-circuit Emulator) ARM7TDMI Embedded supported ICE/JTAG port. internal state ARM7TDMI examined through ICE/JTAG port. ARM7TDMI processor contains hardware extensions advanced debugging features: halt mode, store-multiple (STM) inserted into instruction pipeline. This exports contents ARM7TDMI registers. This data serially shifted without affecting rest system. monitor mode, JTAG interface used transfer data between debugger simple monitor program running ARM7TDMI processor. There three scan chains inside ARM7TDMI processor that support testing, debugging, programming Embedded ICE. scan chains controlled ICE/JTAG port. Embedded mode selected when JTAGSEL low. possible switch directly between JTAG operations. chip reset must performed after JTAGSEL changed. further details Embedded ICE, ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).
13.5.3
Debug Unit Debug Unit provides two-pin (DXRD TXRD) USART that used several debug trace purposes offers ideal means in-situ programming solutions debug monitor communication. Moreover, association with peripheral data controller channels permits packet handling these tasks with processor time reduced minimum. Debug Unit also manages interrupt handling COMMTX COMMRX signals that come from that trace activity Debug Communication Channel. Debug Unit allows blockage access system through interface. specific register, Debug Unit Chip Register, gives information about product version internal configuration. AT91SAM7X256 Debug Unit Chip value 0x275B 0940 32-bit width. AT91SAM7X128 Debug Unit Chip value 0x275A 0740 32-bit width. further details Debug Unit, Debug Unit section.
13.5.4
IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent device packaging technology. IEEE 1149.1 JTAG Boundary Scan enabled when JTAGSEL high. SAMPLE, EXTEST BYPASS functions implemented. debug mode, processor responds
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with non-JTAG chip that identifies processor system. This IEEE 1149.1 JTAG-compliant. possible switch directly between JTAG operations. chip reset must performed after JTAGSEL changed. Boundary-scan Descriptor Language (BSDL) file provided test. 13.5.4.1 JTAG Boundary-scan Register Boundary-scan Register (BSR) contains bits that correspond active pins associated control signals. Each AT91SAM7X input/output corresponds 3-bit register BSR. OUTPUT contains data that forced pad. INPUT facilitates observability data applied pad. CONTROL selects direction pad. Table 13-2.
Number PA6/TXD1 IN/OUT PA5/RXD1 IN/OUT PA4/CTS0/SPI1_NPCS3 IN/OUT PA2/SCK0/SPI1_NPCS1 IN/OUT PA3/RTS0/SPI1_NPCS2 IN/OUT PA1/TXD0 IN/OUT PA0/RXD0 IN/OUT PA30/IRQ0/PCK2 IN/OUT
AT91SAM7X JTAG Boundary Scan Register
Name Type Associated Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL CONTROL INPUT OUTPUT
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Table 13-2.
Number
AT91SAM7X JTAG Boundary Scan Register (Continued)
Name Type Associated Cells CONTROL PA7/SCK1/SPI0_NPCS1 IN/OUT INPUT OUTPUT ERASE INPUT INPUT PB27/TIOA2/PWM0/AD0 IN/OUT OUTPUT CONTROL INPUT PB28/TIOB2/PWM1/AD1 IN/OUT OUTPUT CONTROL INPUT PB29/PCK1/PWM2/AD2 IN/OUT OUTPUT CONTROL INPUT PB30/PCK2/PWM3/AD3 IN/OUT OUTPUT CONTROL INPUT PA8/RTS1/SPI0_NPCS2 IN/OUT OUTPUT CONTROL INPUT PA9/CTS1/SPI0_NPCS3 IN/OUT OUTPUT CONTROL INPUT PA10/TWD IN/OUT OUTPUT CONTROL INPUT PA11/TWCK IN/OUT OUTPUT CONTROL INPUT PA12/SPI0_NPCS0 IN/OUT OUTPUT CONTROL INPUT PA13/SPI0_NPCS1/PCK1 IN/OUT OUTPUT CONTROL
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Table 13-2.
Number PB5/ERX0 IN/OUT PB6/ERX1 IN/OUT PB13/ERX2/SPI0_NPCS1 IN/OUT PB14/ERX3/SPI0_NPCS2 IN/OUT PB8/EMDC IN/OUT PB9/EMDIO IN/OUT PA18/SPI0_SPCK IN/OUT PA17/SPI0_MOSI IN/OUT PA16/SPI0_MISO IN/OUT PA15/SPI0_NPCS3/TCLK2 IN/OUT PA14/SPI0_NPCS2/IRQ1 IN/OUT
AT91SAM7X JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 13-2.
Number
AT91SAM7X JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PB15/ERXDV/ECRSDV IN/OUT OUTPUT CONTROL INPUT PB17/ERXCK/SPI0_NPCS3 IN/OUT OUTPUT CONTROL INPUT PB7/ERXER IN/OUT OUTPUT CONTROL INPUT PB12/ETXER/TCLK0 IN/OUT OUTPUT CONTROL INPUT PB0/ETXCK/EREFCK/PCK0 PB0/ETXCK/ERE FCK/PCK0 OUTPUT CONTROL INPUT PB1/ETXEN PB1/ETXEN OUTPUT CONTROL INPUT PB2/ETX0 PB2/ETX0 OUTPUT CONTROL INPUT PB3/ETX1 PB3/ETX1 OUTPUT CONTROL INPUT PB10/ETX2/SPI1_NPCS1 IN/OUT OUTPUT CONTROL INPUT PB11/ETX3/SPI1_NPCS2 IN/OUT OUTPUT CONTROL INPUT PA19/CANRX IN/OUT OUTPUT CONTROL
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Table 13-2.
Number PB19/PWM0/TCLK1 IN/OUT PB18/EF100/ADTRG IN/OUT PA26/RF/SPI1_NPCS2 IN/OUT PA25/RK/SPI1_NPCS1 IN/OUT PA24/RD/SPI1_MISO IN/OUT PA23/TD/SPI1_MOSI IN/OUT PB4/ECRS IN/OUT PB16/ECOL/SPI1_NPCS3 IN/OUT PA22/TK/SPI1_SPCK IN/OUT PA21/TF/SPI1_NPCS0 IN/OUT PA20/CANTX IN/OUT
AT91SAM7X JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 13-2.
Number
AT91SAM7X JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PB20/PWM1/PCK0 IN/OUT OUTPUT CONTROL INPUT PB21/PWM2/PCK2 IN/OUT OUTPUT CONTROL INPUT PB22/PWM3/PCK2 IN/OUT OUTPUT CONTROL INPUT PB23/TIOA0/DCD1 IN/OUT OUTPUT CONTROL INPUT PB24/TIOB0/DSR1 IN/OUT OUTPUT CONTROL INPUT PB25/TIOA1/DTR1 IN/OUT OUTPUT CONTROL INPUT PB26/TIOB1/RI1 IN/OUT OUTPUT CONTROL INPUT PA27DRXD/PCK3 IN/OUT OUTPUT CONTROL INPUT PA28/DTXD IN/OUT OUTPUT CONTROL INPUT PA29/FIQ/SPI1_NPCS3 IN/OUT OUTPUT CONTROL
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13.5.5 Code Register Access: Read-only
VERSION
PART NUMBER
PART NUMBER
PART NUMBER
MANUFACTURER IDENTITY
MANUFACTURER IDENTITY
VERSION[31:28]: Product Version Number 0x0. PART NUMBER[27:12]: Product Part Number AT91SAM7X256: 0x5B17 AT91SAM7X128: 0x5B16 MANUFACTURER IDENTITY[11:1] 0x01F. Bit[0] Required IEEE Std. 1149.1. 0x1. AT91SAM7X256: JTAG Code value 05B1_003F AT91SAM7X128: JTAG Code value 05B0_F03F
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Reset Controller (RSTC)
14.1 Overview
Reset Controller (RSTC), based power-on reset cells, handles resets system without external components. reports which reset occurred last. Reset Controller also drives independently simultaneously external reset peripheral processor resets. brownout detection also available prevent processor from falling into unpredictable state.
14.2
Block Diagram
Figure 14-1. Reset Controller Block Diagram
Reset Controller
bod_rst_en brown_out Brownout Manager
bod_reset
Main Supply
Startup Counter
Reset State Manager
rstc_irq
proc_nreset
user_reset
NRST
nrst_out
NRST Manager
exter_nreset
periph_nreset
WDRPROC wd_fault
SLCK
6120C-ATARM-25-Oct-05
14.3
Functional Description
Reset Controller made NRST Manager, Brownout Manager, Startup Counter Reset State Manager. runs Slow Clock generates following reset signals: proc_nreset: Processor reset line. also resets Watchdog Timer. periph_nreset: Affects whole embedded peripherals. nrst_out: Drives NRST pin. These reset signals asserted Reset Controller, either external events software action. Reset State Manager controls generation reset signals provides signal NRST Manager when assertion NRST required. NRST Manager shapes NRST assertion during programmable time, thus controlling external device resets.
14.3.1
NRST Manager NRST Manager samples NRST input drives this when required Reset State Manager. Figure 14-2 shows block diagram NRST Manager. Figure 14-2. NRST Manager
RSTC_MR RSTC_SR
URSTIEN rstc_irq
RSTC_MR
URSTS NRSTL
Other interrupt sources user_reset
URSTEN
NRST
RSTC_MR
ERSTL nrst_out External Reset Timer exter_nreset
14.3.1.1
NRST Signal Interrupt NRST Manager samples NRST Slow Clock speed. When line detected low, User Reset reported Reset State Manager. However, NRST Manager programmed trigger reset when assertion NRST occurs. Writing URSTEN RSTC_MR disables User Reset trigger. level NRST read time NRSTL (NRST level) RSTC_SR. soon NRST asserted, URSTS RSTC_SR set. This clears only when RSTC_SR read. Reset Controller also programmed generate interrupt instead generating reset. URSTIEN RSTC_MR must written
14.3.1.2
NRST External Reset Control Reset State Manager asserts signal ext_nreset assert NRST pin. When this occurs, "nrst_out" signal driven NRST Manager time programmed field ERSTL RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
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2(ERSTL+1) Slow Clock cycles. This gives approximate duration assertion between seconds. Note that ERSTL defines two-cycle duration NRST pulse. This feature allows Reset Controller shape NRST level, thus guarantee that NRST line driven time compliant with potential external devices connected system reset. 14.3.2 Brownout Manager Brownout detection prevents processor from falling into unpredictable state power supply drops below certain level. When VDDCORE drops below brownout threshold, brownout manager requests brownout reset asserting bod_reset signal. programmer disable brownout reset setting bod_rst_en input signal, i.e.; locking corresponding general-purpose Flash. When brownout reset disabled, reset performed. Instead, brownout detection reported BODSTS RSTC_SR. BODSTS clears only when RSTC_SR read. BODSTS trigger interrupt BODIEN RSTC_MR. factory, brownout reset disabled. Figure 14-3. Brownout Manager
bod_rst_en bod_reset
RSTC_MR
BODIEN
RSTC_SR
brown_out
BODSTS
Other interrupt sources
rstc_irq
6120C-ATARM-25-Oct-05
14.3.3
Reset States Reset State Manager handles different reset sources generates internal reset signals. reports reset status field RSTTYP Status Register (RSTC_SR). update field RSTTYP performed when processor reset released.
14.3.3.1
Power-up Reset When VDDCORE powered Main Supply cell output filtered with start-up counter that operates Slow Clock. purpose this counter ensure that Slow Clock oscillator stable before starting device. startup time, shown Figure 14-4, hardcoded comply with Slow Clock Oscillator startup time. After startup time, reset signals released field RSTTYP RSTC_SR reports Power-up Reset. When VDDCORE detected Main Supply Cell, reset signals asserted immediately.
Figure 14-4. Power-up Reset
SLCK Main Supply output proc_nreset periph_nreset
Freq.
Startup Time
Processor Startup cycles
NRST (nrst_out)
EXTERNAL RESET LENGTH cycles
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14.3.3.2 User Reset User Reset entered when level detected NRST URSTEN RSTC_MR NRST input signal resynchronized with SLCK insure proper behavior system. User Reset entered soon level detected NRST. Processor Reset Peripheral Reset asserted. User Reset left when NRST rises, after two-cycle resynchronization time threecycle processor startup. processor clock re-enabled soon NRST confirmed high. When processor reset signal released, RSTTYP field Status Register (RSTC_SR) loaded with value 0x4, indicating User Reset. NRST Manager guarantees that NRST line asserted EXTERNAL_RESET_LENGTH Slow Clock cycles, programmed field ERSTL. However, NRST does rise after EXTERNAL_RESET_LENGTH because driven externally, internal reset lines remain asserted until NRST actually rises. Figure 14-5. User Reset State
SLCK
Freq.
NRST
Resynch. cycles Resynch. cycles Processor Startup cycles
proc_nreset RSTTYP periph_nreset User Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH
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14.3.3.3
Brownout Reset When brown_out/bod_reset signal asserted, Reset State Manager immediately enters Brownout Reset. this state, processor, peripheral external reset lines asserted. Brownout Reset left Slow Clock cycles after rising edge brown_out/bod_reset after two-cycle resynchronization. external reset also triggered. When processor reset released, field RSTTYP RSTC_SR loaded with value 0x5, thus indicating that last reset Brownout Reset.
Figure 14-6. Brownout Reset State
SLCK brown_out bod_reset
Resynch. cycles Processor Startup cycles
Freq.
proc_nreset RSTTYP periph_nreset Brownout Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH cycles (ERSTL=2)
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14.3.3.4 Software Reset Reset Controller offers several commands used assert different reset signals. These commands performed writing Control Register (RSTC_CR) with following bits PROCRST: Writing PROCRST resets processor watchdog timer. PERRST: Writing PERRST resets embedded peripherals, including memory system, and, particular, Remap Command. Peripheral Reset generally used debug purposes. EXTRST: Writing EXTRST asserts NRST during time defined field ERSTL Mode Register (RSTC_MR). software reset entered least these bits software. these commands performed independently simultaneously. software reset lasts Slow Clock cycles. internal reset signals asserted soon register write performed. This detected Master Clock (MCK). They released when software reset left, i.e.; synchronously SLCK. EXTRST set, nrst_out signal asserted depending programming field ERSTL. However, resulting falling edge NRST does lead User Reset. only PROCRST set, Reset Controller reports software status field RSTTYP Status Register (RSTC_SR). Other Software Resets reported RSTTYP. soon software operation detected, SRCMP (Software Reset Command Progress) Status Register (RSTC_SR). cleared soon software reset left. other software reset performed while SRCMP set, writing value RSTC_CR effect. Figure 14-7. Software Reset
SLCK
Freq.
Write RSTC_CR
Resynch. cycle Processor Startup cycles
proc_nreset PROCRST=1 RSTTYP periph_nreset PERRST=1 NRST (nrst_out) EXTRST=1
EXTERNAL RESET LENGTH cycles (ERSTL=2)
Software Reset
SRCMP RSTC_SR
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14.3.3.5
Watchdog Reset Watchdog Reset entered when watchdog fault occurs. This state lasts Slow Clock cycles. When Watchdog Reset, assertion reset signals depends WDRPROC WDT_MR: WDRPROC Processor Reset Peripheral Reset asserted. NRST line also asserted, depending programming field ERSTL. However, resulting level NRST does result User Reset state. WDRPROC only processor reset asserted. Watchdog Timer reset proc_nreset signal. watchdog fault always causes processor reset WDRSTEN set, Watchdog Timer always reset after Watchdog Reset, Watchdog enabled default with period maximum. When WDRSTEN WDT_MR reset, watchdog fault impact reset controller. Figure 14-8. Watchdog Reset
SLCK
Freq.
wd_fault
Processor Startup cycles
proc_nreset RSTTYP periph_nreset Only WDRPROC Watchdog Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH cycles (ERSTL=2)
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14.3.4 Reset State Priorities Reset State Manager manages following priorities between different reset sources, given descending order: Power-up Reset Brownout Reset Watchdog Reset Software Reset User Reset Particular cases listed below: When User Reset: watchdog event impossible because Watchdog Timer being reset proc_nreset signal. software reset impossible, since processor reset being activated. When Software Reset: watchdog event priority over current state. NRST effect. When Watchdog Reset: processor reset active Software Reset cannot programmed. User Reset cannot entered. 14.3.5 Reset Controller Status Register Reset Controller status register (RSTC_SR) provides several status fields: RSTTYP field: This field gives type last reset, explained previous sections. SRCMP bit: This field indicates that Software Reset Command progress that further software reset should performed until current one. This automatically cleared current software reset. NRSTL bit: NRSTL Status Register gives level NRST sampled each rising edge. URSTS bit: high-to-low transition NRST sets URSTS RSTC_SR register. This transition also detected Master Clock (MCK) rising edge (see Figure 14-9). User Reset disabled (URSTEN interruption enabled URSTIEN RSTC_MR register, URSTS triggers interrupt. Reading RSTC_SR status register resets URSTS clears interrupt. BODSTS bit: This indicates brownout detection when brownout reset disabled (bod_rst_en triggers interrupt BODIEN RSTC_MR register enables interrupt. Reading RSTC_SR register resets BODSTS clears interrupt.
6120C-ATARM-25-Oct-05
Figure 14-9.
Reset Controller Status Interrupt
read RSTC_SR
Peripheral Access
cycle resynchronization NRST NRSTL
cycle resynchronization
URSTS rstc_irq (URSTEN (URSTIEN
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14.4 Reset Controller (RSTC) User Interface
Reset Controller (RSTC) Register Mapping
Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0000 0x0000_0000
Table 14-1.
Offset 0x00 0x04 0x08
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14.4.1
Reset Controller Control Register RSTC_CR Write-only
EXTRST PERRST PROCRST
Register Name: Access Type:
PROCRST: Processor Reset effect. correct, resets processor. PERRST: Peripheral Reset effect. correct, resets peripherals. EXTRST: External Reset effect. correct, asserts NRST pin. KEY: Password Should written value 0xA5. Writing other value this field aborts write operation.
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14.4.2 Reset Controller Status Register RSTC_SR Read-only
SRCMP RSTTYP BODSTS NRSTL
Register Name: Access Type:
URSTS
URSTS: User Reset Status high-to-low edge NRST happened since last read RSTC_SR. least high-to-low transition NRST been detected since last read RSTC_SR. BODSTS: Brownout Detection Status brownout high-to-low transition happened since last read RSTC_SR. brownout high-to-low transition been detected since last read RSTC_SR. RSTTYP: Reset Type Reports cause last processor reset. Reading this RSTC_SR does reset this field.
RSTTYP
Reset Type Power-up Reset Watchdog Reset Software Reset User Reset Brownout Reset
Comments VDDCORE rising Watchdog fault occurred Processor reset required software NRST detected BrownOut reset occurred
NRSTL: NRST Level Registers NRST Level Master Clock (MCK). SRCMP: Software Reset Command Progress software command being performed reset controller. reset controller ready software command. software reset command being performed reset controller. reset controller busy.
6120C-ATARM-25-Oct-05
14.4.3
Reset Controller Mode Register RSTC_MR Read/Write
URSTIEN ERSTL URSTEN BODIEN
Register Name: Access Type:
URSTEN: User Reset Enable detection level NRST does generate User Reset. detection level NRST triggers User Reset. URSTIEN: User Reset Interrupt Enable USRTS RSTC_SR effect rstc_irq. USRTS RSTC_SR asserts rstc_irq URSTEN BODIEN: Brownout Detection Interrupt Enable BODSTS RSTC_SR effect rstc_irq. BODSTS RSTC_SR asserts rstc_irq. ERSTL: External Reset Length This field defines external reset length. external reset asserted during time 2(ERSTL+1) Slow Clock cycles. This allows assertion duration programmed between seconds. KEY: Password Should written value 0xA5. Writing other value this field aborts write operation.
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Real-time Timer (RTT)
15.1 Overview
Real-time Timer built around 32-bit counter used count elapsed seconds. generates periodic interrupt or/and triggers alarm programmed value.
15.2
Block Diagram
Figure 15-1. Real-time Timer
RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST RTTINCIEN RTT_SR RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS RTT_AR ALMV rtt_alarm
15.3
Functional Description
Real-time Timer used count elapsed seconds. built around 32-bit counter Slow Clock divided programmable 16-bit value. value programmed field RTPRES Real-time Mode Register (RTT_MR). Programming RTPRES 0x00008000 corresponds feeding real-time counter with signal Slow Clock 32.768 Hz). 32-bit counter count seconds, corresponding more than years, then roll over Real-time Timer also used free-running timer with lower time-base. best accuracy achieved writing RTPRES Programming RTPRES possible, result losing status events because status register cleared Slow Clock cycles after read. Thus configured trigger interrupt, interrupt occurs during Slow Clock cycles after reading RTT_SR. prevent several executions interrupt handler, interrupt must disabled interrupt handler re-enabled when status register clear.
6120C-ATARM-25-Oct-05
Real-time Timer value (CRTV) read time register RTT_VR (Real-time Value Register). this value updated asynchronously from Master Clock, advisable read this register twice same value improve accuracy returned value. current value counter compared with value written alarm register RTT_AR (Real-time Alarm Register). counter value matches alarm, ALMS RTT_SR set. alarm register maximum value, corresponding 0xFFFF_FFFF, after reset. RTTINC RTT_SR each time Real-time Timer counter incremented. This used start periodic interrupt, period being second when RTPRES programmed with 0x8000 Slow Clock equal 32.768 Reading RTT_SR status register resets RTTINC ALMS fields. Writing RTTRST RTT_MR immediately reloads restarts clock divider with programmed value. This also resets 32-bit counter. Figure 15-2. Counting
cycle cycle
RTPRES Prescaler
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR) ALMS (RTT_SR) Interface
read RTT_SR
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15.4 Real-time Timer (RTT) User Interface
Real-time Timer (RTT) Register Mapping
Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000
Table 15-1.
Offset 0x00 0x04 0x08 0x0C
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15.4.1
Real-time Timer Mode Register RTT_MR Read/Write
RTPRES RTPRES RTTRST RTTINCIEN ALMIEN
Register Name: Access Type:
RTPRES: Real-time Timer Prescaler Value Defines number SLCK periods required increment real-time timer. RTPRES defined follows: RTPRES Prescaler Period equal RTPRES Prescaler Period equal RTPRES. ALMIEN: Alarm Interrupt Enable ALMS RTT_SR effect interrupt. ALMS RTT_SR asserts interrupt. RTTINCIEN: Real-time Timer Increment Interrupt Enable RTTINC RTT_SR effect interrupt. RTTINC RTT_SR asserts interrupt. RTTRST: Real-time Timer Restart Reloads restarts clock divider with programmed value. This also resets 32-bit counter.
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15.4.2 Real-time Timer Alarm Register RTT_AR Read/Write
ALMV ALMV ALMV ALMV
Register Name: Access Type:
ALMV: Alarm Value Defines alarm value (ALMV+1) compared with Real-time Timer. 15.4.3 Real-time Timer Value Register RTT_VR Read-only
CRTV CRTV CRTV CRTV
Register Name: Access Type:
CRTV: Current Real-time Value Returns current value Real-time Timer.
6120C-ATARM-25-Oct-05
15.4.4
Real-time Timer Status Register RTT_SR Read-only
RTTINC ALMS
Register Name: Access Type:
ALMS: Real-time Alarm Status Real-time Alarm occurred since last read RTT_SR. Real-time Alarm occurred since last read RTT_SR. RTTINC: Real-time Timer Increment Real-time Timer been incremented since last read RTT_SR. Real-time Timer been incremented since last read RTT_SR.
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Periodic Interval Timer (PIT)
16.1 Overview
Periodic Interval Timer (PIT) provides operating system's scheduler interrupt. designed offer maximum accuracy efficient management, even systems with long response time.
16.2
Block Diagram
Figure 16-1. Periodic Interval Timer
PIT_MR
PIT_MR
PITIEN
PIT_SR
PITS
reset
pit_irq
12-bit Adder
read PIT_PIVR
20-bit Counter
Prescaler
MCK/16
CPIV
PIT_PIVR
PICNT
CPIV
PIT_PIIR
PICNT
6120C-ATARM-25-Oct-05
16.3
Functional Description
Periodic Interval Timer aims providing periodic interrupts operating systems. provides programmable overflow counter reset-on-read feature. built around counters: 20-bit CPIV counter 12-bit PICNT counter. Both counters work Master Clock /16. first 20-bit CPIV counter increments from programmable overflow value field Mode Register (PIT_MR). When counter CPIV reaches this value, resets increments Periodic Interval Counter, PICNT. status PITS Status Register (PIT_SR) rises triggers interrupt, provided interrupt enabled (PITIEN PIT_MR). Writing value PIT_MR does reset/restart counters. When CPIV PICNT values obtained reading Periodic Interval Value Register (PIT_PIVR), overflow counter (PICNT) reset PITS cleared, thus acknowledging interrupt. value PICNT gives number periodic intervals elapsed since last read PIT_PIVR. When CPIV PICNT values obtained reading Periodic Interval Image Register (PIT_PIIR), there effect counters CPIV PICNT, PITS. example, profiler read PIT_PIIR without clearing pending interrupt, whereas timer interrupt clears interrupt reading PIT_PIVR. enabled/disabled using PITEN PIT_MR register (disabled reset). PITEN only becomes effective when CPIV value Figure 16-2 illustrates counting. After Enable reset (PITEN= CPIV goes counting until value reached, then reset. restarts counting, only PITEN again. stopped when core enters debug state.
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Figure 16-2. Enabling/Disabling with PITEN
cycle restarts Prescaler Prescaler PITEN cycle
CPIV PICNT PITS (PIT_SR) Interface
read PIT_PIVR
6120C-ATARM-25-Oct-05
16.4
Periodic Interval Timer (PIT) User Interface
Periodic Interval Timer (PIT) Register Mapping
Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000
Table 16-1.
Offset 0x00 0x04 0x08 0x0C
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16.4.1 Periodic Interval Timer Mode Register PIT_MR Read/Write
PITIEN PITEN
Register Name: Access Type:
PIV: Periodic Interval Value Defines value compared with primary 20-bit counter Periodic Interval Timer (CPIV). period equal (PIV PITEN: Period Interval Timer Enabled Periodic Interval Timer disabled when value reached. Periodic Interval Timer enabled. PITIEN: Periodic Interval Timer Interrupt Enable PITS PIT_SR effect interrupt. PITS PIT_SR asserts interrupt. 16.4.2 Periodic Interval Timer Status Register PIT_SR Read-only
PITS
Register Name: Access Type:
PITS: Periodic Interval Timer Status Periodic Interval timer reached since last read PIT_PIVR. Periodic Interval timer reached since last read PIT_PIVR.
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16.4.3
Periodic Interval Timer Value Register PIT_PIVR Read-only
PICNT PICNT CPIV CPIV CPIV
Register Name: Access Type:
Reading this register clears PITS PIT_SR. CPIV: Current Periodic Interval Value Returns current value periodic interval timer. PICNT: Periodic Interval Counter Returns number occurrences periodic intervals since last read PIT_PIVR.
16.4.4
Periodic Interval Timer Image Register PIT_PIIR Read-only
PICNT PICNT CPIV CPIV CPIV
Register Name: Access Type:
CPIV: Current Periodic Interval Value Returns current value periodic interval timer. PICNT: Periodic Interval Counter Returns number occurrences periodic intervals since last read PIT_PIVR.
AT91SAM7X256/128 Preliminary
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Watchdog Timer (WDT)
17.1 Overview
Watchdog Timer used prevent system lock-up software becomes trapped deadlock. features 12-bit down counter that allows watchdog period seconds (slow clock 32.768 kHz). generate general reset processor reset only. addition, stopped while processor debug mode idle mode.
17.2
Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
write WDT_MR WDT_MR WDT_CR
reload
WDRSTT
12-bit Down Counter
WDT_MR reload
Current Value
1/128
SLCK
WDT_MR
WDRSTEN
wdt_fault Reset Controller)
WDUNF
reset
wdt_int
WDERR read WDT_SR reset
reset
WDFIEN
WDT_MR
6120C-ATARM-25-Oct-05
17.3
Functional Description
Watchdog Timer used prevent system lock-up software becomes trapped deadlock. supplied with VDDCORE. restarts with initial values processor reset. Watchdog built around 12-bit down counter, which loaded with value defined field Mode Register (WDT_MR). Watchdog Timer uses Slow Clock divided establish maximum Watchdog period seconds (with typical Slow Clock 32.768 kHz). After Processor Reset, value 0xFFF, corresponding maximum value counter with external reset generation enabled (field WDRSTEN after Backup Reset). This means that default Watchdog running reset, i.e., power-up. user must either disable setting WDDIS WDT_MR) does expect must reprogram meet maximum Watchdog period application requires. Watchdog Mode Register (WDT_MR) written only once. Only processor reset resets Writing WDT_MR register reloads timer with newly programmed mode parameters. normal operation, user reloads Watchdog regular intervals before timer underflow occurs, writing Control Register (WDT_CR) with WDRSTT Watchdog counter then immediately reloaded from WDT_MR restarted, Slow Clock divider reset restarted. WDT_CR register write-protected. result, writing WDT_CR without correct hard-coded effect. underflow does occur, "wdt_fault" signal Reset Controller asserted WDRSTEN Mode Register (WDT_MR). Moreover, WDUNF Watchdog Status Register (WDT_SR). prevent software deadlock that continuously triggers Watchdog, reload Watchdog must occur window defined WDT_MR: WDD; writing WDRSTT restarts Watchdog Timer. attempt restart Watchdog Timer range [WDV; WDD] results Watchdog error, even Watchdog disabled. WDERR updated WDT_SR "wdt_fault" signal Reset Controller asserted. Note that this feature disabled programming value greater than equal value. such configuration, restarting Watchdog Timer permitted whole range WDV] does generate error. This default configuration reset (the values equal). status bits WDUNF (Watchdog Underflow) WDERR (Watchdog Error) trigger interrupt, provided WDFIEN mode register. signal "wdt_fault" reset controller causes Watchdog reset WDRSTEN already explained reset controller programmer Datasheet. that case, processor Watchdog Timer reset, WDERR WDUNF flags reset. reset generated WDT_SR read, status bits reset, interrupt cleared, "wdt_fault" signal reset controller deasserted. Writing WDT_MR reloads restarts down counter. While processor debug state idle mode, counter stopped depending value programmed bits WDIDLEHLT WDDBGHLT WDT_MR.
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Figure 17-2. Watchdog Behavior
Watchdog Error Watchdog Underflow WDRSTEN Normal behavior Forbidden Window Permitted Window WDT_CR WDRSTT WDRSTEN
Watchdog Fault
6120C-ATARM-25-Oct-05
17.4
Watchdog Timer (WDT) User Interface
Watchdog Timer (WDT) Register Mapping
Register Control Register Mode Register Status Register Name WDT_CR WDT_MR WDT_SR Access Write-only Read/Write Once Read-only Reset Value 0x3FFF_2FFF 0x0000_0000
Table 17-1.
Offset 0x00 0x04 0x08
17.4.1
Watchdog Timer Control Register WDT_CR Write-only
WDRSTT
Register Name: Access Type:
WDRSTT: Watchdog Restart effect. Restarts Watchdog. KEY: Password Should written value 0xA5. Writing other value this field aborts write operation.
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17.4.2 Watchdog Timer Mode Register WDT_MR Read/Write Once
WDIDLEHLT WDDBGHLT WDDIS WDRPROC WDRSTEN WDFIEN
Register Name: Access Type:
WDV: Watchdog Counter Value Defines value loaded 12-bit Watchdog Counter. WDFIEN: Watchdog Fault Interrupt Enable Watchdog fault (underflow error) effect interrupt. Watchdog fault (underflow error) asserts interrupt. WDRSTEN: Watchdog Reset Enable Watchdog fault (underflow error) effect resets. Watchdog fault (underflow error) triggers Watchdog reset. WDRPROC: Watchdog Reset Processor WDRSTEN Watchdog fault (underflow error) activates resets. WDRSTEN Watchdog fault (underflow error) activates processor reset. WDD: Watchdog Delta Value Defines permitted range reloading Watchdog Timer. Watchdog Timer value less than equal WDD, writing WDT_CR with WDRSTT restarts timer. Watchdog Timer value greater than WDD, writing WDT_CR with WDRSTT causes Watchdog error. WDDBGHLT: Watchdog Debug Halt Watchdog runs when processor debug state. Watchdog stops when processor debug state. WDIDLEHLT: Watchdog Idle Halt Watchdog runs when system idle mode. Watchdog stops when system idle state. WDDIS: Watchdog Disable Enables Watchdog Timer. Disables Watchdog Timer.
6120C-ATARM-25-Oct-05
17.4.3
Watchdog Timer Status Register WDT_SR Read-only
WDERR WDUNF
Register Name: Access Type:
WDUNF: Watchdog Underflow Watchdog underflow occurred since last read WDT_SR. least Watchdog underflow occurred since last read WDT_SR. WDERR: Watchdog Error Watchdog error occurred since last read WDT_SR. least Watchdog error occurred since last read WDT_SR.
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
Voltage Regulator Mode Controller (VREG)
18.1 Overview
Voltage Regulator Mode Controller contains Read/Write register, Voltage Regulator Mode Register. offset 0x60 with respect System Controller offset. This register controls Voltage Regulator Mode. Setting PSTDBY (bit puts Voltage Regulator Standby Mode Low-power Mode. reset, PSTDBY reset, wake Voltage Regulator Normal Mode.
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18.2
Voltage Regulator Power Controller (VREG) User Interface
Voltage Regulator Power Controller Register Mapping
Register Voltage Regulator Mode Register Name VREG_MR Access Read/Write Reset Value
Table 18-1.
Offset 0x60
18.2.1
Voltage Regulator Mode Register VREG_MR Read/Write
PSTDBY
Register Name: Access Type:
PSTDBY: Periodic Interval Value Voltage regulator normal mode. Voltage regulator standby mode (low-power mode).
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Memory Controller (MC)
19.1 Overview
Memory Controller (MC) manages controls accesses requested masters, typically ARM7TDMI processor Peripheral Controller. features arbiter, address decoder, abort status, misalignment detector Embedded Flash Controller.
19.2
Block Diagram
Figure 19-1. Memory Controller Block Diagram
Memory Controller ARM7TDMI Processor Embedded Flash Controller Abort Status Internal Internal Flash
Abort
EMAC
Arbiter
Misalignment Detector
Address Decoder
User Interface
Peripheral Controller Peripheral Peripheral
Bridge
From Master Slave
Peripheral
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19.3
Functional Description
Memory Controller handles internal arbitrates accesses three masters. made arbiter address decoder abort status misalignment detector Embedded Flash Controller handles only little-endian mode accesses. masters work little-endian mode only.
19.3.1
Arbiter Memory Controller simple, hard-wired priority arbiter that gives control three masters. EMAC highest priority; Peripheral Controller medium priority; processor lowest one.
19.3.2
Address Decoder Memory Controller features Address Decoder that first decodes four highest bits 32-bit address defines three separate areas: 256-Mbyte address space internal memories 256-Mbyte address space reserved embedded peripherals undefined address space 3584M bytes representing fourteen 256-Mbyte areas that return Abort accessed Figure 19-2 shows assignment 256-Mbyte memory areas. Figure 19-2. Memory Areas
256M Bytes 0x0000 0000
0x0FFF FFFF 0x1000 0000
Internal Memories
256MBytes 3,584 Mbytes
Undefined (Abort)
0xEFFF FFFF
256M Bytes
0xF000 0000
0xFFFF FFFF
Peripherals
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19.3.2.1 Internal Memory Mapping Within Internal Memory address space, Address Decoder Memory Controller decodes eight more address bits allocate 1-Mbyte address spaces embedded memories. allocated memories accessed along 1-Mbyte address space repeated times within this address space, equaling bytes divided size memory. When address access undefined within internal memory area, Address Decoder returns Abort master. Figure 19-3. Internal Memory Mapping
0x0000 0000 Internal Memory Area
0x000F FFFF
Bytes
0x0010 0000
0x001F FFFF
Internal Memory Area Internal Flash Internal Memory Area Internal SRAM Internal Memory Area Internal SRAM
Bytes
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000
Bytes
Bytes
Undefined Areas (Abort)
0x0FFF FFFF
252M bytes
19.3.2.2
Internal Memory Area first bytes Internal Memory Area contain processor exception vectors, particular, Reset Vector address 0x0. Before execution remap command, on-chip Flash mapped into Internal Memory Area that ARM7TDMI reaches executable instruction contained Flash. After remap command, internal SRAM address 0x0020 0000 mapped into Internal Memory Area memory mapped into Internal Memory Area accessible both original location address 0x0.
19.3.3
Remap Command After execution, Remap Command causes Internal SRAM accessed through Internal Memory Area vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) mapped from address address 0x20, Remap Command allows user redefine dynamically these vectors under software control. Remap Command accessible through Memory Controller User Interface writing MC_RCR (Remap Control Register) field one. Remap Command cancelled writing MC_RCR field one, which acts toggling command. This allows easy debug user-defined boot sequence offering simple chip same configuration after reset.
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19.3.4
Abort Status There reasons abort occur: access undefined address access misaligned address. When abort occurs, signal sent back masters, regardless which generated access. However, only ARM7TDMI take abort signal into account, only under condition that generating access. Peripheral Controller EMAC handle abort input signal. Note that connections represented Figure 19-1. facilitate debug fault analysis operating system, Memory Controller integrates Abort Status register set. full 32-bit wide abort address saved MC_AASR. Parameters access saved MC_ASR include: size request (field ABTSZ) type access, whether data read write, code fetch (field ABTTYP) whether access accessing undefined address (bit UNDADD) misaligned address (bit MISADD) source access leading last abort (bits MST_EMAC, MST_PDC MST_ARM) whether abort occurred each master since last read register (bits SVMST_EMAC, SVMST_PDC SVMST_ARM) unless this information loaded bits case Data Abort from processor, address data access stored. This useful, searching which address generated abort would require disassembling instructions full knowledge processor context. case Prefetch Abort, address have changed, prefetch abort pipelined processor. processor takes prefetch abort into account only read instruction executed probable that several aborts have occurred during this time. Thus, this case, preferable content Abort Link register processor.
19.3.5
Embedded Flash Controller Embedded Flash Controller added Memory Controller ensures interface flash block with 32-bit internal bus. allows increase performance Thumb Mode Code Fetch with system 32-bit buffers. also manages with programming, erasing, locking unlocking sequences thanks full commands.
19.3.6
Misalignment Detector Memory Controller features Misalignment Detector that checks consistency accesses. each access, regardless master, size access bits address checked. type access word (32-bit) bits type access half-word (16-bit) abort returned master access cancelled. Note that accesses processor when fetching instructions checked. misalignments generally software bugs leading wrong pointer handling. These bugs particularly difficult detect debug phase.
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requested address saved Abort Status Register address instruction generating misalignment saved Abort Link Register processor, detection this kind software bugs simplified.
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19.4
Memory Controller (MC) User Interface
Base Address: 0xFFFFFF00 Table 19-1.
Offset 0x00 0x04 0x08 0x10-0x5C 0x60
Memory Controller (MC) Register Mapping
Register Remap Control Register Abort Status Register Abort Address Status Register Reserved Configuration Registers Section "Embedded Flash Controller (EFC)", page Name MC_RCR MC_ASR MC_AASR Access Write-only Read-only Read-only Reset State
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19.4.1 Remap Control Register MC_RCR Write-only
Register Name: Access Type: Offset:
RCB: Remap Command effect. This Command acts toggle basis: writing alternatively cancels restores remapping page zero memory devices.
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19.4.2
Abort Status Register MC_ASR Read-only 0x04
ABTTYP MISADD SVMST_ARM MST_ARM SVMST_PDC MST_PDC ABTSZ UNDADD SVMST_EMAC MST_EMAC
Register Name: Access Type: Reset Value: Offset:
UNDADD: Undefined Address Abort Status last abort access undefined address address space. last abort access undefined address address space. MISADD: Misaligned Address Abort Status last aborted access address misalignment. last aborted access address misalignment. ABTSZ: Abort Size Status
ABTSZ Abort Size Byte Half-word Word Reserved
ABTTYP: Abort Type Status
ABTTYP Abort Type Data Read Data Write Code Fetch Reserved
MST_EMAC: EMAC Abort Source last aborted access EMAC. last aborted access EMAC.
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MST_PDC: Abort Source last aborted access PDC. last aborted access PDC. MST_ARM: Abort Source last aborted access ARM. last aborted access ARM. SVMST_EMAC: Saved EMAC Abort Source abort EMAC occurred since last read MC_ASR notified MST_EMAC. least abort EMAC occurred since last read MC_ASR. SVMST_PDC: Saved Abort Source abort occurred since last read MC_ASR notified MST_PDC. least abort occurred since last read MC_ASR. SVMST_ARM: Saved Abort Source abort occurred since last read MC_ASR notified MST_ARM. least abort occurred since last read MC_ASR.
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19.4.3
Abort Address Status Register MC_AASR Read-only 0x08
ABTADD ABTADD ABTADD ABTADD
Register Name: Access Type: Reset Value: Offset:
ABTADD: Abort Address This field contains address last aborted access.
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Embedded Flash Controller (EFC)
20.0.1 Overview Embedded Flash Controller (EFC) part Memory Controller ensures interface Flash block with 32-bit internal bus. increases performance Thumb Mode Code Fetch with system 32-bit buffers. also manages programming, erasing, locking unlocking sequences using full commands.
20.1
20.1.1
Functional Description
Embedded Flash Organization Embedded Flash interfaces directly 32-bit internal bus. composed several interfaces: memory plane organized several pages same size 32-bit read buffers used code read optimization (see "Read Operations" page 100). write buffer that manages page programming. write buffer size equal page size. This buffer write-only accessible along MByte address space, that each word written final address (see "Write Operations" page 102). Several lock bits used protect write erase operations lock regions. lock region composed several consecutive pages, each lock region associated lock bit. Several general-purpose bits. Each controls specific feature device. Refer product definition section assignment. Embedded Flash size, page size lock region organization described product definition section.
Table 20-1.
Product Specific Lock General-purpose Bits
AT91SAM7X128 Denomination Number General-purpose bits Number Lock Bits
AT91SAM7X256
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Figure 20-1. Embedded Flash Memory Mapping
Page
Flash Memory
Start Address Lock Region Lock Region
Lock Lock
Page (m-1)
Lock Region (n-1)
32-bit wide
Lock
Page (n-1)*m
Page (n*m-1)
20.1.2
Read Operations optimized controller manages embedded Flash reads. system 32-bit buffers added order start access following address during second read, thus increasing performance when processor running Thumb mode (16-bit instruction set). Figure 20-2, Figure 20-3 Figure 20-4. This optimization concerns only Code Fetch Data. read operations performed with without wait state. wait states programmed field (Flash Wait State) Flash Mode Register MC_FMR (see Flash Mode Register" page 110). Defining enables single-cycle access embedded Flash. Flash memory accessible through 32-bit reads. Flash block size smaller than address space reserved internal memory area, embedded Flash wraps around address space appears repeated within
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Figure 20-2. Code Read Optimization Thumb Mode
Master Clock
Request (16-bit) Code Fetch @Byte Flash Access @Byte @Byte @Byte @Byte @Byte @Byte @Byte @Byte
Bytes
Bytes
Bytes 8-11
Bytes 12-15
Bytes 16-19
Buffer bits)
Bytes
Bytes
Bytes 8-11
Bytes 12-15
Data
Bytes
Bytes
Bytes
Bytes
Bytes
Bytes 10-11
Bytes 12-13
Bytes 14-15
Note:
When equal accesses performed single-cycle access.
Figure 20-3. Code Read Optimization Thumb Mode
Wait State Cycle Wait State Cycle Wait State Cycle Wait State Cycle
Master Clock
Request (16-bit) Code Fetch @Byte Flash Access @Byte @Byte @Byte @Byte @Byte @Byte @Byte
Bytes
Bytes
Bytes 8-11
Bytes 12-15
Buffer bits)
Bytes
Bytes
Bytes 8-11
Data
Bytes
Bytes
Bytes
Bytes
Bytes
Bytes 10-11
Bytes 12-13
Note:
When equal case sequential reads, accesses performed single-cycle access (except first one).
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Figure 20-4. Code Read Optimization Thumb Mode
Wait State Cycles Wait State Cycles Wait State Cycles Wait State Cycles
Master Clock
Request (16-bit) Code Fetch @Byte
Flash Access
Bytes
Bytes
Bytes 8-11
Bytes 12-15
Buffer bits)
Bytes
Bytes
Bytes 8-11
Data
10-11
12-13
Note:
When equal case sequential reads, first access takes cycles, second access cycle, third access cycles, fourth access cycle, etc.
20.1.3
Write Operations internal memory area reserved embedded Flash also written through writeonly latch buffer. Write operations take into account only lowest address bits thus wrap around within internal memory area address space appear repeated 1024 times within Write operations prevented programming Memory Protection Unit product. Writing 8-bit 16-bit data allowed lead unpredictable data corruption. Write operations performed number wait states equal number wait states read operations except (see Flash Mode Register" page 110).
20.1.4
Flash Commands offers command manage programming memory flash, locking unlocking lock sectors, consecutive programming locking, full Flash erasing. Table 20-2.
Command Write page Lock Write Page Lock Clear Lock Erase General-purpose Clear General-purpose Security
Commands
Value 0x01 0x02 0x03 0x04 0x08 0x0B 0x0D 0x0F Mnemonic SGPB CGPB
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these commands, field FCMD MC_FCR register written with command number. soon MC_FCR register written, FRDY flag automatically cleared. Once current command achieved, then FRDY flag automatically set. interrupt been enabled setting FRDY MC_FMR, interrupt line Memory Controller activated. commands protected same keyword, which written eight highest bits MC_FCR register. Writing MC_FCR with data that does contain correct and/or with invalid command effect memory plane; however, PROGE flag MC_FSR register. This flag automatically cleared read access MC_FSR register. When current command writes erases page locked region, command effect whole memory plane; however, LOCKE flag MC_FSR register. This flag automatically cleared read access MC_FSR register.
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Figure 20-5. Command State Chart
Read Status: MC_FSR
Check FRDY flag
Write FCMD PAGENB MC_FCR
Read Status: MC_FSR
Check FRDY flag
Check LOCKE flag
Locking region violation
Check PROGE flag
keyword violation and/or Invalid command
Command Successful
order guarantee valid operations Flash memory, field Flash Microsecond Cycle Number (FMCN) Flash Mode Register MC_FMR must correctly programmed (see Flash Mode Register" page 110).
20.1.4.1
Flash Programming Several commands used program Flash. Flash technology requires that erase must done before programming. entire memory plane erased same time, page automatically erased clearing NEBP MC_FMR register before writing command MC_FCR register.
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setting NEBP MC_FMR register, page programmed several steps been erased before (see Figure 20-6). Figure 20-6. Example Partial Page Programming:
bits wide bits wide bits wide
words
words
words
words
Step Erase Flash Page erased
Step Programming second part Page (NEBP
Step Programming third part Page (NEBP
After programming, page (the whole lock region) locked prevent miscellaneous write erase sequences. lock automatically after page programming using WPL. Data written stored internal latch buffer. size latch buffer corresponds page size. latch buffer wraps around within internal memory area address space appears repeated number pages
Note: Writing 8-bit 16-bit data allowed lead unpredictable data corruption.
Data written latch buffer before programming command written Flash Command Register MC_FCR. sequence follows: Write full page, page address, within internal memory area address space using only 32-bit access. Programming starts soon page number programming command written Flash Command Register. FRDY Flash Programming Status Register (MC_FSR) automatically cleared. When programming completed, FRDY Flash Programming Status Register (MC_FSR) rises. interrupt enabled setting FRDY MC_FMR, interrupt line Memory Controller activated. errors detected MC_FS
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